AIC1341 High Performance, Triple-Output, AutoTracking Combo Controller n FEATURES n GENERAL DESCRIPTION l Provide Triple Accurate Regulated Voltages The AIC1341 combines a synchronous voltage l Optimized Voltage-Mode PWM Control mode PWM controller with two linear controllers l Dual N-Channel MOSFET Synchronous Drivers as well as the monitoring and protection functions l Fast Transient Response in this chip. The PWM controller regulates the l Adjustable Over Current Protection using RDS(ON). No External Current Sense Resistor Required. output voltage with a synchronous rectified stepdown converter. The built-in N-Channel MOSFET drivers also help to simplify the design of step- l Programmable Softstart Function l 200KHz Free-Running Oscillator l Robust Outputs Auto-Tracking Characteristics The PWM controller features over current protec- l Sink and Source Capabilities with External Circuit tion using RDS(ON). It improves efficiency and saves down converter. It is able to power CPUs, GPUs, memories, chipsets and multi-voltage applications. cost, as there is no expensive current sense resis- n APPLICATIONS tor required. l Advanced PC Mboards l Information PCs l Servers and Workstations that regulates power for multiple system I/O. Out- l Internet Appliances put voltage of both linear regulators can also be l PC Add-On Cards adjusted by means of the external resistor divider. l DDR Termination Both linear regulators feature current limit. For a Two built-in adjustable linear controllers drive an external MOSFETs to form two linear regulators system I/O requires current less than 500mA, the AIC1340 is recommended for saving one external MOSFET. The programmable soft-start design provodes a controlled output voltage rise, which limits the current rate during power on time. The shutdown function is also provided for disabling the combo controller. Analog Integrations Corporation 4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC DS-1341-00 May 24, 01 TEL: 886-3-5772500 FAX: 886-3-5772510 www.analog.com.tw 1 AIC1341 n TYPICAL APPLICATION CIRCUIT AIC1341CS +12VIN VCC +5VIN 4 14 5 2 SS 1 OCSET UGATE + GND Q1 PHASE VOUT1 +3.3VIN VIN2 GATE3 VOUT3 7 16 LGATE + Q2 10 FB3 15 11 PGND + +3.3VIN FB1 13 GATE2 8 VOUT2 FB2 6 + 12 COMP1 14 3 SD GND Typical Triple-Output Application n ORDERING INFORMATION ORDER NUMBER AIC1341-XX PACKAGING TYPE S: SMALL OUTLINE TEMPERATURE RANGE C: O °C~+70°C AIC1341CS (SO 16) PIN CONFIGURATION PHASE 1 UGATE 2 16 LGATE 15 PGND SD 3 14 OCSET VCC 4 13 F B 1 SS 5 FB2 6 12 COMP1 11 F B 3 VIN2 7 10 GATE3 GATE2 8 9 GND 2 AIC1341 n ABSOLUTE MAXIMUM RATING Absolute Maximum Ratings Supply Voltage (VCC).............................................................................................................. 15V UGATE....................................................................................................GND - 0.3V to VCC + 0.3V LGATE ....................................................................................................GND - 0.3V to VCC + 0.3V Input Output and I/O Voltage .................................................................................GND - 0.3V to 7V Operating Conditions Ambient Temperature Range ........................................................................................ 0° C to 85°C Maximum Operating Junction Temperature ............................................................................. 100°C Supply Voltage, VCC....................................................................................................... 15V±10% Thermal Information Thermal Resistance θJA (°C/W) SOIC Package ....................................................................................................... 100°C/W Maximum Junction Temperature (Plastic Package).................................................................. 150°C Maximum Storage Temperature Range.......................................................................-65°C to 150°C Maximum Lead Temperature (Soldering 10s)........................................................................... 300°C n TEST CIRCUIT Refer to APPLICATION CIRCUIT. n ELECTRICAL CHARACTERISTICS (Vcc=12V, T J=25°C, Unless otherwise specified) PARAMETER TEST CONDITIONS SYMBOL UGATE, LGATE, GATE2 and GATE3 open ICC MIN. TYP. MAX. UNIT 1.8 5 mA VCC SUPPLY CURRENT Supply Current POWER ON RESET Rising VCC Threshold VOCSET=4.5V VCCTHR 8.6 9.5 10.4 V Falling VCC Threshold VOCSET=4.5V VCCTHF 8.2 9.2 10.2 V Rising VIN2 Under-Voltage Threshold VIN2THR 2.5 2.6 2.7 V VIN2 Under-Voltage Hysteresis VIN2HYS 130 mV Rising VOCSET1 Threshold VOCSETH 1.3 V 3 AIC1341 n ELECTRICAL CHARACTERISTICS (Continued) SYMBOL MIN. TYP. MAX. UNIT F 170 200 230 KHz FB2 Reference Voltage VREF2 1.245 1.270 1.295 V FB3 Reference Voltage VREF3 1.250 1.275 1.300 V +2.5 % 80 % PARAMETER TEST CONDITIONS OSCILLATOR and REFERENCE Free Running Frequency LINEAR CONTROLLER Regulation 0 < IGATE2/3 < 10mA Under-Voltage Level FB2/3 falling -2.5 FB2/3UV 70 PWM CONTROLLER ERROR AMPLIFIER DC GAIN Gain Bandwidth Product Slew Rate COMP1=10pF 76 dB GBWP 11 MHz SR 6 V/µS PWM CONTROLLER GATE DRIVER Upper Drive Source VCC=12V, VUGATE=11V RUGH 5.2 6.5 Ω Upper Drive Sink VCC=12V, VUGATE =1V RUGL 3.3 5 Ω Lower Drive Source VCC=12V, VLGATE=11V RLGH 4.1 6 Ω Lower Drive Sink VCC=12V, VLGATE=1V RLGL 3 5 Ω ISS 11 PROTECTION Soft-Start Current Chip Shutdown Soft Start Threshold µA 1.0 V 4 AIC1341 n PIN DESCRIPTIONS Pin 1: Pin 2: Pin 3: Pin 4: Pin 5: Pin 6: Pin 7: PHASE: Over-current detection pin. Connect the PHASE pin to source of the external high-side NMOSFET. This pin detects the voltage drop across the high-side N-MOSFET RDS(ON) for overcurrent protection. UGATE: External high-side N-MOSFET gate drive pin. Connect UGATE to gate of the external high-side N-MOSFET. SD: VCC: SS: FB2: VIN2: To shut down the system, active high or floating. If connecting a resistor to ground, keep the resistor less than 4.7KΩ The chip power supply pin. It also provides the gate bias charge for all the MOSFETs controlled by the IC. Recommended supply voltage is 12V. Soft-start pin. Connect a capacitor from this pin to ground. This capacitor, along with an internal 10µA (typically) current source, sets the soft-start interval of the converter. Pulling this pin low will shut down the IC. Connect this pin to a resistor divider to set the linear regulator output voltage. This pin supplies power to the internal regulator. Connect this pin to a suitable 3.3V source. Additionally, this pin is used to monitor the 3.3V supply. If, following a start-up cycle, the voltage drops below 2.6V (typically), the chip shuts down. A new softstart cycle is initiated upon re- turn of the 3.3V supply above the under-voltage threshold. Pin 8: GATE2: Linear Controller output drive pin. This pin can drive either a Darlington NPN transistor or a Nchannel MOSFET. Pin 9: GND: Signal GND for IC. All voltage levels are measured with respect to this pin. Pin 10: GATE3: Linear Controller output drive pin. This pin can drive either a Darlington NPN transistor or an Nchannel MOSFET. Pin 11: FB3 Negative feedback pin for the linear controller error amplifier connect this pin to a resistor divider to set the linear controller output voltage. Pin 12: COMP1 External compensation pin. This pin is connected to error amplifier output and PWM comparator. A RC network is connected to FB1 to compensate the voltage control feedback loop of the converter. Pin 13: FB1 The error amplifier inverting input pin. The FB1 pin and COMP1 pin are used to compensate the voltage-control feedback loop. Pin 14: OCSET: Current limit sense pin. Connect a resistor ROCSET from this pin to the drain of the external high-side N-MOSFET. ROCSET, an internal 200µA current source (IOCSET ), and the upper N-MOSFET onresistance (RDS(ON)) set the overcurrent trip point according to the following equation: I PEAK = I OCSET × ROCSET RDS(ON) 5 AIC1341 Pin 15: PGND: Driver power GND pin. PGND should be connected to a low impedance ground plane in close to lower N-MOSFET source. Pin 16: LGATE: Lower N-MOSFET gate drive pin. n TYPICAL PERFORMANCE CHARACTERISTICS UGATE UGATE LGATE LGATE Fig.1 The gate drive waveforms FAULT SS VOUT1 =3.5V SS VOUT1 =2V Over Load Applied Inductor Current 10A/div Fig.2 Over-Current Operation on Inductor VOUT1 =1.3V Fig.3 Soft start initiates PWM Output 6 AIC1341 n TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VOUT1 VOUT3 ( 2mV/div) 2.0VDC 5A to 12A Load Step 1A to 2A Load Step Fig.4 Transient Response of PWM Output Fig.5 Transient Response of Linear Controller n BLOCK DIAGRAM VCC VIN2 SS FB3 + + + GATE3 LUV + OCSET 1.3V 9.5V 200uA + 0.3V + 2.6V + GATE2 SS 1.26V POR FB2 INHIBIT OC1 + PHASE VCC COUNT 3 LUV 3.6V OC1 S R - S UGATE Q R + Q POR + GATE CONTROL 5V R S 10uA 0.2V PWM COMP Q VCC R + 200KHz OSCILLATOR SS SS SLOW DISCHARGE 4V LGATE PGND + FAST DISCHARGE 1.3V 20uA 5V 70K GND ERROR AMP SD FB1 COMP1 7 AIC1341 n DESCRIPTION The AIC1341 is designed for applications with multiple voltage demand. This IC has one PWM controller and two linear controllers. The PWM controller is designed to regulate the voltage (V OUT1) by driving 2 MOSFETs (B y UGATE and LGATE) in a synchronous rectified buck converter configuration. The voltage is regulated to a level, which is decided by a resistor devide network. The Power-On Reset (POR) function continually monitors the input supply voltage +12V at VCC pin, the 5V input voltage at OCSET pin, and the 3.3V input at VIN2 pin. The POR function initiates soft-start operation after all three input supply voltage exceeds their POR thresholds. Soft-Start The POR function initiates the soft-start sequence. Initially, the voltage on SS pin rapidly increases to approximate 1V. Then an internal 10µA current source charges an external capacitor (CSS) on the SS pin to 4V. As the SS pin voltage slews from 1V to 4V, the PWM error amplifier reference input (Non-inverting terminal) and output (COMP1 pin) is clamped to a level proportional to the SS pin voltage. As the SS pin voltage slew from 1V to 4V, the output clamp generates PHASE pulses of increasing width that charge the output capacitors. Additionally both linear regulator’s reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a controlled output voltage smooth rise. cient voltage the input reference clamp slows the rate of output voltage rise. Over-Current Protection All outputs are protected against excessive overcurrent. The PWM controller uses upper MOSFET’s on-resistance, RDS(ON) to monitor the current for protection against shorted outputs. Both the linear regulator and controller monitor FB2 and FB3 for under-voltage to protect against excessive current. When the voltage across Q1 (ID • RDS(ON)) exceeds the level (200µA•ROCSET ), this signal inhibit all outputs. Discharge soft-start capacitor (Css) with 10µA current sink, and increments the counter. Css recharges and initiates a soft-start cycle again until the counter increments to 3. This sets the fault latch to disable all outputs. Fig. 2 illustrates the over-current protection until an over load on OUT1. Should excessive current cause FB2 or FB3 to fall below the linear under-voltage threshold, the LUV signal sets the over-current latch if Css is fully charged. Cycling the bias input power off then on reset the counter and the fault latch. The over-current function for PWM controller will trip at a peak inductor current (IPEAK) determined by: IPEAK = Fig.3 shows the soft-start sequence for the typical application. The internal oscillator’s triangular waveform is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse width on PHASE pin increases. The interval of increasing pulse width continues until output reaches sufficient voltage to transfer control to the input reference clamp. Each linear output (V OUT2 and VOUT3) initially follows a ramp. When each output reaches suffi- IOCSET × R OCSET R DS(ON) The OC trip point varies with MOSFET’s temperature. To avoid over-current tripping in the normal operating load range, determine the ROCSET resistor from the equation above with: 1. The maximum RDS(ON) at the highest junction. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK > IOUT(MAX ) + (inductor ripple current) /2. 8 AIC1341 Shutdown Q1, Q2 loop. The GND and PGND pins Compatible with the TTL logic level, by holding the should be shorted right at the IC. This help to SD (pin3) pin low will activate the controller. If minimize internal ground disturbances in the connecting a resistor to ground, make sure the IC and prevents differences in ground potential resistor is less than 4.7KΩ for normal operation. from disrupting internal circuit operation. 5) The wiring traces from the control IC to the Layout Considerations MOSFET gate and source should be sized to Any inductance in the switched current path gen- carry 1A current. Locate COUT2 close to the erates a large voltage spike during the switching AIC1341 IC. interval. The voltage spikes can degrade efficiency, 6) The Vcc pin should be decoupled directly to radiate noise into the circuit, and lead to device GND by a 1µF ceramic capacitor, trace over-voltage stress. Careful component selection lengths should be as short as possible. and tight layout of critical components, and short, wide metal trace minimize the voltage spike. A multi-layer printed circuit board is recom- 1) A ground plane should be used. Locate the mended. Figure 6 shows the connections of the input capacitors (CIN) close to the power critical components in the converter. The CIN and switches. Minimize the loop formed by CIN, COUT could each represent numerous physical ca- the upper MOSFET (Q1) and the lower pacitors. Dedicate one solid layer for a ground MOSFET (Q2) as possible. Connections plane and make all critical component ground should be as wide as short as possible to connections with vias to this layer. minimize loop inductance. 2) The connection between Q1, Q2 and output inductor should be as wide as short as practi- PWM Output Capacitors cal. Since this connection has fast voltage The load transient for the microprocessor core re- transitions will easily induce EMI. quires high quality capacitors to supply the high 3) The output capacitor (COUT ) should be locat- slew rate (di/dt) current demand. ed as close the load as possible. Because The ESR (equivalent series resistance) and ESL minimize the transient load magnitude for high (equivalent series inductance) parameters rather slew rate requires low inductance and resis- than actual capacitance determine the buck ca- tance in circuit board pacitor values. For a given transient load magni- 4) The AIC1341 is best placed over a quiet ground plane area. The GND pin should be connected to the groundside of the output ca- tude, the output voltage transient change due to the output capacitor can be note by the following equation: ∆IOUT , ∆T pacitors. Under no circumstances should ∆VOUT = ESR × ∆IOUT + ESL × GND be returned to a ground inside the CIN, ∆IOUT is transient load current step. where 9 AIC1341 + +12V VCC +3.3VIN GND VIN2 OCSET GATE3 UGATE +5VIN + Q3 + C IN Q1 VOUT3 PHASE + LOUT COUT3 VOUT + LGATE COUT Q2 Q4 GATE2 PGND SS V OUT2 Css + COUT2 Power Plane Layer Circuit Plane Layer Via Connection to Ground Plane Fig.6 Printed circuit board power planes and islands After the initial transient, the ESL dependent term The response time to a transient is different for the drops off. Because the strong relationship be- application of load and remove of load. tween output capacitor ESR and output load transient, the output capacitor is usually chosen for ESR, not for capacitance value. A capacitor with L × ∆IOUT L × ∆IOUT , tFALL = . VIN − VOUT VOUT Where ∆IOUT is transient load current step. tRISE = suitable ESR will usually have a larger capacitance value than is needed for energy storage. In a typical 5V input, 2V output application, a 3µH A common way to lower ESR and raise ripple cur- inductor has a 1A/µS rise time, resulting in a 5µS rent capability is to parallel several capacitors. In delay in responding to a 5A load current step. To most case, multiple electrolytic capacitors of optimize performance, different combinations of small case size are better than a single large input and output voltage and expected loads may case capacitor. require different inductor value. A smaller value of Output Inductor Selection Inductor value and type should be chosen based on output slew rate requirement, output ripple requirement and expected peak current. Inductor value is primarily controlled by the required current response time. The AIC1341 will provide either 0% or 85% duty cycle in response to a load transient. inductor will improve the transient response at the expense of increase output ripple voltage and inductor core saturation rating. Peak current in the inductor will be equal to the maximum output load current plus half of inductor ripple current. The ripple current is approximately equal to: 10 AIC1341 I RIPPLE = (V IN − VOUT) × VOUT ; f × L × VIN dissipated by the AIC1341. However, the gate charge increases the switching interval, tSW, which increase the upper MOSFET switching losses. f = 200KHz oscillator frequency. Ensure that both MOSFETs are within their The inductor must be able to withstand peak cur- maximum junction temperature at high ambient rent without saturation, and the copper resistance temperature by calculating the temperature rise in the winding should be kept as low as possible according to package thermal resistance specifi- to minimize resistive power loss cations. IOUT × VIN × tSW × f 2 × RDS(ON) × (1 − D) PUPPER = IOUT 2 × RDS(ON) × D + Input Capacitor Selection Most of the input supply current is supplied by the PLOWER = IOUT 2 input bypass capacitor, the resulting RMS current The equations above do not model power loss due flow in the input capacitor will heat it up. Use a to the reverse recovery of the lower MOSFET’s mix of input bulk capacitors to control the voltage body diode. overshoot across the upper MOSFET. The ce- The RDS(ON) is different for the two previous equa- ramic capacitance for the high frequency decou- tions even if the type devices is used for both. pling should be placed very close to the upper This is because the gate drive applied to the upper MOSFET to suppress the voltage induced in the MOSFET is different than the lower MOSFET. parasitic circuit impedance. The buck capacitors Logic level MOSFETs should be selected based to supply the RMS current is approximate equal on on-resistance considerations, RDS(ON) to: be chosen base on input and output voltage, al- IRMS = (1− D) × D × I2 OUT + , where D = 1 VIN × D × 12 f × L 2 VOUT VIN The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage. should lowable power dissipation and maximum required output current. Power dissipation should be calculated based primarily on required efficiency or allowable thermal dissipation. Rectifier Schottky diode is a clamp that prevent the loss parasitic MOSFET body diode from conducting during the dead time between the turn off of the lower MOSFET and the turn on of the upper PWM MOSFET Selection MOSFET. The diode’s rated reverse breakdown voltage must be greater than twice the maximum In high current PWM application, the MOSFET input voltage. power dissipation, package type and heatsink are the dominant design factors. The conduction loss is the only component of power dissipation for the lower MOSFET, since it turns on into near zero voltage. The upper MOSFET has conduction loss Linear Controller MOSFET Selection The power dissipated in a linear regulator is : PLINEAR = IOUT × (VIN2 − VOUT) and switching loss. The gate charge losses are Select a package and heatsink that maintains proportional to the switching frequency and are junction temperature below the maximum rating 11 AIC1341 while operation at the highest expected ambient Notes temperature. VOUT1 - The PWM output VOUT2 - The linear controller dominated by FB2, Linear Output Capacitor The output capacitors for the linear controller GATE2 and VIN2 VOUT3 - The linear controller dominated by FB3 provide dynamic load current. The linear controller and uses dominant pole compensation integrated in GATE3 the error amplifier and is insensitive to output ca- All the designators mentioned above are refering pacitor selection. COUT2 and COUT3 should be se- to the TYPICAL APPLICATION CIRCUIT in pre- lected for transient load regulation. vious page. 12 AIC1341 n APPLICATION CIRCUIT 1000pF K AIC1341CS 10 +12VIN 1 µH 2K VCC 1µ F 4 14 SS 2 5 0.1µF 1 + OCSET UGATE +5VIN 6030L 1000µF*2 0.1 µF PHASE GND 5V OUT +5.0VIN VIN2 7µ H 7 16 6030L GATE3 VOUT3 6030L + 1000µ F *5 10 FB3 15 11 3.3V LGATE PGND 3.9K + 2.4K 24K +5.0VIN FB1 13 GATE2 6030L 8.2K 8 VOUT2 33pF 91K COMP1 1000pF FB2 6 2.5V + 2.4K 12 2.4K 14 GND 3 SD Circuit 1 Multiple Voltage Power application Circuit 13 AIC1341 n PACKAGE DIMENSIONS 16 LEAD PLASTIC SO (300 mil) (unit: mm) D E H SYMBOL MIN MAX A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 10.10 10.50 E 7.40 7.60 e e 1.27(TYP) A A1 l B c L H 10.00 10.65 L 0.40 1.27 14