Data Sheet 26182.128A 6818 DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6818xA LOAD SUPPLY 1 SERIAL DATA OUT 2 VBB VDD 40 LOGIC SUPPLY 39 SERIAL DATA IN OUT 2 OUT 30 5 36 OUT 3 OUT 29 6 35 OUT 4 OUT 28 7 34 OUT 5 OUT 27 8 33 OUT 6 OUT 26 9 32 OUT 7 OUT 25 10 31 OUT 8 OUT 24 11 30 OUT 9 OUT 23 12 29 OUT 10 OUT 22 13 28 OUT 11 OUT 21 14 27 OUT 12 OUT 20 15 26 OUT 13 OUT 19 16 25 OUT 14 OUT 18 17 24 OUT 15 OUT 17 18 23 OUT 16 BLANKING 19 ST 22 STROBE GROUND 20 CLK 21 CLOCK LATCHES OUT 1 37 REGISTER 38 4 LATCHES 3 OUT 31 REGISTER OUT 32 BLNK Dwg. PP-029-4 ABSOLUTE MAXIMUM RATINGS at TA = 25°C Logic Supply Voltage, VDD ................... 7.0 V Driver Supply Voltage, VBB ................... 60 V Continuous Output Current Range, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA (Suffix ‘E–’) .................. -40°C to +85°C (Suffix ‘S–’) .................. -20°C to +85°C Storage Temperature Range, TS ............................... -55°C to +125°C Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges. The A6818– devices combine a 32-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6818– features an increased data input rate (compared with the older UCN/UCQ5818–F) and a controlled output slew rate. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6809– and A6810– (10 bits), A6811– (12 bits), and A6812– (20 bits). The A6818– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Two temperature ranges are available for optimum performance in commercial (suffix S-) or industrial (suffix E-) applications. Package styles are provided for through-hole DIP (suffix -A) or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logicpower dissipation, and low output-saturation voltages allow these devices to drive most multiplexed vacuum-fluorescent displays over the maximum operating temperature range. FEATURES ■ Controlled Output Slew Rate ■ Low Output-Saturation Voltages ■ High-Speed Data Storage ■ Low-Power CMOS Logic ■ 60 V Minimum and Latches Output Breakdown ■ Improved Replacements ■ High Data Input Rate for SN75518N, SN75518NF, ■ PNP Active Pull-Downs UCN5818–, and UCQ5818– Complete part number includes a suffix to identify operating temperature range (E- or S-) and package type (-A or -EP). Always order by complete part number, e.g., A6818SEP . 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER LOAD SUPPLY LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT2 OUT3 2 1 44 43 42 41 40 VBB V DD OUT31 OUT32 OUT30 4 SERIAL DATA OUT NC 6 38 9 37 10 36 13 LATCHES 12 REGISTER 8 11 Dwg. EP-010-5 39 2 REGISTER IN 7 LATCHES OUT29 5 VDD 3 A6818xEP TYPICAL INPUT CIRCUIT 34 OUT 8 33 19 35 14 Dwg. EP-021-19 ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS OUTN 31 30 OUT13 17 29 NC CLK ST 18 19 20 21 22 23 24 25 26 27 28 NC OUT17 BLANKING GROUND CLOCK STROBE OUT16 OUT15 OUT14 NC BLNK 15 16 Dwg. PP-059-2 3.0 TYPICAL OUTPUT DRIVER V BB 32 OUT18 OUT19 OUT 4 2.5 SUFFIX 'A', R θJA = 36°C/W 2.0 1.5 SUFFIX 'EP', RθJA = 46°C/W 1.0 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. GP-025A 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1998, 2000 Allegro MicroSystems, Inc. 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER FUNCTIONAL BLOCK DIAGRAM LOGIC SUPPLY V DD CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER STROBE LATCHES SERIAL DATA OUT BLANKING MOS BIPOLAR LOAD SUPPLY VBB GROUND OUT 1 OUT 2 OUT 3 OUT N Dwg. FP-013-1 TRUTH TABLE Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN Serial Data Strobe Output Input Latch Contents I1 I2 I3 ... IN-1 Output Contents IN Blanklng I1 I2 I3 ... IN-1 IN H H R1 R2 ... RN-2 RN-1 RN-1 L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN X X X L R1 R2 R3 ... RN-1 RN PN H P1 P2 P3 ... PN-1 PN L P1 P2 P3 ... PN-1 PN X X H L X X ... P1 P2 P3 ... L = Low Logic Level X PN-1 PN H = High Logic Level www.allegromicro.com X = Irrelevant X P = Present State X ... X R = Previous State L L ... L L 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature range (A6818E- and A6818K-), VBB = 60 V unless otherwise noted. Limits @ VDD = 3.3 V Characteristic Output Leakage Current Symbol ICEX Test Conditions VOUT = 0 V Limits @ VDD = 5 V Mln. Typ. Max. Min. Typ. Max. Units — <-0.1 -15 — <-0.1 -15 µA 57.5 58.3 — 57.5 58.3 — V VOUT(1) IOUT = -25 mA VOUT(0) IOUT = 1 mA — 1.0 1.5 — 1.0 1.5 V Output Pull-Down Current IOUT(0) VOUT = 5 V to VBB 2.5 5.0 — 2.5 5.0 — mA Input Voltage VIN(1) 2.2 — — 3.3 — — V VIN(0) — — 1.1 — — 1.7 V Output Voltage Input Current Input Clamp Voltage Serial Data Output Voltage Maximum Clock Frequency Logic Supply Current IIN(1) VIN = VDD — <0.01 1.0 — <0.01 1.0 µA IIN(0) VIN = 0.8 V — <-0.01 -1.0 — <-0.01 -1.0 µA IIN = -200 µA — -0.8 -1.5 — -0.8 -1.5 V VOUT(1) IOUT = -200 µA 2.8 3.05 — 4.5 4.75 — V VOUT(0) IOUT = 200 µA — 0.15 0.3 — 0.15 0.3 V 10 33 — 10 33 — MHz VIK fc IDD(1) All Outputs High — 0.25 0.75 — 0.3 1.0 mA IDD(0) All Outputs Low — 0.25 0.75 — 0.3 1.0 mA IBB(1) All Outputs High, No Load — 4.5 9.0 — 4.5 9.0 mA IBB(0) All Outputs Low — 0.2 20 — 0.2 20 µA tdis(BQ) CL = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 µs ten(BQ) CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 µs tp(STH-QL) RL = 2.3 kΩ, CL ≤ 30 pF — 0.7 2.0 — 0.7 2.0 µs tp(STH-QH) RL = 2.3 kΩ, CL ≤ 30 pF — 1.8 3.0 — 1.8 3.0 µs Output Fall Time tf RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Rise Time tr RL = 2.3 kΩ, CL ≤ 30 pF 2.4 — 12 2.4 — 12 µs Output Slew Rate dV/dt RL = 2.3 kΩ, CL ≤ 30 pF 4.0 — 20 4.0 — 20 V/µs IOUT = ±200 µA — 50 — — 50 — ns Load Supply Current Blanking-to-Output Delay Strobe-to-Output Delay Clock-to-Serial Data Out Delay tp(CH-SQX) Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at TA = +25°C. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) C 50% CLOCK A SERIAL DATA IN B DATA 50% t p(CH-SQX) SERIAL DATA OUT DATA 50% D 50% STROBE BLANKING E LOW = ALL OUTPUTS ENABLED t p(STH-QH) t p(STH-QL) 90% DATA OUT N 10% Dwg. WP-029 HIGH = ALL OUTPUTS BLANKED (DISABLED) BLANKING 50% t dis(BQ) t en(BQ) tr tf 90% OUT N A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ......................................... 25 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ............................................... 25 ns C. Clock Pulse Width, tw(CH) ............................................... 50 ns 10% DATA Dwg. WP-030 NOTE – Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches. D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns E. Strobe Pulse Width, tw(STH) ............................................. 50 ns www.allegromicro.com 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6818EA & A6811SA Dimensions in Inches (controlling dimensions) 0.015 0.008 40 21 0.700 MAX 0.580 0.485 0.600 BSC 1 2 0.070 0.030 3 20 0.100 4 2.095 1.980 0.005 MIN BSC 0.250 MAX 0.015 0.200 0.115 MIN 0.022 0.014 Dwg. MA-003-40 in Dimensions in Millimeters (for reference only) 0.381 0.204 40 21 17.78 MAX 14.73 12.32 15.24 BSC 1 2 1.77 0.77 3 4 2.54 53.2 50.3 BSC 20 0.13 MIN 6.35 MAX 0.39 5.08 2.93 MIN 0.558 0.356 Dwg. MA-003-40 mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER A6818EEP & A6818SEP Dimensions in Inches (controlling dimensions) 18 28 29 17 0.032 0.026 0.319 0.291 0.695 0.685 0.021 0.013 0.656 0.650 0.319 0.291 0.050 INDEX AREA BSC 39 7 40 0.020 44 1 2 6 0.656 0.650 MIN 0.695 0.685 0.180 0.165 Dwg. MA-005-44A in Dimensions in Millimeters (for reference only) 28 18 29 17 0.812 0.661 8.10 7.39 17.65 17.40 0.533 0.331 16.662 16.510 8.10 7.39 INDEX AREA 1.27 BSC 39 7 40 0.51 MIN 4.57 4.20 44 1 2 6 16.662 16.510 17.65 17.40 Dwg. MA-005-44A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 6818 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000