ADVANCE INFORMATION 8-BIT SERIAL-INPUT, DMOS POWER DRIVER (Subject to change without notice) January 24, 2000 20 NO CONNECTION 2 VDD 19 GROUND SERIAL DATA IN 3 18 SERIAL DATA OUT OUT 0 4 17 OUT 7 OUT 1 5 16 OUT 6 OUT 2 6 15 OUT 5 OUT 3 7 14 OUT 4 REGISTER CLEAR 8 CLR CLK 13 CLOCK OUTPUT ENABLE 9 OE ST 12 STROBE GROUND 10 11 GROUND LATCHES LOGIC SUPPLY NC REGISTER NC LATCHES 1 REGISTER NO CONNECTION Dwg. PP-029-12 Note that the A6B595KA (DIP) and the A6B595KLW (SOIC) are electrically identical and share a common terminal number assignment. ABSOLUTE MAXIMUM RATINGS at TA = 25°C Output Voltage, VO ............................... 50 V Output Drain Current, Continuous, IO .......................... 150 mA* Peak, IOM ................................... 500 mA† Single-Pulse Avalanche Energy, EAS ................................................. 30 mJ Logic Supply Voltage, VDD .................. 7.0 V Input Voltage Range, VI ................................... -0.3 V to +7.0 V Package Power Dissipation, PD ........................................... See Graph Operating Temperature Range, TA ................................. -40°C to +125°C Storage Temperature Range, TS ................................. -55°C to +150°C * Each output, all outputs on. † Pulse duration ≤ 100 µs, duty cycle ≤ 2%. Caution: These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. Data Sheet 26185.122 6B595 The A6B595KA and A6B595KLW combine an 8-bit CMOS shift register and accompanying data latches, control circuitry, and DMOS power driver outputs. Power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. The serial-data input, CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Serial-data input rates are over 5 MHz. Use with TTL may require appropriate pull-up resistors to ensure an input logic high. A CMOS serial-data output enables cascade connections in applications requiring additional drive lines. Similar devices with reduced rDS(on) are available as the A6595KA and A6595KLW. The A6B595 DMOS open-drain outputs are capable of sinking up to 500 mA. All of the output drivers are disabled (the DMOS sink drivers turned off) by the OUTPUT ENABLE input high. The A6B595KA is furnished in a 20-pin dual in-line plastic package. The A6B595KLW is furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing leads. Copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 mA from all outputs continuously, to ambient temperatures over 85°C. FEATURES ■ 50 V Minimum Output Clamp Voltage ■ 150 mA Output Current (all outputs simultaneously) ■ 5 Ω Typical rDS(on) ■ Low Power Consumption ■ Replacements for TPIC6B595N and TPIC6B595DW Always order by complete part number: Part Number Package A6B595KA 20-pin DIP A6B595KLW 20-lead SOIC RθJA 55°C/W 70°C/W RθJC 25°C/W 17°C/W ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER LOGIC SYMBOL 2.5 9 12 2.0 SU FF IX 1.5 SU FF IX 'A ', R θJ A = 'LW ', R θJ 1.0 G3 C2 SRG8 8 13 R 3 1D C1 2 4 55 °C /W 5 6 A =7 0° C/ W 7 14 0.5 15 16 2 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 17 150 18 Dwg. GS-004A Dwg. FP-043 FUNCTIONAL BLOCK DIAGRAM REGISTER CLEAR (ACTIVE LOW) V DD CLOCK SERIAL DATA IN SERIAL-PARALLEL SHIFT REGISTER STROBE D-TYPE LATCHES LOGIC SUPPLY SERIAL DATA OUT OUTPUT ENABLE (ACTIVE LOW) GROUND GROUND OUT 0 OUT N Grounds (terminals 10, 11, and 19) must be connected together externally. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1999, Allegro MicroSystems, Inc. Dwg. FP-013-4 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER V DD OUT IN Dwg. EP-063 Dwg. EP-010-16 DMOS POWER DRIVER OUTPUT LOGIC INPUTS VDD OUT RECOMMENDED OPERATING CONDITIONS over operating temperature range Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V High-Level Input Voltage, VIH ............................ ≥ 0.85VDD Low-level input voltage, VIL ................................. ≤0.15VDD Dwg. EP-063-1 SERIAL DATA OUT TRUTH TABLE Shift Register Contents Data Clock Input Input I0 I1 I2 ... I6 H H R0 R1 … R5 R6 R6 L L R0 R1 … R5 R6 R6 R0 R1 R2 … R6 R7 R7 X X … X X X P0 P1 P2 … P6 P7 P7 X X L = Low Logic Level I7 Serial Data Output Strobe H = High Logic Level www.allegromicro.com — X = Irrelevant Latch Contents I0 I1 ... I6 R0 R1 R2 … R6 R7 P0 P1 P2 … P6 P7 L P0 P1 P2 … P6 P7 X … X H H … H X I2 Output Contents X P = Present State I7 Output Enable X R = Previous State I0 I1 H I2 H … I6 I7 H 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise specified). Limits Characteristic Symbol Test Conditions Output Breakdown Voltage V(BR)DSX Off-State Output Current Static Drain-Source On-State Resistance IDSX rDS(on) Min. Typ. Max. Units IO = 1 mA 50 — — V VO = 40 V, VDD = 5.5 V — 0.1 5.0 µA VO = 40 V, VDD = 5.5 V, TA = 125°C — 0.15 8.0 µA IO = 100 mA, VDD = 4.5 V — 4.2 5.7 Ω IO = 100 mA, VDD = 4.5 V, TA = 125°C — 6.8 9.5 Ω IO = 350 mA, VDD = 4.5 V (see note) — 5.5 8.0 Ω Nominal Output Current ION VDS(on) = 0.5 V, TA = 85°C — 90 — mA Logic Input Current IIH VI = VDD = 5.5 V — — 1.0 µA IIL VI = 0, VDD = 5.5 V — — -1.0 µA IOH = -20 µA, VDD = 4.5 V 4.4 4.49 — V IOH = -4 mA, VDD = 4.5 V 4.0 4.2 — V IOL = 20 µA, VDD = 4.5 V — 0.005 0.1 V IOL = 4 mA, VDD = 4.5 V — 0.3 0.5 V tPLH IO = 100 mA, CL = 30 pF — 150 — ns tPHL IO = 100 mA, CL = 30 pF — 90 — ns Output Rise Time tr IO = 100 mA, CL = 30 pF — 200 — ns Output Fall Time tf IO = 100 mA, CL = 30 pF — 200 — ns IDD(OFF) VDD = 5.5 V, Outputs OFF — 20 100 µA IDD(ON) VDD = 5.5 V, Outputs ON — 150 300 µA IDD(fclk) fclk = 5 MHz, CL = 30 pF, Outputs OFF — 0.4 5.0 mA SERIAL-DATA Output Voltage VOH VOL Prop. Delay Time Supply Current Typical Data is at VDD = 5 V and is for design information only. NOTE — Pulse test, duration ≤100 µs, duty cycle ≤2%. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER TIMING REQUIREMENTS and SPECIFICATIONS (Logic Levels are VDD and Ground) C 50% CLOCK A SERIAL DATA IN B DATA 50% tp SERIAL DATA OUT DATA 50% D E STROBE 50% OUTPUT ENABLE LOW = ALL OUTPUTS ENABLED tp HIGH = OUTPUT OFF DATA 50% OUT N LOW = OUTPUT ON Dwg. WP-029-2 HIGH = ALL OUTPUTS DISABLED OUTPUT ENABLE 50% t PLH t PHL tf tr 90% OUT N DATA 10% Dwg. WP-030-2 A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) .......................................... 20 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) .............................................. 20 ns C. Clock Pulse Width, tw(CLK) ............................................. 40 ns D. Time Between Clock Activation and Strobe, tsu(ST) ....................................................... 50 ns E. Strobe Pulse Width, tw(ST) .............................................. 50 ns F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs NOTE – Timing is representative of a 12.5 MHz clock. Higher speeds are attainable. www.allegromicro.com Serial data present at the input is transferred to the shift register on the rising edge of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. Information present at any register is transferred to the respective latch on the rising edge of the STROBE input pulse (serial-to-parallel conversion). When the OUTPUT ENABLE input is high, the output source drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER TEST CIRCUITS +15 V 10.5 Ω INPUT 200 mH tav IAS = 500 mA IO DUT OUT VO V(BR)DSX VO(ON) Dwg. EP-066 EAS = IAS x V(BR)DSX x tAV/2 Single-Pulse Avalanche Energy Test Circuit and Waveforms 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER TERMINAL DESCRIPTIONS Terminal No. Terminal Name Function 1 NC No internal connection. 2 LOGIC SUPPLY (VDD) The logic supply voltage (typically 5 V). 3 SERIAL DATA IN Serial-data input to the shift-register. 4-7 OUT0-3 Current-sinking, open-drain DMOS output terminals. 8 CLEAR When (active) low, the registers are cleared (set low). 9 OUTPUT ENABLE 10 GROUND Reference terminal for output voltage measurements (OUT0-3). 11 GROUND Reference terminal for output voltage measurements (OUT0-7). 12 STROBE Data strobe input terminal; shift register data is latched on rising edge. 13 CLOCK Clock input terminal for data shift on rising edge. 14-17 OUT4-7 Current-sinking, open-drain DMOS output terminals. 18 SERIAL DATA OUT 19 GROUND 20 NC When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). CMOS serial-data output to the following shift register. Reference terminal for input voltage measurements. No internal connection. NOTE — Grounds (terminals 10, 11, and 19) must be connected together externally. www.allegromicro.com 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER A6B595KA Dimensions in Inches (controlling dimensions) 0.014 0.008 11 20 0.430 MAX 0.280 0.240 0.300 BSC 1 0.070 0.045 0.100 1.060 0.980 10 BSC 0.005 MIN 0.210 MAX 0.150 0.115 0.015 MIN 0.022 0.014 Dwg. MA-001-20 in Dimensions in Millimeters (for reference only) 20 0.355 0.204 11 10.92 MAX 7.11 6.10 7.62 BSC 1 1.77 1.15 2.54 26.92 24.89 BSC 10 0.13 MIN 5.33 MAX 3.81 2.93 0.39 MIN 0.558 0.356 Dwg. MA-001-20 mm NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative 3. Lead thickness is measured at seating plane or below. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER A6B595KLW Dimensions in Inches (for reference only) 20 11 0.0125 0.0091 0.419 0.394 0.2992 0.2914 0.050 0.016 0.020 0.013 1 2 0.050 3 0° TO 8° BSC 0.5118 0.4961 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-20 in Dimensions in Millimeters (controlling dimensions) 20 11 0.32 0.23 10.65 10.00 7.60 7.40 1.27 0.40 0.51 0.33 1 2 1.27 3 13.00 12.60 BSC 0° TO 8° 2.65 2.35 0.10 MIN. Dwg. MA-008-20 mm NOTES:1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. www.allegromicro.com 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER This page intentionally left blank 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER This page intentionally left blank www.allegromicro.com 6B595 8-BIT SERIAL-INPUT, DMOS POWER DRIVER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000