TI SN74ACT7804-20DL

SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
D
D
D
D
D
D
D
D
D
D
D
Member of the Texas Instruments
Widebus Family
Load Clock and Unload Clock Can Be
Asynchronous or Coincident
512 Words by 18 Bits
Low-Power Advanced CMOS Technology
Full, Empty, and Half-Full Flags
Programmable Almost-Full/Almost-Empty
Flag
Fast Access Times of 15 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
Data Rates up to 50 MHz
3-State Outputs
Pin-to-Pin Compatible With SN74ACT7806
and SN74ACT7814
Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing
description
A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ACT7804 is a
512-word by 18-bit FIFO for high speed and fast
access times. It processes data at rates up to
50 MHz and access times of 15 ns in a bit-parallel
format.
Data is written into memory on a low-to-high
transition at the load-clock (LDCK) input and is
read out on a low-to-high transition at the
unload-clock (UNCK) input. The memory is full
when the number of words clocked in exceeds the
number of words clocked out by 512. When the
memory is full, LDCK signals have no effect on the
data residing in memory. When the memory is
empty, UNCK signals have no effect.
DL PACKAGE
(TOP VIEW)
RESET
D17
D16
D15
D14
D13
D12
D11
D10
VCC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
LDCK
NC
NC
FULL
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OE
Q17
Q16
Q15
GND
Q14
VCC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
VCC
Q4
Q3
Q2
GND
Q1
Q0
UNCK
NC
NC
EMPTY
NC – No internal connection
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and
almost-full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF
output is high when the FIFO contains 256 or more words. The AF/AE status flag is a programmable flag. The
first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value
(X) and the almost-full offset value (Y) if program enable (PEN) is low. The AF/AE flag is high when the FIFO
contains X or fewer words or (512 – Y) or more words. The AF/AE flag is low when the FIFO contains between
(X + 1) and (511 – Y) words.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
description (continued)
A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, AF/AE high, HF
low, and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon
power up.
The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.
It is important to note that the first word does not have to be unloaded. The data outputs are noninverting with
respect to the data inputs and are in the high-impedance state when the output-enable (OE) input is high.
The SN74ACT7804 is characterized for operation from 0°C to 70°C.
logic symbol†
RESET
LDCK
UNCK
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
23
21
FULL
LDCK
32
56
D0
RESET
25
OE
PEN
Φ
FIFO 512 × 18
SN74ACT7804
HALF-FULL
UNCK
ALMOST FULL/EMPTY
EN1
EMPTY
22
24
FULL
HF
AF/AE
29
EMPTY
PROGRAM ENABLE
0
0
33
20
34
19
36
18
37
17
38
16
40
15
41
14
42
12
43
11
Data
Data
45
1
9
46
8
47
7
48
6
49
5
51
4
53
3
54
2
55
17
17
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
functional block diagram
OE
D0–D17
Location 1
Location 2
Read
Pointer
UNCK
512 × 18 SRAM
Write
Pointer
LDCK
Location 511
Location 512
Q0–Q17
EMPTY
Reset
Logic
RESET
StatusFlag
Logic
PEN
FULL
HF
AF/AE
Terminal Functions
TERMINAL
I/O
DESCRIPTION
24
O
Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value
of 64 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when
memory contains X or fewer words or (512 – Y) or more words. AF/AE is high after reset.
D0–D17
2–9, 11–12,
14–21
I
18-bit data input port
EMPTY
29
O
Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.
FULL
28
O
Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF
22
O
Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low after reset.
LDCK
25
I
Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE
56
I
Output enable. When OE is high, the data outputs are in the high-impedance state.
PEN
23
I
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7
is latched as an AF/AE offset value when PEN is low and LDCK is high.
33–34, 36–38,
40–43, 45–49,
51, 53–55
O
18-bit data output port
RESET
1
I
Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY low.
UNCK
32
I
Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
NAME
NO.
AF/AE
Q0–Q17
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• DALLAS, TEXAS 75265
3
SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
offset values for AF/AE
The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value
(Y). They can be programmed after the FIFO is reset and before the first word is written to memory. The AF/AE
flag is high when the FIFO contains X or fewer words or (512 – Y) or more words.
To program the offset values, PEN can be brought low after reset only when LDCK is low. On the following
low-to-high transition of LDCK, the binary value on D0–D7 is stored as the almost-empty offset value (X) and
the almost-full offset value (Y). Holding PEN low for another low-to-high transition of LDCK reprograms Y to the
binary value on D0–D7 at the time of the second LDCK low-to-high transition. Writes to the FIFO memory are
disabled while the offsets are programmed. A maximum value of 255 can be programmed for either X or Y (see
Figure 1). To use the default values of X = Y = 64, PEN must be held high.
RESET
LDCK
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
Don’t Care
PEN
ÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏ
ÌÌÌÌÌ
ÌÌÌÌÌ
D0–D7
Don’t Care
X and Y
Y
EMPTY
Figure 1. Programming X and Y Separately
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
RESET
1
0
PEN
ÏÏ
ÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏ
ÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
LDCK
D0–D17
W1
W2
W
(X+1)
W256
W
(512–Y)
Don’t Care
W512
1
0
W1
W2
W
(Y+1)
W
(Y+2)
W257
W258
W
(512–X)
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
• DALLAS, TEXAS 75265
Q0–Q17
W
(513–X)
ÏÏ
ÏÏ
ÏÏ
ÏÏ
OE
W511
W512
EMPTY
AF/AE
HF
Define the AF/AE Flag Using
the Default Value of X and Y
Figure 2. Write, Read, and Flag Timing Reference
5
SCAS204C – APRIL 1992 – REVISED APRIL 1998
FULL
SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
POST OFFICE BOX 655303
UNCK
SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
’ACT7804-20
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
High-level input voltage
Low level output current
Low-level
TA
Operating free-air temperature
’ACT7804-40
MAX
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
4.5
5.5
2
High-level output current
IOL
’ACT7804-25
MIN
2
2
UNIT
V
V
0.8
0.8
0.8
V
Q outputs, flags
–8
–8
–8
mA
Q outputs
16
16
16
8
8
8
Flags
0
70
0
70
0
70
mA
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
II
IOZ
ICC
∆ICC§
Ci
Flags
Q outputs
TEST CONDITIONS
TYP‡
MAX
2.4
UNIT
VCC = 4.5 V,
VCC = 4.5 V,
IOH = –8 mA
IOL = 8 mA
VCC = 4.5 V,
VCC = 5.5 V,
IOL = 16 mA
VI = VCC or 0
0.5
±5
µA
VCC = 5.5 V,
VCC = 5.5 V,
VO = VCC or 0
VI = VCC – 0.2 V or 0
±5
µA
VCC = 5.5 V,
VI = 0,
One input at 3.4 V,
Other inputs at VCC or GND
f = 1 MHz
VO = 0,
f = 1 MHz
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ This is the supply current for each input that is at one of the specified TTL voltage levels rather 0 V or VCC.
POST OFFICE BOX 655303
V
0.5
Co
6
MIN
• DALLAS, TEXAS 75265
V
400
µA
1
mA
4
pF
8
pF
SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
timing requirements over recommended operating conditions (see Figures 1 through 3)
’ACT7804-20
MIN
fclock
tw
Clock frequency
MIN
Setup time
Hold time
MAX
’ACT7804-40
MIN
40
MAX
25
LDCK high or low
7
8
12
UNCK high or low
7
8
12
PEN low
7
8
12
10
10
12
RESET low
th
’ACT7804-25
50
Pulse duration
tsu
MAX
D0–D17 before LDCK↑
5
5
5
PEN before LDCK↑
5
5
5
LDCK inactive before RESET high
5
6
6
D0–D17 after LDCK↑
0
0
0
LDCK inactive after RESET high
5
6
6
PEN low after LDCK↑
3
3
3
PEN high after LDCK↓
0
0
0
UNIT
MHz
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
fmax
LDCK or UNCK
tpd
d
tpd‡
tPLH
TO
(OUTPUT)
LDCK↑
Any Q
UNCK↑
UNCK↑
Any Q
LDCK↑
EMPTY
UNCK↑
tPHL
EMPTY
RESET low
LDCK↑
tPLH
tpd
d
tPLH
tPHL
FULL
UNCK↑
FULL
RESET low
LDCK↑
AF/AE
UNCK↑
’ACT7804-20
TYP†
MAX
’ACT7804-25
MIN
MIN
50
40
9
6
11.5
MAX
’ACT7804-40
MIN
MAX
25
MHz
20
9
22
9
24
15
6
18
6
20
10.5
6
15
6
17
6
19
6
15
6
17
6
19
4
16
4
18
4
20
6
15
6
17
6
19
6
15
6
17
6
19
4
18
4
20
4
22
7
18
7
20
7
22
7
18
7
20
7
22
AF/AE
2
10
2
12
2
14
LDCK↑
HF
5
18
5
20
5
22
7
18
7
20
7
22
3
12
3
14
3
16
UNCK↑
HF
ns
ns
RESET low
RESET low
UNIT
ns
ns
ns
ns
ns
ns
ten
OE
Any Q
2
9
2
10
2
11
ns
tdis
OE
Any Q
2
10
2
11
2
12
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This parameter is measured at CL = 30 pF (see Figure 4).
operating characteristics, VCC = 5 V, TA = 25°CFigure 2
PARAMETER
Cpd
Power dissipation capacitance per FIFO channel
POST OFFICE BOX 655303
TEST CONDITIONS
Outputs enabled
• DALLAS, TEXAS 75265
CL = 50 pF,
f = 5 MHz
TYP
53
UNIT
pF
7
SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
7V
PARAMETER
S1
ten
500 Ω
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
tdis
500 Ω
tpd
S1
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
Open
Closed
Open
Closed
Open
Open
tw
LOAD CIRCUIT
3V
Input
0V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tsu
th
3V
Data
Input
1.5 V
1.5 V
0V
3V
Output
Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
tPZH
1.5 V
VOL
Output
Waveform 2
S1 at Open
VOL + 0.3 V
1.5 V
VOH
VOH – 0.3 V
≈0V
NOTE A: CL includes probe and jig capacitance.
Figure 3. Load Circuit and Voltage Waveforms
• DALLAS, TEXAS 75265
VOL
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
POST OFFICE BOX 655303
tPLZ
≈ 3.5 V
Output
Waveform 1
S1 at 7 V
tPHL
VOH
8
1.5 V
0V
tPZL
3V
Output
1.5 V
3V
Timing
Input
Input
1.5 V
SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
SUPPLY CURRENT
vs
CLOCK FREQUENCY
200
VCC = 5 V
TA = 25°C
RL = 500 Ω
TA = 75°C
CL = 0 pF
180
typ + 6
VCC = 5.5 V
160
I CC(f) – Supply Current – mA
t pd – Propagation Delay Time – ns
typ + 8
typ + 4
typ + 2
typ
VCC = 5 V
140
120
100
VCC = 4.5 V
80
60
40
20
0
typ – 2
0
50
100
150
200
250
300
0
10
20
30
40
50
60
70
fclock – Clock Frequency – MHz
CL – Load Capacitance – pF
Figure 4
Figure 5
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• DALLAS, TEXAS 75265
9
SN74ACT7804
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SCAS204C – APRIL 1992 – REVISED APRIL 1998
APPLICATION INFORMATION
LDCK
SN74ACT7804
UNCK
LDCK
EMPTY
FULL
FULL
OE
D18–D35
D0–D17
Q0–Q17
UNCK
EMPTY
OE
Q18–Q35
SN74ACT7804
LDCK
FULL
UNCK
EMPTY
OE
D0–D17
D0–D17
Q0–Q17
Figure 6. Word-Width Expansion: 512 × 36 Bits
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Q0–Q17
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
1M7804-20DLG4
ACTIVE
SSOP
DL
56
1M7804-20DLRG4
ACTIVE
SSOP
DL
56
SN74ACT7804-20DL
ACTIVE
SSOP
DL
56
SN74ACT7804-20DLR
ACTIVE
SSOP
DL
56
SN74ACT7804-25DL
ACTIVE
SSOP
DL
56
SN74ACT7804-25DLR
ACTIVE
SSOP
DL
56
SN74ACT7804-40DL
ACTIVE
SSOP
DL
56
SN74ACT7804-40DLR
ACTIVE
SSOP
DL
56
20
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
20
20
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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