TI SN74LVT573DWR

SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
D
D
D
D
D
D
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54LVT573 . . . FK PACKAGE
(TOP VIEW)
3D
4D
5D
6D
7D
1Q
D
SN54LVT573 . . . J OR W PACKAGE
SN74LVT573 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
2D
1D
OE
VCC
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Support Live Insertion
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
D
description
These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The eight latches of the ’LVT573 are transparent D-type latches. While the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components. OE does not affect the internal operations of the latches.
Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT573 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74LVT573 is characterized for operation from – 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic symbol†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
11
2
logic diagram (positive logic)
EN
OE
C1
1D
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
LE
1
11
1Q
C1
2Q
3Q
1D
2
19
1Q
1D
4Q
5Q
6Q
7Q
To Seven Other Channels
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . – 0.5 V to 7 V
Current into any output in the low state, IO: SN54LVT573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVT573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVT573 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVT573 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . 0.6 W
DW package . . . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
2
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SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
recommended operating conditions (see Note 4)
SN54LVT573
SN74LVT573
MIN
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0.8
0.8
Input voltage
5.5
5.5
V
IOH
IOL
High-level output current
– 24
– 32
mA
48
64
mA
∆t /∆v
Input transition rise or fall rate
10
10
ns / V
85
°C
High-level input voltage
2
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
– 55
2
125
– 40
V
V
V
3
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VCC = 2.7 V,
VCC = MIN to MAX‡,
II = –18 mA
IOH = –100 µA
VCC = 2.7 V,
IOH = – 8 mA
IOH = – 24 mA
VCC = 3 V
VCC = 2
2.7
7V
VOL
VCC = 3 V
VCC = 0 or MAX‡,
36V
VCC = 3.6
Ioff
VCC = 0,
II(hold)
I(h ld)
VCC = 3 V
IOZH
IOZL
VCC = 3.6 V,
VCC = 3.6 V,
VCC = 3.6 V,
VI = VCC or GND
ICC
MIN
SN74LVT573
TYP†
MAX
MIN
–1.2
VCC – 0.2
2.4
–1.2
VCC – 0.2
2.4
0.2
IOL = 24 mA
IOL = 16 mA
0.5
0.5
0.4
0.4
IOL = 32 mA
IOL = 48 mA
0.5
0.5
VI = 2 V
VO = 3 V
0.55
Control
inputs
Data inputs
50
10
±1
±1
1
1
–5
–5
± 100
Data inputs
75
75
–75
–75
VO = 0.5 V
IO = 0,
V
0.55
IOL = 64 mA
VI = 5.5 V
VI or VO = 0 to 4.5 V
VI = 0.8 V
V
2
0.2
VI = VCC
VI = 0
UNIT
V
2
IOH = – 32 mA
IOL = 100 µA
VI = VCC or GND
II
SN54LVT573
TYP†
MAX
TEST CONDITIONS
1
1
µA
–1
–1
µA
0.13
0.39
0.13
0.19
Outputs low
8.6
14
8.6
12
0.13
0.39
0.13
0.19
∆ICC§
VCC = 3 V to 3.6 V,
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
µA
µA
Outputs high
Outputs
disabled
µA
µ
0.3
0.2
4
Co
8
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
mA
mA
4
pF
8
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVT573
VCC = 3.3 V
± 0.3 V
MIN
tw
tsu
Pulse duration, LE high
th
Hold time, data after LE↓
4
MAX
SN74LVT573
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
MAX
VCC = 2.7 V
MIN
UNIT
MAX
3.3
3.3
3.3
3.3
ns
1
0.9
0.7
0.6
ns
1.8
2
1.6
1.8
ns
Setup time, data before LE↓
POST OFFICE BOX 655303
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SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT573
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
LE
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
VCC = 3.3 V
± 0.3 V
SN74LVT573
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN TYP†
MAX
VCC = 2.7 V
MIN
MAX
MIN
0.5
4.7
4.9
1
2.5
4.2
4.7
0.5
4.9
5.4
1
2.7
4.3
5.2
1
6
6.9
1.6
3.5
5.6
6.3
1.4
6.9
7.6
2.5
4.3
6.5
7.2
0.5
5.3
6.4
1
2.8
5.1
6.2
0.7
5.7
7.2
1.3
3.3
5.5
6.6
1.2
5.9
6.9
2
3.7
5.7
6.7
1
5.4
5.5
1.5
3
4.6
5.1
UNIT
MAX
ns
ns
ns
ns
† All typical values are at VCC = 3.3 V, TA = 25°C.
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5
SN54LVT573, SN74LVT573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS138D – MAY 1992 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
500 Ω
2.7 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
0V
tw
tsu
2.7 V
Input
1.5 V
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPHL
tPLH
2.7 V
Output
Control
tPLZ
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
tPZH
3V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVT573DBLE
OBSOLETE
SSOP
DB
20
SN74LVT573DBR
ACTIVE
SSOP
DB
20
SN74LVT573DBRE4
ACTIVE
SSOP
DB
20
SN74LVT573DW
ACTIVE
SOIC
DW
20
SN74LVT573DWE4
ACTIVE
SOIC
DW
20
SN74LVT573DWR
ACTIVE
SOIC
DW
20
SN74LVT573DWRE4
ACTIVE
SOIC
DW
20
TBD
Call TI
Call TI
SN74LVT573NSR
OBSOLETE
SO
NS
20
TBD
Call TI
Call TI
SN74LVT573PWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
SN74LVT573PWR
ACTIVE
TSSOP
PW
20
SN74LVT573PWRE4
ACTIVE
TSSOP
PW
20
TBD
Call TI
Call TI
SNJ54LVT573FK
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
SNJ54LVT573J
OBSOLETE
CDIP
J
20
TBD
Call TI
Call TI
SNJ54LVT573W
OBSOLETE
CFP
W
20
TBD
Call TI
Call TI
TBD
2000 Green (RoHS &
no Sb/Br)
25
Lead/Ball Finish
Call TI
CU NIPDAU
TBD
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
TBD
2000 Green (RoHS &
no Sb/Br)
2000 Green (RoHS &
no Sb/Br)
Call TI
CU NIPDAU
CU NIPDAU
MSL Peak Temp (3)
Call TI
Level-1-260C-UNLIM
Call TI
Level-1-260C-UNLIM
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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Following are URLs where you can obtain information on other Texas Instruments products and application
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Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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