AMICC A45L9332AF-7

A45L9332A Series
Preliminary
256K X 32 Bit X 2 Banks Synchronous Graphic RAM
Document Title
256K X 32Bit X 2 Banks Synchronous Graphic RAM
Revision History
History
Issue Date
Remark
0.0
Initial issue
August 21, 2001
Preliminary
0.1
Update AC and DC data specification
October 22, 2001
Rev. No.
PRELIMINARY
(October, 2001, Version 0.1)
AMIC Technology, Inc.
A45L9332A Series
Preliminary
256K X 32 Bit X 2 Banks Synchronous Graphic RAM
Features
n
n
n
n
n
n
n
n
n
n 100 Pin QFP, LQFP (14 X 20 mm)
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
32ms refresh period (2K cycle)
Graphics Features
n SMRS cycle
- Load mask register
- Load color register
n Write Per Bit (Old Mask)
n Block Write (8 Columns)
General Description
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Write per bit and 8 columns block write improves
performance in graphics system.
The A45L9332A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 X 262,144 words by 32
bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
PRELIMINARY
(October, 2001, Version 0.1)
1
AMIC Technology, Inc.
A45L9332A Series
PRELIMINARY
DQ0
VDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
DQ31
DQ30
VSSQ
DQ29
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQ1
98
96
VSSQ
99
97
DQ2
100
Pin Configuration
DQ 3
1
80
DQ28
VDDQ
2
79
VDDQ
DQ 4
3
78
DQ 27
DQ 5
4
77
DQ 26
VSSQ
5
76
VSSQ
DQ 6
6
75
DQ25
DQ7
7
74
DQ 24
VDDQ
8
73
VDDQ
DQ 16
9
72
DQ15
DQ 17
10
71
DQ14
VSSQ
11
70
VSSQ
DQ 18
12
69
DQ13
DQ 19
13
68
DQ12
VDDQ
14
67
VDDQ
VDD
15
66
VSS
VSS
16
65
VDD
DQ 20
17
64
DQ11
DQ 21
18
63
DQ10
VSSQ
19
62
VSSQ
DQ9
A45L9332AE
A45L9332AF
(October, 2001, Version 0.1)
45
46
47
48
49
50
VSS
A4
A5
A6
A7
A9
NC
51
44
30
NC
NC
A8
43
52
NC
29
42
DSF
BA(A10)
NC
CKE
53
41
54
28
NC
27
CS
40
RAS
NC
CLK
39
55
NC
26
38
DQM1
CAS
NC
56
37
25
36
DQM3
WE
NC
NC
57
NC
58
24
35
23
DQM2
VDD
DQM0
34
VDDQ
A3
59
33
22
A2
DQ8
VDDQ
32
60
31
61
21
A1
20
A0
DQ 22
DQ 23
2
AMIC Technology, Inc.
A45L9332A Series
DQMi
INPUT BUFFER
Block Diagram
MASK
REGISTER
MASK
BLOCK
WRITE
CONTROL
LOGIC
WRITE
CONTROL
LOGIC
CLOCK
REGISTER
MUX
CLK
CKE
DQi
(i=0~31)
COLUMN
MASK
256K x 32
CELL
ARRAY
INPUT BUFFER
SENSE AMPLIFIER
COLUMN
DECORDER
WE
LATENCY &
BURST LENGTH
CAS
PROGRAMING
REGISTER
RAS
DQMi
TIMMING REGISTER
CS
256K x 32
CELL
ARRAY
DSF
ROW DECORDER
BANK SELECTION
DQMi
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
REFRESH
COUNTER
ADDRESS REGISTER
CLOCK
PRELIMINARY
(October, 2001, Version 0.1)
3
ADDRESS (A0~A10)
AMIC Technology, Inc.
A45L9332A Series
Pin Descriptions
Symbol
Name
Description
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + t ss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A9
Address
Row address : RA0~RA9, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
A10(BA)
Bank Select Address
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
DQMi
Data Input/Output Mask
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte Masking)
DQi
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
DSF
Define Special Function
Enables write per bit, block write and special mode register set.
VDD/VSS
Power Supply/Ground
Power Supply: +3.3V±0.3V/Ground
VDDQ/VS
SQ
Data Output
Power/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
NC
No Connection
PRELIMINARY
(October, 2001, Version 0.1)
4
AMIC Technology, Inc.
A45L9332A Series
Absolute Maximum Ratings*
*Comments
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . 50mA
Permanent device damage may occur if “Absolute Maximum
Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
Capacitance (TA=25°C, f=1MHz)
Parameter
Symbol
Input Capacitance
Data Input/Output Capacitance
Condition
CI1
A0 to A9, BA
CI2
CLK, CKE,
DQMi, DSF
CI/O
DQ0 to DQ15
Min
CS , RAS , CAS , WE ,
Typ
Max
Unit
2
4
pF
2
4
pF
2
6
pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V)
Parameter
Supply Voltage
Symbol
Min
Typ
Max
Unit
VDD,VDDQ
3.0
3.3
3.6
V
Note
Input High Voltage
VIH
2.0
3.0
VDD+0.3
V
Input Low Voltage
VIL
-0.3
0
0.8
V
Note 1
Output High Voltage
VOH
2.4
-
-
V
IOH = -2mA
Output Low Voltage
VOL
-
-
0.4
V
IOL = 2mA
Input Leakage Current
IIL
-5
-
5
µA
Note 2
Output Leakage Current
IOL
-5
-
5
µA
Note 3
Output Loading Condition
See Figure 1
Note: 1. VIL (min) = -1.5V AC (pulse width ≤ 5ns).
2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V ≤ Vout ≤ VDD
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
CDC1
0.1 + 0.01
µF
Decoupling Capacitance between VDDQ and VSSQ
CDC2
0.1 + 0.01
µF
Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
PRELIMINARY
(October, 2001, Version 0.1)
5
AMIC Technology, Inc.
A45L9332A Series
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Symbol
Icc1
Icc2 P
Icc2 PS
ICC2N
Parameter
Test Conditions
Speed
CAS
Latency
-6
-7
-8
Operating Current
Burst Length = 1
3
230
210
170
(One Bank Active)
tRC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA
2
-
260
160
Precharge Standby
Current in powerdown mode
CKE ≤ VIL(max), tCC = 15ns
4
CKE ≤ VIL(max), CKL ≤ VIL(max), tCC = ∞
4
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Precharge Standby
Current in non
power-down mode
ICC2NS
ICC3 PS
ICC3N
ICC3NS
Active Standby
Current in powerdown mode
Active Standby
current in non
power-down mode
(One Bank Active)
Notes
mA
1
mA
35
Input signals are changed one time during 30ns
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
15
Input signals are stable.
ICC3 P
Unit
CKE ≤ VIL(max), tCC = 15ns
6
CKE ≤ VIL(max), CKE ≤ VIL(max) tCC = ∞
6
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
mA
60
Input signals are changed one time during 30ns
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
40
Input signals are stable.
ICC4
Operating Current
IOL = 0mA, Page Burst
(Burst Mode)
All bank Activated, tCCD = tCCD (min)
ICC5
Refresh Current
tRC ≥ tRC (min)
ICC6
Self Refresh Current
CKE ≤ 0.2V
ICC7
Operating Current
(One Bank Block
Write)
tCC ≥ tCC (min), IOL=0mA, tBWC(min)
3
310
280
250
2
-
230
210
3
150
120
120
2
-
180
120
4
240
220
mA
1
mA
2
mA
190
mA
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).
2. Refresh period is 32ms. Addresses are changed only one time during tCC(min).
PRELIMINARY
(October, 2001, Version 0.1)
6
AMIC Technology, Inc.
A45L9332A Series
AC Operating Test Conditions
(VDD = 3.3V ±0.3V, TA = 0°C to +70°C)
Parameter
Value
AC input levels
VIH/VIL = 2.4V/0.4V
Input timing measurement reference level
1.4V
Input rise and all time (See note3)
tr/tf = 1ns/1ns
Output timing measurement reference level
1.4V
Output load condition
See Fig.2
3.3V
1200Ω
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
VTT =1.4V
50Ω
Output
ZO=50Ω
OUTPUT
870Ω
30pF
3pF
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
AC Characteristics
(AC operating conditions unless otherwise noted)
-6
Symbol
tCC
Parameter
CAS
Latency
Min
3
6
-7
Max
Min
-8
Max
7
CLK cycle time
1000
Min
8
1000
CLK to valid
3
-
5.5
-
6
-
6.5
Output delay
2
-
-
-
7.5
-
7
tCH
CLK high pulse width
3
(October, 2001, Version 0.1)
-
ns
1,2
ns
2
ns
3
3
-
3
7
2.5
2.5
-
2
PRELIMINARY
2.5
2.5
1
10
tSAC
2.5
ns
8
1000
-
Output data hold time
Note
Max
2
tOH
Unit
3
AMIC Technology, Inc.
A45L9332A Series
AC Characteristics (continued)
(AC operating conditions unless otherwise noted)
-6
Symbol
tCL
tSS
Parameter
CAS
Latency
Min
3
2.5
CLK low pulse width
-7
Max
Min
-
3
2
Note
Max
Min
Max
-
3
-
ns
3
-
2.5
-
ns
3
3
2
Input setup time
2
Unit
2.5
-
2
-8
-
2.5
3
tSH
Input hold time
1
-
1
-
1
-
ns
3
1
-
1
-
1
-
ns
2
2
3
tSLZ
CLK to output in Low-Z
2
CLK to output
3
-
5.5
-
6
-
6.5
In Hi-Z
2
-
-
-
7.5
-
7
tSHZ
ns
*All AC parameters are measured from half to half.
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
PRELIMINARY
(October, 2001, Version 0.1)
8
AMIC Technology, Inc.
A45L9332A Series
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Symbol
Parameter
CAS
Latency
Version
-6
-7
-8
2
2
2
3
3
3
2
2
-
2
2
3
3
3
2
2
-
3
2
3
8
7
6
2
-
5
5
Unit
Note
CLK
1
CLK
1
CLK
1
CLK
1
3
tRRD(min)
Row active to row active delay
tRCD(min)
RAS to CAS delay
tRP(min)
Row precharge time
2
tRAS(min)
Row active time
3
tRAS(max)
tRC(min)
Row cycle time
tCDL(min)
Last data in new col. Address delay
tRDL(min)
Last data in row precharge
tBDL(min)
Last data in to burst stop
tCCD(min)
Col. Address to col. Address delay
tBPL(min)
Block write data-in to PRE command
tBWC(min)
Block write cycle time
µs
100
2
3
11
10
9
2
-
7
7
CLK
1
CLK
2
CLK
2
1
CLK
2
1
CLK
3
2
CLK
1
CLK
1,3
3
2
CLK
4
2
1
CLK
3
1
2
3
2
2
2
2
-
2
2
3
2
3
2
3
2
3
2
Number of valid output data
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. This parameter means minimum CAS to CAS delay at block write cycle only.
4. In case of row precharge interrupt, auto precharge and read burst stop.
PRELIMINARY
(October, 2001, Version 0.1)
9
AMIC Technology, Inc.
A45L9332A Series
Simplified Truth Table
Command
Register
CKEn-1 CKEn
WE DSF DQM A10 A9 A8~A0 Notes
L
H
Auto Refresh
Refresh
X
L
L
L
L
L
L
L
H
L
H
H
H
1,2
X
OP CODE
L
X
X
X
X
X
H
H
Entry
Self
Bank Active
& Row Addr.
RAS CAS
Mode Register Set
Special Mode Register Set
Refresh
CS
Exit
H
L
L
H
H
X
H
X
X
X
L
L
H
H
Write Per Bite Disable
Write Per Bit Enable
Read &
Auto Precharge Disable
Column Addr. Auto Precharge Enable
3
H
V
X
L
H
L
H
L
X
V
X
L
H
L
L
L
X
V
Block Write & Auto Precharge Disable
Column Addr. Auto Precharge Enable
H
X
L
H
L
L
H
X
V
Burst Stop
H
X
L
H
H
L
L
X
X
H
L
Exit
L
H
Entry
H
L
Precharge Power Down Mode
Exit
H
L
H
Entry
H
L
Bank Selection
Clock Suspend or
Active Power Down
Row Addr.
L
H
Both Banks
3
4,5
X
Write &
Auto Precharge Disable
Column Addr. Auto Precharge Enable
Precharge
3
L
H
L
DQM
H
No Operation Command
H
H
L
L
H
L
L
X
X
X
X
X
X
X
L
H
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
V
H
X
X
X
X
L
H
H
H
H
X
X
X
H
Column
Addr.
4,5,9
4
4,6
Column 4,5
Addr. 4,5,6,9
Column 4,5
Addr. 4,5,6,9
X
V
L
X
H
7
X
X
X
X
1,2,7
3
X
X
X
V
X
X
X
8
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note : 1. OP Code : Operand Code
A0~A10 : Program keys. (@MRS)
Color register exists only one per DQi which both banks share.
So dose Mask Register.
Color or mask is loaded into chip through DQ pin.
2. MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ’s are idle.
A new command can be issued at the next clock of MRS/SMRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
PRELIMINARY
(October, 2001, Version 0.1)
10
AMIC Technology, Inc.
A45L9332A Series
Simplified Truth Table
4. A10 : Bank select address.
If “Low” at read, (block) write, Row active and precharge, bank A is selected.
If “High” at read, (block) write, Row active and precharge, bank B is selected.
If A9 is “High” at Row precharge, A10 is ignored and both banks are selected.
5. It is determined at Row active cycle.
whether Normal/Block write operates in write per bit mode or not.
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit = I/O mask
(Block) Write with write per bit mode = Masked (Block ) Write
6. During burst read or write with auto precharge, new read/ (block) write command cannot be issued.
Another bank read/(block) write command can be issued at tPR after the end of burst.
7. Burst stop command is valid only t full page burst length.
8. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
9. Graphic features added to SDRAM’s original features.
If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ’s.
SGRAM vs SDRAM
Function
DSF
SGRAM
MRS
L
MRS
Bank Active
H
SMRS
Function
Write
L
H
L
H
Bank Active
Bank Active
with
with
Normal
Block
Write per bit
Write per bit
Write
Write
Disable
Enable
IF DSF is low, SGRAM functionality is identical to SDRAM functionality.
SGRAM can be used as an unified memory by the appropriate DSF control
→SDRAM = Graphic Memory + main Memory
PRELIMINARY
(October, 2001, Version 0.1)
11
AMIC Technology, Inc.
A45L9332A Series
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address
A10
A9
Function
RFU
W.B.L
(Note 1)
A8
A7
A6
TM
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
(Note 2)
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
Reserved
0
1
Vendor
0
0
1
-
1
Interleave
0
0
1
2
Reserved
1
0
Use
0
1
0
2
0
1
0
4
4
1
1
Only
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved
Reserved
Write Burst Length
A9
Length
1
0
1
Reserved
1
0
1
Reserved
Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
256(Full)
Reserved
(Note 3)
Special Mode Register Programmed with SMRS
Address
A10
A9
Function
A8
A7
X
A6
A5
LC
LM
Load Color
A6
A4
A3
A2
A1
A0
X
Load Mask
Function A5
Function
0
Disable
0
Disable
1
Enable
1
Enable
(Note 4)
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256bit) is available only at Sequential mode of burst type.
4. If LC and LM both high (1), data of mask and color register will be unknown.
PRELIMINARY
(October, 2001, Version 0.1)
12
AMIC Technology, Inc.
A45L9332A Series
Burst Sequence (Burst Length = 4)
Initial address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
Burst Sequence (Burst Length = 8)
Initial address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
Pixel to DQ Mapping (at BLOCK WRITE)
Column address
3 Byte
2 Byte
1 Byte
0 Byte
A2
A1
A0
I/O31 – I/O24
I/O23 – I/O16
I/O15 – I/O8
I/O7 – I/O0
0
0
0
DQ24
DQ16
DQ8
DQ0
0
0
1
DQ25
DQ17
DQ9
DQ1
0
1
0
DQ26
DQ18
DQ10
DQ2
0
1
1
DQ27
DQ19
DQ11
DQ3
1
0
0
DQ28
DQ20
DQ12
DQ4
1
0
1
DQ29
DQ21
DQ13
DQ5
1
1
0
DQ30
DQ22
DQ14
DQ6
1
1
1
DQ31
DQ23
DQ15
DQ7
PRELIMINARY
(October, 2001, Version 0.1)
13
AMIC Technology, Inc.
A45L9332A Series
Device Operations
Clock (CLK)
read, auto refresh, etc. The device deselect is also a NOP
and is entered by asserting CS high. CS high disables
The clock input is used as the reference for all SGRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with
CKE high all inputs are assumed to be in valid state (low or
high) for the duration of set up and hold time around
positive edge of the clock for proper functionality and ICC
specifications.
the command decoder so that RAS , CAS and WE , DSF
and all the address inputs are ignored.
Power-Up
The following sequence is recommended for POWER UP
1. Power must be applied to either CKE and DQM inputs to
pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.
The clock signal must also be asserted at the same time.
2. After VDD reaches the desired voltage, a minimum
pause of 200 microseconds is required with inputs in
NOP condition.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize
the internal circuitry.
5. Perform a MODE REGISTER SET cycle to program the
CAS latency, burst length and burst type as the default
value of mode register is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
Cf.) Sequence of 4 & 5 may be charged.
Clock Enable (CLK)
The clock enable (CKE) gates the clock onto SGRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock is suspended
form the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When both banks are in the idle state and CKE goes
low synchronously with clock, the SGRAM enters the power
down mode form the next clock cycle. The SGRAM remains
in the power down mode ignoring the other inputs as long
as CKE remains low. The power down exit is synchronous
as the internal clock is suspended. When CKE goes high at
least “tSS + 1 CLOCK” before the high going edge of the
clock, then the SGRAM becomes active from the same
clock edge accepting all the input commands.
Bank Select (A10)
This SGRAM is organized as two independent banks of
262,144 words X 32 bits memory arrays. The A10 inputs is
latched at the time of assertion of RAS and CAS to select
the bank to be used for the operation. When A10 is
asserted low, bank A is selected. When A10 is asserted
high, bank B is selected. The bank select A10 is latched at
bank activate, read, write mode register set and precharge
operations.
Mode Register Set (MRS)
Address Input (A0 ~ A9)
CAS , WE and DSF (The SGRAM should be in active
mode with CKE already high prior to writing the mode
register). The state of address pins A0~A9 and A10 in the
same cycle as CS , RAS , CAS , WE and DSF going low
is the data written in the mode register. One clock cycle is
required to complete the write in the mode register. The
mode register contents can be changed using the same
command and clock cycle requirements during operation as
long as both banks are in the idle state. The mode register
is divided into various fields depending on functionality. The
burst length field uses A0~A2, burst type uses A3,
addressing mode uses A4~A6, A7~A8 and A10 are used
for vendor specific options or test mode. And the write burst
length is programmed using A9. A7~A8 and A10 must be
set to low for normal SGRAM operation.
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies.
The mode register stores the data for controlling the various
operation modes of SGRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various
vendor specific options to make SGRAM useful for variety
of different applications. The default value of the mode
register is not defined, therefore the mode register must be
written after power up to operate the SGRAM. The mode
register is written by asserting low on CS , RAS ,
The 18 address bits required to decode the 262,144 word
locations are multiplexed into 10 address input pins
(A0~A9). The 10 bit row address is latched along with
RAS and A10 during bank activate command. The 8 bit
column address is latched along with CAS , WE and A10
during read or write command.
NOP and Device Deselect
When RAS , CAS and WE are high, the SGRAM
performs no operation (NOP). NOP does not initiate any
new operation, but is needed to complete operations which
require more than single clock like bank activate, burst
PRELIMINARY
(October, 2001, Version 0.1)
14
AMIC Technology, Inc.
A45L9332A Series
Device Operations (continued)
Burst Write
Bank Activate
The burst write command is similar to burst read command,
and is used to write data into the SGRAM consecutive clock
cycles in adjacent addresses depending on burst length
and burst sequence. By asserting low on CS , CAS and
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and CS with
desired row and bank addresses, a row access is initiated.
The read or write operation can occur after a time delay of
tRCD(min) from the time of bank activation. tRCD(min) is an
internal timing parameter of SGRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate and
read or write command should be calculated by dividing
tRCD(min) with cycle time of the clock and then rounding off
the result to the next higher integer. The SGRAM has two
internal banks on the same chip and shares part of the
internal circuitry to reduce chip area, therefore it restricts
the activation of both banks immediately. Also the noise
generated during sensing of each bank of SGRAM is high
requiring some time for power supplies recover before the
other bank can be sensed reliably. tRRD(min) specifies the
minimum time required between activating different banks.
The number of clock cycles required between different bank
activation must be calculated similar to tRCD specification.
The minimum time required for the bank to be active to
initiate sensing and restoring the complete row of dynamic
cells is determined by tRAS(min) specification before a
precharge command to that active bank can be asserted.
The maximum time any bank can be in the active state is
determined by tRAS(max). The number of cycles for both
tRAS(min) and tRAS(max) can be calculated similar to tRCD
specification.
WE with valid column address, a write burst is initiated.
The data inputs are provided for the initial address in the
same clock cycle as the burst write command. The input
buffer is deselected at the end of the burst length, even
though the internal writing may not have been completed
yet. The writing can not complete to burst length. The burst
write can be terminated by issuing a burst read and DQM
for blocking data inputs or burst write in the same or the
other active bank. The burst stop command is valid only at
full page burst length where the writing continues at the end
of burst and the burst is wrap around. The write burst can
also be terminated by using DQM for blocking data and
precharging the bank “tRDL” after the last data input to be
written into the active row. See DQM OPERATION also.
DQM Operation
The DQM is used to mask input and output operation. It
works similar to OE during read operation and inhibits
writing during write operation. The read latency is two
cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in the read cycle and
occurs in the same cycle during write cycle. DQM operation
is synchronous with the clock, therefore the masking occurs
for a complete cycle. The DQM signal is important during
burst interrupts of write with read or precharge in the
SGRAM. Due to asynchronous nature of the internal write,
the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is not
required. DQM is also used for device selection, byte
selection and bus control in a memory system. DQM0
controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2
controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31.
DQM masks the DQ’s by a byte regardless that the
corresponding DQ’s are in a state of WPB masking or Pixel
masking. Please refer to DQM timing diagram also.
Burst Read
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low
on CS and CAS with WE being high on the positive edge
of the clock. The bank must be active for at least tRCD(min)
before the burst read command is issued. The first output
appears CAS latency number of clock cycles after the issue
of burst read command. The burst length, burst sequence
and latency from the burst read command is determined by
the mode register which is already programmed. The burst
read can be initiated on any column address of the active
row. The address wraps around if the initial address does
not start from a boundary such that number of outputs from
each I/O are equal to the burst length programmed in the
mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to
keep the data output gapless. The burst read can be
terminated by issuing another burst read or burst write in
the same bank or the other active bank or a precharge
command to the same bank. The burst stop command is
valid only at full page burst length where the output dose
not go into high impedance at the end of burst and the
burst is wrap around.
PRELIMINARY
(October, 2001, Version 0.1)
Precharge
The precharge operation is performed on an active bank by
asserting low on CS , RAS , WE and A9 with valid A10 of
the bank to be precharged. The precharge command can
be asserted anytime after tRAS(min) is satisfied from the
bank activate command in the desired bank. “tRP” is defined
as the minimum time required to precharge a bank.
The minimum number of clock cycles required to complete
row precharge is calculated by dividing “tRP” with clock cycle
time and rounding up to the next higher integer. Care
should be taken to make sure that burst write is completed
or DQM is used to inhibit writing before precharge
15
AMIC Technology, Inc.
A45L9332A Series
data retention and low power operation of SGRAM. In self
refresh mode, the SGRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.
Device Operations (continued)
command is asserted. The maximum time any bank can be
active is specified by tRAS(max). Therefore, each bank has
to be precharged within tRAS(max) from the bank activate
command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when both banks are in
idle state.
The self refresh mode is entered from all banks idle state
by asserting low on CS , RAS , CAS and CKE with high
on WE . Once the self refresh mode is entered, only CKE
state being low matters, all the other inputs including clock
are ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of “tRC” before the SGRAM
reaches idle state to begin normal operation. If the system
uses burst auto refresh during normal operation, it is
recommended to used burst 2048 auto refresh cycles
immediately after exiting self refresh.
Auto Precharge
The precharge operation can also be performed by using
auto precharge. The SGRAM internally generates the
timing to satisfy tRAS(min) and “tRP” for the programmed
burst length and CAS latency. The auto precharge
command is issued at the same time as burst read or burst
write by asserting high on A9. If burst read or burst write
command is issued with low on A9, the bank is left active
until a new command is asserted. Once auto precharge
command is given, no new commands are possible to that
particular bank until the bank achieves idle state.
Define Special Function (DSF)
The DSF controls the graphic applications of SGRAM. If
DSF is tied to low, SGRAM function is 256K X 32 X 2 Bank
SDRAM. SDRAM can be used as an unified memory by the
appropriate DSF command. All the graphic function mode
can be entered only by setting DSF high when issuing
commands which otherwise would be normal SDRAM
commands.
SDRAM functions such as RAS Active, Write, and WCBR
Both Banks Precharge
Both banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS and
WE with high on A9 after both banks have satisfied
tRAS(min) requirement, performs precharge on both banks.
At the end of tRP after performing precharge all, both banks
are in idle state.
change to SGRAM functions such as RAS Active with
WPB, Block Write and SWCBR respectively. See the
sessions below for the graphic functions that DSF controls.
Auto Refresh
Special Mode Register Set (SMRS)
The storage cells of SGRAM need to be refreshed every
32ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on CS , RAS and CAS with high on CKE
There are two kinds of special mode registers in SGRAM.
One is color register and the other is mask register. Those
usage will be explained at “WRITE PER BIT” and ”BLOCK
WRITE” session. When A5 and DSF goes high in the same
cycle as CS , RAS , CAS and WE going low, load mask
register (LMR) process is executed and the mask registers
are filled with the masks for associated DQ’s through DQ
pins. And when A6 and DSF goes high in the same cycle
as CS , RAS , CAS and WE going low, load color
register (LCR) process is executed and the color register is
filled with color data for associated DQ’s through the DQ
pins. If both A5 and A6 are high at SMRS, data of mask
and color cycle is required to complete the write in the
mask register and the color register at LMR and LCR
respectively. The next clock of LMR or LCR, a new
commands can be issued. SMRS, compared with MRS, can
be issued at the active state under the condition that DQ’s
are idle. As in write operation, SMRS accepts the data
needed through DQ pins. Therefore it should be attended
not to induce bus contention. The more detailed materials
can obtained by referring corresponding timing diagram.
and WE . The auto refresh command can only be asserted
with both banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by “tRC(min)”. The minimum number of clock
cycles required can be calculated by driving “tRC” with clock
cycle time and then rounding up to the next higher integer.
The auto refresh command must be followed by NOP’s until
the auto refresh operation is completed. Both banks will be
in the idle state at the end of auto refresh operation. The
auto refresh is the preferred refresh mode when the
SGRAM is being used for normal data transactions. The
auto refresh cycle can be performed once in 15.6us or a
burst of 2048 auto refresh cycles once in 32ms.
Self Refresh
The self refresh is another refresh mode available in the
SGRAM. The self refresh is the preferred refresh mode for
PRELIMINARY
(October, 2001, Version 0.1)
16
AMIC Technology, Inc.
A45L9332A Series
Device Operations (continued)
Timing Diagram to Illustrate tBWC
Write Per Bit
Write per bit (i.e. I/O mask mode) for SGRAM is a function
that selectively masks bits of data being written to the
devices. The mask is stored in an internal register and
applied to each bit of data written when enabled. Bank
active command with DSF = High enabled write per bit
operations is stored in the mask register accessed by
SWCBR (Special Mode Register Set Command). When a
mask bit = 1, the associated data bit is written when a write
command is executed and write per bit has been enabled
for the bank being written. When a mask bit = 0, the
associated data bit is unaltered when a write command is
executed and the write per bit has been enabled for the
bank being written. No additional timing conditions are
required for write per bit operations. Write per bit writes can
be either single write, burst writes or block writes. DQM
masking is the same for write per bit and non-WPB write.
0
2
Clock
CKE
High
CS
RAS
CAS
WE
Block Write
DSF
Block write is a feature allowing the simultaneous writing of
consecutive 8 columns of data within a RAM device during
a single access cycle. During block write the data to be
written comes from an internal “color” register and DQ I/O
pins are used for independent column selection. The block
of column to be written is aligned on 8 column boundaries
and is defined by the column address with the 3 LSB’s
ignored. Write command with DSF = 1enables block write
for the associated bank. A write command with DSF = 0
enables normal write for the associated bank. The block
width is 8 column where column = “n” bits for by “n” part.
The color register is the same width as the data port of the
chip. It is written via a SWCBR where data present on the
DQ pin is to be coupled into the internal color register. The
color register provides the data masked by the DQ column
select, WPB mask (If enabled), and DQM byte mask.
Column data masking (Pixel masking) is provided on an
individual column basis for each byte of data. The column
mask is driven on the DQ pins during a block write
command. The DQ column mask function is segmented on
a per bit basis (i.e. DQ[0:7] provides the column mask for
data bits[0:7], DQ[8:15] provides the column mask for data
bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9
masks column [1] for data its [8:15], etc). Block writes are
always non-burst, independent of the burst length that has
been programmed into the mode register. Back to back
block writes are allowed provided that the specified block
write cycle time (tBWC) is satisfied. If write per bit was
enabled by the bank active command with DSF = 1, then
write per bit masking of the color register data is enabled.
If write per bit was disabled by a bank active command with
DSF = 0, the write per bit masking of the color register data
is disabled. DQM masking provides independent data byte
masking during block write exactly the same as it does
during normal write operations, except that the control is
extended to the consecutive 8 columns of the block write.
PRELIMINARY
1
(October, 2001, Version 0.1)
1 CLK BW
17
AMIC Technology, Inc.
A45L9332A Series
Summary of 2M Byte SGRAM Basic Features and Benefits
Features
256K X 32 X 2 SGRAM
Benefits
Better interaction between memory and system without wait-state of
asynchronous DRAM.
Interface
Synchronous
High speed vertical and horizontal drawing.
High operation frequency allows performance gain for SCROLL, FILL,
and BitBLT.
Bank
Pseudo-infinite row length by on-chip interleaving operation.
2 ea
Page Depth / 1 Row
Total Page Depth
Burst Length (Read)
Burst Length (Write)
Hidden row activation and precharge.
256 bit
High speed vertical and horizontal drawing.
2048 bytes
High speed vertical and horizontal drawing
1,2,4,8 Full Page
Programmable burst of 1,2,4,8 and full page transfer per column
addresses.
1,2,4,8 Full Page
Programmable burst of 1,2,4,8 and full page transfer per column
addresses.
BRSW
Burst Type
Sequential & Interleave
CAS Latency
2,3
Switch to burst length of 1 at write without MRS
Compatible with Intel and Motorola CPU based system.
Programmable CAS latency.
High speed FILL, CLEAR, Text with color registers.
Block Write
8 Columns
Maximum 32 byte data transfers (e.g. for 8bpp : 32 pixels) with plane
and byte masking functions.
Color Register
1 ea.
A and B bank share.
Mask Register
1 ea.
Write-per-bit capability (bit plane masking). A and B banks share.
DQM0-3
Mask function
Write per bit
Byte masking (pixel masking for 8bpp system) for data-out/in
Each bit of the mask register directly controls a corresponding bit
plane.
Pixel Mask at Block Write Byte masking (pixel masking for 8bpp system) for color by DQi
Basic feature And Function Descriptions
1. CLOCK Suspend
1) Click Suspended During Write (BL=4)
2) Clock Suspended During Read (BL=4)
CLK
CMD
WR
RD
CKE
Masked by CKE
Masked by CKE
Internal
CLK
DQ(CL2)
D0
D1
D2
D3
DQ(CL3)
D0
D1
D2
D3
Q0
Q1
Q0
Not Written
Q2
Q3
Q1
Q2
Q3
Suspended Dout
Note: CLK to CLK disable/enable=1 clock
PRELIMINARY
(October, 2001, Version 0.1)
18
AMIC Technology, Inc.
A45L9332A Series
2. DQM Operation
2) Read Mask (BL=4)
1) Write Mask (BL=4)
CLK
CMD
WR
RD
DQMi
Masked by CKE
DQ(CL2)
D0
DQ(CL3)
D0
D1
D1
Masked by CKE
D3
Q0
Hi-Z
Hi-Z
D3
DQM to Data-in Mask = 0CLK
Q1
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2
2) Read Mask (BL=4)
CLK
CMD
RD
CKE
DQM
Q0
DQ(CL2)
Hi-Z
Hi-Z
DQ(CL3)
Q2
Q1
Hi-Z
Hi-Z
Q4
Q3
Hi-Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
* Note : 1. There are 4 DQMi (I=0~3).
Each DQMi masks 8 DQi’s. (1 Byte, 1 Pixel for 8bbp).
2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.
PRELIMINARY
(October, 2001, Version 0.1)
19
AMIC Technology, Inc.
A45L9332A Series
3. CAS Interrupt (I)
1) Read intreupted by Read (BL=4) Note 1
CKL
CMD
RD
ADD
A
RD
B
DQ(CL2)
QA0
DQ(CL3)
QB0
QB1 QB2
QB3
QA0
QB0
QB2
QB1
QB3
tCCD
Note2
2) Write interrupted by (Block) Write (BL =2)
3) Write interrupted by Read (BL =2)
CKL
CMD
WR
WR
ADD
A
B
DQ
DA0
DB0
tCCD
WR
tCCD
Note2
WR
BW
tCCD
Note2
C
D
DC0
Pixel
RD
A
Note2
B
Note4
DB1
tCDL
tCDL
Note3
Note3
DQ(CL2)
DA0
DQ(CL3)
DA0
QB0
Pixel
QB0
QB1
tCDL
Note3
2) Block Write to Block Write
CKL
CMD
BW
BW
ADD
A
B
Note4
DQ
Pixel Pixel
tBWC
Note5
Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.
By “ CAS Interrupt”, to stop burst read/write by CAS access; read, write and block write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. ( = 1CLK).
4. Pixel : Pixel mask.
5. tBWC : Block write minimum cycle time.
PRELIMINARY
(October, 2001, Version 0.1)
20
AMIC Technology, Inc.
A45L9332A Series
4. CAS Interrupt (II) : Read Interrupted Write & DQM
(1) CL=2, BL=4
CLK
i) CMD
RD
WR
DQM
D0
DQ
ii) CMD
Hi-Z
DQ
D0
RD
iii) CMD
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
RD
DQM
D1
WR
DQM
Hi-Z
D0
DQ
iv) CMD
RD
WR
DQM
Q0
DQ
Hi-Z
Note 1
D0
D3
(2) CL=3, BL=4
CLK
i) CMD
RD
WR
DQM
D0
DQ
ii) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
D0
DQ
iii) CMD
RD
WR
DQM
D0
WR
DQ
iv) CMD
RD
WR
DQM
Hi-Z
DQ
v) CMD
D0
RD
WR
DQM
Q0
DQ
Hi-Z
Note 2
D0
D3
* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.
PRELIMINARY
(October, 2001, Version 0.1)
21
AMIC Technology, Inc.
A45L9332A Series
5. Write Interrupted by Precharge & DQM
CLK
Note 2
CMD
WR
PRE
Note 1
DQM
DQ
D0
D1
D2
D3
Masked by DQM
Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL=4)
2) Block Write
CLK
CLK
CMD
WR
CMD
BW
DQ
D0
DQ
Pixel
PRE
D1
D2
D3
tRDL
Note 1
PRE
tBPL
Note 1
3) Read (BL=4)
CLK
CMD
RD
Note 2
PRE
DQ(CL2)
Q0
DQ(CL3)
Q1
Q2
Q3
Q0
Q1
Q2
1
Q3
2
7. Auto Precharge
2) Block Write
1) Normal Write (BL=4)
CLK
CMD
DQ
CLK
WR
D0
D1
D2
D3
Note 3
CMD
BW
DQ
(CL 2,3)
Pixel
tBPL
Auto Precharge Starts
Note 3
tRP
Auto Precharge Starts
3) Read (BL=4)
CLK
CMD
DQ(CL2)
RD
Q0
DQ(CL3)
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Note 3
Auto Precharge Starts
* Note : 1. tBPL : Block write data-in to PRE command delay.
2. Number of valid output data after Row Precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other active bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
8. Burst Stop & Precharge Interrupt
1) Write Interrupted by Precharge (BL=4)
2) Write Burst Stop (Full Page Only)
CLK
CMD
CLK
WR
PRE
CMD
WR
DQ
D0
STOP
DQM
DQ
D0
D1
D2
D3
tRDL
D2
Note 1
tBDL
3) Read Interrupted by Precharge (BL=4)
4) Read Burst Stop (Full Page Only)
CLK
CMD
D1
CLK
RD
PRE
DQ(CL2)
Q0
DQ(CL3)
CMD
Note 3
Q1
Q0
1
RD
STOP
DQ(CL2)
Q1
2
Q0
DQ(CL3)
Note 3
Q1
Q0
1
Q1
2
9. MRS & SMRS
2) Mode Register Set
2) Special Mode Register Set
CLK
CLK
Note 4
CMD
PRE
MRS
tRP
CMD
ACT
SMRS ACT SMRS SMRS
BW
1CLK 1CLK 1CLK 1CLK
1CLK
Note : 1.tRDL : 2CLK, Last Data in to Row Precharge.
2. tBDL : 1CLK, Last Data in to Burst Stop Delay.
3. Number of valid output data after Row precharge or burst stop : 1,2 for CAS latency=2,3 respectively.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at all bank precharge state.
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down) Exit
CLK
CLK
CKE
CKE
tSS
Internal
CLK
tSS
Internal
CLK
Note 1
RD
CMD
Note 2
NOP
CMD
ACT
11. Auto Refresh & Self Refresh
Note 3
1) Auto Refresh
~
~
CLK
Note 4
CKE
Note 5
PRE
AR
CMD
~~
~
~
~
~
Internal
CLK
CMD
tRP
tRC
Note 6
CLK
~
~
~
~
2) Self Refresh
Note 4
PRE
SR
CMD
~
~
CMD
~
~
~
~
CKE
tRP
tRC
* Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended.
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
12. About Burst Type Control
Basic
MODE
Sequential counting
Interleave counting
PseudoDecrement Sequential
Counting
PseudoMODE
Pseudo-Binary Counting
Random
MODE
Random column Access
tCCD = 1 CLK
At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
At MRS A3 = “1”. (See to Interleave Counting Mode)
Starting Address LSB 3 bits A0-2 should be “000” or “111”[email protected]=8.
--if LSB = “000” : Increment Counting.
--if LSB= “111” : Decrement Counting.
For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8)
[email protected] write, LSB=”000”, Accessed Column in order 0-1-2-3-4-5-6-7
[email protected] read, LSB=”111”, Accessed Column in order 7-6-5-4-3-2-1-0
At BL=4, same applications are possible. As above example, at Interleave
Counting mode, by confining starting address to some values, PseudoDecrement Counting Mode can be realized. See the BURST SEQUENCE TABLE
carefully.
At MRS A3 = “0”. (See to Sequential Counting Mode)
A0-2 = “111”. (See to Full Page Mode)
Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be
realized.
[email protected] Sequential Counting Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8)
[email protected] Pseudo-Binary Counting,
Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command)
Note. The next column address of 256 is 0
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.
13. About Burst Length Control
At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “001”.
2
At auto precharge, tRAS should not be violated.
4
At MRS A2,1,0 = “010”
8
At MRS A2,1,0 = “011”.
At MRS A2,1,0 = “111”.
Full Page
Wrap around mode (Infinite burst length) should be stopped by burst stop,
RAS interrupt or CAS interrupt.
At MRS A9=”1”.
BRSW
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
8 Column Block Write. LSB A0-2 are ignored. Burst length=1.
Block Write
tBWC should not be violated.
At auto precharge, tRAS should not be violated.
tBDL=1, Valid DQ after burst stop is 1,2 for CL=2,3 respectively
Burst Stop
Using burst stop command, it is possible only at full page burst length.
Before the end of burst, Row precharge command of the same bank
RAS Interrupt
Stops read/write burst with Row precharge.
(Interrupted by Precharge) tRDL=2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively
During read/write burst with auto precharge, RAS interrupt cannot be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
CAS Interrupt
During read/write burst with auto precharge, CAS interrupt can not be issued.
1
Basic
MODE
Special
MODE
Random
MODE
Interrupt
MODE
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
14. Mask Functions
1) Normal Write
I/O masking : By Mask at Write per Bit Mode, the selected bit planes keep the original data.
If bit plane 0,3,7,9,15,22,24, and 31 keep the original value.
i) STEP
•• SMRS (LMR) : Load mask [31-0]=”0111,1110,1011,1111,0111,1101,0111,0110”
•• Row Active with DSF “H” : Writ Per Bit Mode Enable
•• Perform Normal Write
ii) ILLUSTRATION
I/O(=DQ)
External Data-in
DQMi
Mask Register
Before Write
After Write
31
24
11111111
DQM3=0
01111110
00000000
01111110
23
16
11111111
DQM2=0
10111111
00000000
10111111
15
8
0000000
DQM1=0
0111101
1111111
1000010
7
0
00000000
DQM0=1
01110110
11111111
11111111
Note 1
2) Block Write
Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.
If Pixel 0,4,9,13,18, 22, 27 and 31 keep the original white color.
Assume 8bpp,
White = “0000,0000”, Red = “1010,0011”, Green = “1110,0001”, Yellow = “0000,1111”, Blue = “1100,0011”
i) STEP
•• SMRS(LCR) : Load color (for 8bbp, through X32 DQ color 0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= “1100,0011,1110,0001,0000,1111,1010,0011”
•• Row Active with DSF “L” : I/O Mask by Write Per Bit Mode Disable
•• Block write with DQ[31-0] = “0111,0111,1011,1011,1101,1101,1110,1110”
ii) ILLUSTRATION
I/O(=DQ)
31
24
23
16
15
8
7
0
DQMi
DQM3=0
DQM2=0
DQM1=0
DQM0=1
Color Register
Color3=Blue
Color2=Green
Color1=Yellow
Color0=Red
000
White DQ24=H
White DQ16=H
White DQ8=H
White DQ0=L
Before
001
White DQ25=H
White DQ17=H
White DQ9=L
White DQ1=H
Block
010
White
DQ26=H
White
DQ18=L
White
DQ10=H
White DQ2=H
Write
011
White
DQ27=L
White
DQ19=H
White
DQ11=H
White DQ3=H
&
100
White DQ28=H
White DQ20=H
White DQ12=H
White DQ4=L
DQ
101
White
DQ29=H
White
DQ21=H
White
DQ13=L
White
DQ5=H
(Pixel
110
White DQ30=H
White DQ22=L
White DQ14=H
White DQ6=H
data)
111
White DQ31=L
White DQ23=H
White DQ15=H
White DQ7=H
000
Blue
Green
Yellow
White
001
Blue
Green
White
White
010
Blue
White
Yellow
White
After
011
White
Green
Yellow
White
Block
100
Blue
Green
Yellow
White
Write
101
Blue
Green
White
White
110
Blue
White
Yellow
White
111
White
Green
Yellow
White
Note 2
* Note : 1. DQM byte masking.
2. At normal write, One column is selected among columns decoded by A2-0 (000-111)
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
(Continued)
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TANLE.
Assume 8bpp,
White = “0000,0000”, Red = “1010,0011”, Green = “1110,0001”, Yellow = “0000,1111”, Blue = “1100,0011”
i) STEP
•• SMRS (LCR) : Load color (for 8bpp, through X 32 DQ color0-3 are loaded into color registers)
Load (color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= “1100,0011,1110,0001,0000,1111,1010,0011”
••SMRS (LMR) : Load mask, Mask[31-0] = “1111,1111,1101,1101,0100,0010,0111,0110”
→ Byte 3:No I/O Masking; Byte 2:I/O Masking; Byte 1:I/O and Pixel Masking; Byte 0:DQM Byte Masking
•• Row Active with DSF “H” : I/O Mask by Write Per Bit Mode Enable
•• Block Write with DQ[31-0] = “0111,0111,1111,1111,0101,0101,1110,1110”
(Pixel Mask)
ii) ILLUSTRATUON
I/O(=DQ)
Color Register
DQMi
Mask Register
Before Write
After Write
31
24
Blue
11000011
DQM3=0
11111111
Yellow
00001111
Blue
11000011
23
16
Green
11100001
DQM2=0
11011101
Yellow
00001111
Blue
11000011
15
8
Yellow
00001111
DQM1=0
01000010
Green
11100001
Red
10100011
7
0
Red
10100011
DQM0=1
01110110
White
00000000
White
00000000
Note 1
I/O(=DQ)
31
24
DQMi
DQM3=0
Color Register
Color3=Blue
000
Yellow DQ24=H
Before
001
Yellow DQ25=H
Block
010
Yellow DQ26=H
Write
011
Yellow DQ27=L
&
100
Yellow DQ28=H
DQ
101
Yellow DQ29=H
(Pixel
110
Yellow DQ30=H
data)
111
Yellow DQ31=L
000
Blue
001
Blue
010
Blue
After
011
Yellow
Block
100
Blue
Write
101
Blue
110
Blue
111
Yellow
Note 2
PIXEL MASK
23
16
DQM2=0
Color2=Green
Yellow DQ16=H
Yellow DQ17=H
Yellow DQ18=H
Yellow DQ19=H
Yellow DQ20=H
Yellow DQ21=H
Yellow DQ22=H
Yellow DQ23=H
Blue
Blue
Blue
Blue
Blue
Blue
Blue
Blue
15
8
DQM1=0
Color1=Yellow
Green DQ8=H
Green DQ9=L
Green DQ10=H
Green DQ11=H
Green DQ12=H
Green DQ13=L
Green DQ14=H
Green DQ15=L
Red
Green
Red
Green
Red
Green
Red
Green
I/O MASK
PIXEL & I/O MASK
7
0
DQM0=1
Color0=Red
White DQ0=L
White DQ1=H
White DQ2=H
White DQ3=H
White DQ4=L
White DQ5=H
White DQ6=H
White DQ7=H
White
White
White
White
White
White
White
White
Note 1
BYTE MASK
* Note : 1. DQM byte masking.
2. At normal write, One column is selected among columns decoded by A2-0 (000-111)
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
Power On Sequence & Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CS
tRP
tRC
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
A9/AP
~
~
A10/BA
~
~
ADDR
~
~
CAS
~
~
~
~
RAS
Ra
KEY
BS
KEY
Ra
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
DSF
KEY
~
~
~
~
WE
High-Z
DQ
Precharge
(All Banks)
Auto Refresh
~
~
High level is necessary
~
~
DQM
~
~
High level is necessary
~
~
CKE
Auto Refresh
Mode Regiser Set
Row Active
(Write per Bit
Enable or Disable)
: Don't care
PRELIMINARY
(October, 2001, Version 0.1)
28
AMIC Technology, Inc.
A45L9332A Series
Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCL
tCC
High
CKE
tRAS
tRC
tSH
*Note 1
CS
tSS
tRCD
tRP
tSH
RAS
tSS
tCCD
tSH
CAS
tSS
tSH
ADDR
tSS
Ra
Ca
Cb
tSS
Cc
Rb
tSH
*Note 2,3
*Note 2
A10
BS
A9
Ra
*Note 2,3
BS
*Note 2,3
BS
*Note 3
BS
*Note 3
*Note 4
*Note 2
BS
*Note 3
BS
*Note 4
Rb
tSH
WE
tSS
*Note 5
*Note 6
DSF
*Note 5
*Note 3
tSS
tSH
tSS
tSH
DQM
tRAC
tSH
tSAC
Qa
DQ
tSLZ
tOH
Db
Qc
tSS
tSHZ
Row Active
(Write per Bit
Enable or
Disable)
Read
Write
or
Block Write
Read
Precharge
Row Active
(Write per Bit
Enable or
Disable
: Don't care
PRELIMINARY
(October, 2001, Version 0.1)
29
AMIC Technology, Inc.
A45L9332A Series
* Note : 1. All inputs can be don’t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by A10.
A10
Active & Read/Write
0
Bank A
1
Bank B
3. Enable and disable auto precharge function are controlled by A9 in read/write command.
A9
0
1
A10
Operation
0
Disable auto precharge, leave bank A active at end of burst.
1
Disable auto precharge, leave bank B active at end of burst.
0
Enable auto precharge, precharge bank A at end of burst.
1
Enable auto precharge, precharge bank B at end of burst.
4. A9 and A10 control bank precharge when precharge command is asserted.
A9
A10
Precharge
0
0
Bank A
0
1
Bank B
1
X
Both Bank
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.
A10
0
1
DSF
Operation
L
Bank A row active, disable write per bit function for bank A
H
Bank A row active, enable write per bit function for bank A
L
Bank B row active, disable write per bit function for bank B
H
Bank B row active, enable write per bit function for bank B
6. Block write/normal write is controlled by DSF
PRELIMINARY
DSF
Operation
Minimum cycle time
L
Normal write
tCCD
H
Block write
tBWC
(October, 2001, Version 0.1)
30
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
tRC
*Note 1
CS
t RCD
RAS
*Note 2
CAS
ADDR
Ra
Ca0
Rb
Cb0
A10
A9
Ra
Rb
WE
DSF
DQM
t OH
DQ
(CL = 2)
Qa0
tRAC
*Note 3
Qa1
tSAC
Qa2
Qa3
Db0
Db1
*Note 4
t SHZ
Db2
Db3
tRDL
tOH
DQ
(CL = 3)
Qa0
t RAC
*Note 3
Row Active
(A-Bank)
Qa1
Qa3
tSHZ
t SAC
Read
(A-Bank)
Qa2
Precharge
(A-Bank)
Db0
*Note 4
Row Active
(A-Bank)
Db1
Db2
Db3
tRDL
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after tSHZ from the clock.
3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
At Full page bit burst, burst is wrap-around.
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
Page Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
tRCD
RAS
*Note 2
CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
A10
A9
Ra
tRDL
tCDL
WE
*Note 2
DSF
*Note1
*Note3
DQM
DQ
(CL=2)
Qa0
DQ
(CL=3)
Row Active
(A-Bank)
Read
(A-Bank)
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Dc0
Dc1
Dd0
Dd1
Write
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
Block Write Cycle (with Auto Precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
*Note 2
ADDR
RAa
CAa
CAb
RBa
CBa
CBb
Pixel
Mask
Pixel
Mask
A10
A9
RAa
RBa
WE
DSF
tBWC
DQM
*Note 1
Pixel
Mask
DQ
Row Active with
Write-per-Bit
Enable
(A-Bank)
Pixel
Mask
Masked
Block Write
(A-Bank)
Row Active
(B-Bank)
Block Write with
Auto Precharge
(B-Bank)
Masked
Block Write with
Auto Precharge
(A-Bank)
Block Write
(B-Bank)
: Don't care
*Note : 1. Column Mask (DQi=L : Mask, DQi=H : Non Mask)
2. At Block Write, CA0-2 are ignored.
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
SMRS and Block/Normal Write @ Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
*Note1
A0-2
RAa
RBa
CBa
A3,4,7,8
RAa
CAa
RBa
CBa
A5
RAa
CAa
RBa
CBa
A6
RAa
CAa
RBa
CBa
A9
RAa
CAa
A10
WE
DSF
DQM
DQ
I/O
Mask
Color
Load Color
Register
Pixel
Mask
Row Active
with WPB*
Enable
(B-Bank)
Load Color
Register
Row Active
with WPB*
Enable
(A-Bank)
I/O
Mask
Masked
Bolck Write
(A-Bank)
Color
DBa0
DBa1
DBa2
DBa3
Load Color
Register
Load Mask Register
WPB* : Write-Per-Bit
Masked Write
with Auto
Precharge
(B-Bank)
: Don't care
* Note : 1. At the next clock of special mode set command, new command is possible.
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
Page Read Cycle at Different Bank @Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
*Note 1
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
A10
A9
RAa
RBb
WE
DSF
Low
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(B-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
: Don't care
* Note : 1. CS can be don’t care when RAS, CAS and
WE
are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.
PRELIMINARY
(October, 2001, Version 0.1)
35
AMIC Technology, Inc.
A45L9332A Series
Page Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
ADDR
RAa
Key
CAa
RBb
CBb
CAc
CBd
A10
A9
RAa
RBb
tCDL
WE
DSF
DQM
DQ
Mask
DAa0 DAa1 DAa2
Load Mask
Register
Row Active
(B-Bank)
Row Active with
Write-Per-Bit
enable
(A-Bank)
PRELIMINARY
DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2 DAc3 DBd0 DBd1 DBd2 DBd3
Write
(B-Bank)
Masked Write
with auto
precharge
(A-Bank)
Masked Write
(A-Bank)
Write with auto
Precharge
(B-Bank)
: Don't care
(October, 2001, Version 0.1)
36
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
A10
A9
RAa
RBb
RAc
tCDL
*Note 1
WE
DSF
DQM
DQ
(CL=2)
QAa0
DQ
(CL=3)
Row Active
(A-Bank)
QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
Read
(A-Bank)
Precharge
(A-Bank)
Write
(B-Bank)
Row Active
(B-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
: Don't care
* Note : 1. tCDL should be met to complete write.
PRELIMINARY
(October, 2001, Version 0.1)
37
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle with Auto Precharge I @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
ADDR
RAa
RBb
RAa
RBb
CAa
CBb
A10
A9
WE
DSF
DQMi
DQ
(CL=2)
QAa0
DQ
(CL=3)
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
QAa1
QAa2 QAa3
QAa0
QAa1 QAa2
Auto Precharge
Start Point
(A-Bank)
QAa3
DBb0
DBb1
DBb2
DBb3
DBb0
DBb1
DBb2
DBb3
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
Row Active
(B-Bank)
: Don't care
*Note : 1. tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode and Block write)
PRELIMINARY
(October, 2001, Version 0.1)
38
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle with Auto Precharge II @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
ADDR
Ra
Rb
Ra
Rb
Ca
Cb
Ra
Ca
A10
A9
Ra
WE
DSF
DQM
Qa0
DQ
(CL=2)
DQ
(CL=3)
Row Active
(A-Bank)
Read with
Auto Pre
Charge
(A-Bank)
Qa1
Qb0
Qb1
Qb2
Qb3
Qa0
Qa1
Qb0
Qb1
Qb2
Read without
Auto Precharge
(B-Bank)
Auto Precharge
Strart Point
(A-Bank) *Note 1
Precharge
(B-Bank)
Qb3
Row Active
(A-Bank)
Da0
Da1
Da0
Da1
Write with
Auto Precharge
(A-Bank)
Row Active
(B-Bank)
: Don't care
* Note : 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point.
- Any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
PRELIMINARY
(October, 2001, Version 0.1)
39
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle with Auto Precharge III @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
ADDR
Ra
Ca
Rb
Cb
A10
A9
Ra
Rb
WE
DSF
DQM
DQ
(CL=2)
Qa0
DQ
(CL=3)
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qb0
Qa3
Qb1
Qb2
Qb3
Qb0
Qb1
Db2
Db3
* Note 1
Row Active
(A-Bank)
Read with
Auto Preharge
(A-Bank)
Auto Precharge Read with
Start Point Auto Precharge
(B-Bank)
(A-Bank)
Row Active
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
: Don't care
* Note : 1. Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point
PRELIMINARY
(October, 2001, Version 0.1)
40
AMIC Technology, Inc.
A45L9332A Series
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full Page Only)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
ADDR
RAa
CAa
CAb
A10
* Note 1
A9
* Note 1
RAa
WE
DSF
DQM
* Note 2
DQ
(CL=2)
QAa0
1
1
QAa1
QAa2
QAa3 QAa4
QAb0 QAb1 QAb2 QAb3
QAa0
QAa1
QAa2 QAa3 QAa4
QAb4 QAb5
2
DQ
(CL=3)
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
2
QAb0 QAb1
QAb2 QAb3
Read
(A-Bank)
QAb4
QAb5
Precharge
(A-Bank)
: Don't care
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQ’s after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
PRELIMINARY
(October, 2001, Version 0.1)
41
AMIC Technology, Inc.
A45L9332A Series
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full Page Only)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
ADDR
RAa
CAa
CAb
A10
* Note 1
A9
* Note 1
RAa
tBDL
tRDL
WE
DSF
* Note 3
DQM
* Note 2
DAa0 DAa1
DQ
Row Active
(A-Bank)
DAa2 DAa3 DAa4
Write
(A-Bank)
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
Burst Stop
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of burst stop command cannot be written into corresponding memory cell.
It is defined by AC parameter of tBDL(=1CLK).
3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of tRDL(2=CLK).
DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
4. Burst stop is valid only at full page burst length.
PRELIMINARY
(October, 2001, Version 0.1)
42
AMIC Technology, Inc.
A45L9332A Series
Burst Read Single Bit Write Cycle @Burst Length=2, BRSW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
* Note 2
CAS
ADDR
RAa
CAa
RBb
RAc
CAb
CBc
CAd
A10
A9
RBb
RAa
RAc
WE
DSF
DQM
DQ
(CL=2)
DAa0
DQ
(CL=3)
DAa0
Row Active
(A-Bank)
QAb0
QAb1
DBc0
QAb0 QAb1
DBc0
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
QAd0
QAd1
QAd0
Read
(A-Bank)
QAd1
Precharge
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
: Don't care
* Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
The next cycle starts the precharge.
3. WPB function is also possible at BRSW mode.
PRELIMINARY
(October, 2001, Version 0.1)
43
AMIC Technology, Inc.
A45L9332A Series
Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cc
Cb
A10
A9
Ra
WE
DSF
* Note 1
DQM
Qa0
DQ
Qa1
Qa2
Qa3
tSHZ
Row Active
Read
Clock
Suspension
Qb0
Qb1
Dc0
Dc2
tSHZ
Read
Write
DQM
Read DQM
Write
Clock
Suspension
: Don't care
* Note : 1. DQM needed to prevent bus contention.
PRELIMINARY
(October, 2001, Version 0.1)
44
AMIC Technology, Inc.
A45L9332A Series
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
~
~
~
~
tSS
~
~
0
CLOCK
* Note 2
tSS
tSS
tSS
CKE
~
~
* Note 1
*Note 3
~
~
~
~
~
~
CS
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
ADDR
Ra
~
~
~
~
~
~
~
~
A10
~
~
~
~
~
~
A9
Ra
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
Precharge
Power-down
Entry
~
~
DQ
~
~
DQM
~
~
DSF
~
~
~
~
WE
Ca
~
~
CAS
~
~
RAS
Precharge
Power-down
Exit
Row Active
Qa0
Read
Qa1
Qa2
Precharge
Active
Power-down
Exit
Active
Power-down
Entry
: Don't care
* Note : 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least “1CLK + tSS” prior to Row active command.
3. Cannot violate minimum refresh specification. (32ms)
PRELIMINARY
(October, 2001, Version 0.1)
45
AMIC Technology, Inc.
A45L9332A Series
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
* Note 4
* Note 2
tSS
CKE
* Note 1
tRC min.
~
~
~
~
~
~
~
~
CLOCK
* Note 6
~
~
* Note 3
~
~
~
~
tSS
* Note 5
~
~
~
~
~
~
RAS
~
~
~
~
CS
* Note 7
* Note 7
~
~
~
~
~
~
~
~
CAS
~
~
~
~
~
~
~
~
ADDR
~
~
~
~
~
~
~
~
A10
~
~
~
~
~
~
~
~
A9
~
~
~
~
~
~
~
~
WE
DSF
Hi-Z
~
~
~
~
DQ
~
~
~
~
~
~
~
~
DQM
Hi-Z
Self Refresh Exit
Self Refresh Entry
Auto Refresh
: Don't care
* Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.
If the system uses burst refresh.
PRELIMINARY
(October, 2001, Version 0.1)
46
AMIC Technology, Inc.
A45L9332A Series
Mode Register Set Cycle
0
1
2
3
Auto Refresh Cycle
4
5
6
0
1
2
3
4
5
6
7
8
9
10
High
CKE
~
~
~
~
CLOCK
High
~
~
*Note 2
tRC
~
~
CS
~
~
~
~
RAS
~
~
* Note 1
~
~
CAS
~
~
* Note 3
Ra
~
~
Key
ADDR
~
~
~
~
WE
~
~
~
~
DSF
~
~
DQ
Hi-Z
Hi-Z
~
~
~
~
DQM
Auto Refresh
MRS
New Command
New
Command
: Don't care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
* Note : 1. CS , RAS , CAS &
mode register.
WE
activation and DSF of low at the same clock cycle with address key will set internal
2. Minimum 1 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
PRELIMINARY
(October, 2001, Version 0.1)
47
AMIC Technology, Inc.
A45L9332A Series
Function Truth Table (Table 1)
Current
State
IDLE
Row
Active
Read
PRELIMINARY
CS
RAS CAS
WE
DSF
BA
Address
(A10)
Action
Note
H
X
X
X
X
X
X
NOP
L
H
H
H
X
X
X
NOP
L
H
H
L
X
X
X
ILLEGAL
2
L
H
L
X
X
BA
CA
ILLEGAL
2
L
L
H
H
L
BA
RA
Row Active; Latch Row Address; Non-IO Mask
L
L
H
H
H
BA
RA
Row Active; latch Row Address; IO Mask
L
L
H
L
L
BA
PA
NOP
L
L
H
L
H
X
X
ILLEGAL
L
L
L
H
L
X
X
Auto Refresh or Self Refresh
L
L
L
H
H
X
L
L
L
L
L
OP Code
Mode Register Access
5
L
L
L
L
H
OP Code
Special Mode Register Access
6
H
X
X
X
X
X
X
NOP
L
H
H
H
X
X
X
NOP
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
L
H
L
L
L
BA
CA,AP
Begin Write; Latch CA; Determine AP
L
H
L
L
H
BA
CA,AP
Block Write; Latch CA; Determine AP
L
L
H
H
X
BA
RA
ILLEGAL
L
L
H
L
L
BA
PA
Precharge
L
L
H
L
H
X
X
ILLEGAL
L
L
L
H
X
X
X
ILLEGAL
L
L
L
L
L
X
X
ILLEGAL
X
5
ILLEGAL
2
Begin Read; Latch CA; Determine AP
ILLEGAL
2
L
L
L
L
H
H
X
X
X
X
X
X
NOP(Continue Burst to End →Row Active)
L
H
H
H
X
X
X
NOP(Continue Burst to End →Row Active)
L
H
H
L
L
X
X
Term burst →Row Active
L
H
H
L
H
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
L
H
L
L
L
BA
CA,AP
Term burst; Begin Write; Latch CA; Determine AP
3
L
H
L
L
H
BA
CA,AP
Term burst; Block Write; Latch CA; Determine AP
3
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
L
BA
PA
Term Burst; Precharge timing for Reads
3
L
L
H
L
H
X
X
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
(October, 2001, Version 0.1)
OP Code
4
48
Special Mode Register Access
Term burst; Begin Read; Latch CA; Determine AP
6
3
ILLEGAL
AMIC Technology, Inc.
A45L9332A Series
Function Truth Table (Table 1, Continued)
Current
State
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Precharge
PRELIMINARY
CS
RAS CAS
WE
DSF
BA
Address
(A10)
Action
Note
H
X
X
X
X
X
X
NOP(Continue Burst to End→Row Active)
L
H
H
H
X
X
X
NOP(Continue Burst to End→Row Active)
L
H
H
L
L
X
X
Term burst →Row Active)
L
H
H
L
H
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
L
H
L
L
L
BA
CA,AP
Term burst; Begin Write; Latch CA; Determine AP
3
L
H
L
L
H
BA
CA,AP
Term burst; Block Write; Latch CA; Determine AP
3
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
L
BA
PA
Term Burst; Precharge timing for Writes
3
L
L
H
L
H
X
X
ILLEGAL
ILLEGAL
Term burst; Begin Read; Latch CA; Determine AP
3
ILLEGAL
L
L
L
X
X
X
X
H
X
X
X
X
X
X
NOP(Continue Burst to End→Precharge)
L
H
H
H
X
X
X
NOP(Continue Burst to End→Precharge)
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
X
BA
CA,AP
ILLEGAL
2
L
H
L
L
X
BA
CA,AP
ILLEGAL
2
L
L
H
X
X
BA
RA,PA
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP(Continue Burst to End→Precharge)
L
H
H
H
X
X
X
NOP(Continue Burst to End→Precharge)
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
X
BA
CA,AP
ILLEGAL
2
L
H
L
L
X
BA
CA,AP
ILLEGAL
2
2
L
L
H
X
X
BA
RA,PA
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP→Idle after tRP
L
H
H
H
X
X
X
NOP→Idle after tRP
L
H
H
L
X
X
X
ILLEGAL
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
NOP→Idle after tRP
2
L
L
L
X
X
X
X
ILLEGAL
4
(October, 2001, Version 0.1)
49
2
AMIC Technology, Inc.
A45L9332A Series
Function Truth Table (Table 1, Continued)
Current
State
Block
Write
Recovering
Row
Activating
Refreshing
CS
RAS CAS
WE
DSF
BA
Address
(A10)
Action
Note
H
X
X
X
X
X
X
NOP→Row Active after tBWC
L
H
H
H
X
X
X
NOP→Row Active after tBWC
L
H
H
L
X
X
X
ILLEGAL
L
H
L
X
X
BA
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
Term Block Write: Precharge timing for Block
Write
2
L
L
L
X
X
X
X
ILLEGAL
2
H
X
X
X
X
X
X
NOP→Row Active after tRCD
L
H
H
H
X
X
X
NOP→Row Active after tRCD
L
H
H
L
X
X
X
ILLEGAL
L
H
L
X
X
BA
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
ILLEGAL
2
L
L
L
X
X
X
X
ILLEGAL
2
CA,AP ILLEGAL
CA,AP ILLEGAL
H
X
X
X
X
X
X
NOP→Idle after tRC
L
H
H
X
X
X
X
NOP→Idle after tRC
L
H
L
X
X
X
X
ILLEGAL
L
L
H
X
X
X
X
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
Abbreviations
RA = Row Address (A0~A9)
NOP = No Operation Command
2
BA = Bank Address (A10)
CA = Column Address (A0~A7)
2
PA = Precharge All (A9)
AP = Auto Precharge (A9)
Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state : Function may be legal in the bank indicated by BA, depending on the state of that
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).
5. Illegal if any banks is not idle.
6. Legal only if all banks are in idle or row active state.
PRELIMINARY
(October, 2001, Version 0.1)
50
AMIC Technology, Inc.
A45L9332A Series
Function Truth Table for CKE (Table 2)
Current
State
Self
Refresh
CKE
n-1
H
CKE
n
X
X
X
L
H
H
X
L
H
L
L
H
L
L
CS
RAS CAS
WE
DSF
Address
Action
Note
X
X
X
X
INVALID
X
X
X
X
Exit Self Refresh→ABI after tRC
7
H
H
H
X
X
Exit Self Refresh→ABI after tRC
7
L
H
H
L
X
X
ILLEGAL
H
L
H
L
X
X
X
ILLEGAL
H
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP(Maintain Self Refresh)
H
X
X
X
X
X
X
X
INVALID
Both
L
H
H
X
X
X
X
X
Exit Power Down→ABI
8
8
Bank
L
H
L
H
H
H
X
X
Exit Power Down→ABI
Precharge
L
H
L
H
H
L
X
X
ILLEGAL
Power
L
H
L
H
L
X
X
X
ILLEGAL
Down
L
H
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP(Maintain Power Down Mode)
H
H
X
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
X
Enter Power Down
9
H
L
L
H
H
H
X
X
Enter Power Down
9
H
L
L
H
H
L
X
X
ILLEGAL
H
L
L
H
L
X
X
X
ILLEGAL
H
L
L
L
H
X
X
X
ILLEGAL
H
L
L
L
L
H
L
X
Enter Self Refresh
H
L
L
L
L
L
X
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP
All
Banks
Idle
9
Any State
H
H
X
X
X
X
X
X
Refer to Operations in Table 1
Other than
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
10
Listed
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
10
Above
L
L
X
X
X
X
X
X
Maintain clock Suspend
Abbreviations : ABI = All Banks Idle
Note: 7. After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low
to high transition to issue a new command.
8. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time “tSS + one clock” must be satisfied before any command other than exit.
9. Power-down and self refresh can be entered only from the all banks idle state.
10. Must be a legal command.
PRELIMINARY
(October, 2001, Version 0.1)
51
AMIC Technology, Inc.
A45L9332A Series
Ordering Information
Part No.
Cycle Time (ns)
A45L9332AF-6
6
A45L9332AE-6
Clock Frequency (MHz)
Access Time
Package
166
5.5 ns @ CL = 3
100 QFP
6
166
5.5 ns @ CL = 3
100 LQFP
A45L9332AF-7
7
143
6.0 ns @ CL = 3
100 QFP
A45L9332AE-7
7
143
6.0 ns @ CL = 3
100 LQFP
A45L9332AF-8
8
125
6.5 ns @ CL = 3
100 QFP
A45L9332AE-8
8
125
6.5 ns @ CL = 3
100 LQFP
* QFP (Height = 3.0mm Max)
LQFP (Height = 1.4mm Max)
PRELIMINARY
(October, 2001, Version 0.1)
52
AMIC Technology, Inc.
A45L9332A Series
Package Information
QFP 100L Outline Dimensions
unit: inches/mm
HE
A2
A1
D
E
80
51
50
100
31
1
L1
L
HD
D
81
y
30
e
b
c
θ
Symbol
Dimensions in inches
Dimensions in mm
Min.
Nom.
Max.
Min.
Nom.
Max.
0.004
-
-
0.100
-
-
A2
0.107
0.112
0.117
2.723
2.85
2.977
b
0.010
-
0.014
0.26
-
0.36
A1
c
0.0057
0.006
0.0063
0.142
0.150
0.158
HE
0.905
0.913
0.921
22.950
23.200
23.450
E
0.783
0.787
0.791
19.900
20.000
20.100
HD
0.669
0.677
0.685
16.950
17.200
17.450
D
0.547
0.551
0.555
13.900
14.000
14.100
e
0.020
0.026
0.032
0.500
0.650
0.800
L
0.025
0.031
0.037
0.650
0.800
0.950
L1
0.057
0.063
0.069
1.450
1.600
1.750
y
-
-
0.004
-
-
0.100
0°
-
0°
-
8°
θ
8°
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
PRELIMINARY
(October, 2001, Version 0.1)
53
AMIC Technology, Inc.
A45L9332A Series
Package Information
LQFP 100L Outline Dimensions
unit: inches/mm
HE
A2
A1
D
E
80
51
50
100
31
1
L1
L
HD
D
81
y
30
e
b
c
θ
Symbol
Dimensions in inches
Dimensions in mm
Min.
Nom.
Max.
Min.
Nom.
Max.
A1
0.002
-
-
0.05
-
-
A2
0.053
0.055
0.057
1.35
1.40
1.45
b
0.011
0.013
0.015
0.27
0.32
0.37
c
0.005
-
0.008
0.12
-
0.20
HE
0.860
0.866
0.872
21.85
22.00
22.15
E
0.783
0.787
0.791
19.90
20.00
20.10
HD
0.624
0.630
0.636
15.85
16.00
16.15
D
0.547
0.551
0.555
13.90
14.00
14.10
e
L
0.026 BSC
0.018
L1
0.024
0.65 BSC
0.030
0.45
0.039 REF
0.60
0.75
1.00 REF
y
-
-
0.004
-
-
0.1
θ
0°
3.5°
7°
0°
3.5°
7°
Notes:
1. Dimensions D and E do not include mold protrusion.
2. Dimensions b does not include dambar protrusion.
Total in excess of the b dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
PRELIMINARY
(October, 2001, Version 0.1)
54
AMIC Technology, Inc.