Ultra Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable BSI BS616UV8021 DESCRIPTION FEATURES • Ultra low operation voltage : 1.8 ~ 2.3V • Ultra low power consumption : Vcc = 2.0V C-grade: 20mA (Max.) operating current I-grade : 25mA (Max.) operating current 0.6uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc=2.0V -10 100ns (Max.) at Vcc=2.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE1, CE2 and OE options • I/O Configuration x8/x16 selectable by CIO, LB and UB pin The BS616UV8021 is a high performance, ultra low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits or 1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide range of 1.8V to 2.3V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.6uA and maximum access time of 70/100ns in 2.0V operation. Easy memory expansion is provided by an active HIGH chip enable2(CE2), active LOW chip enable1(CE1), active LOW output enable(OE) and three-state output drivers. The BS616UV8021 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616UV8021 is available in DICE form and 48-pin BGA type. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE BS616UV8021DC BS616UV8021BC BS616UV8021FC BS616UV8021DI BS616UV8021BI BS616UV8021FI Vcc RANGE 70 / 100 15uA 20mA O O 1.8V ~ 2.3V 70 / 100 20uA 25mA -40 C to +85 C 3 4 5 6 LB OE A0 A1 A2 CE2 D8 UB A3 A4 CE1 D0 C D9 D10 A5 A6 D1 D2 E VCC D12 A17 Vss A7 A16 D14 D3 D4 A12 Address A11 A10 Input A9 A8 A17 A7 A6 Buffer 16(8) D0 . . . . VSS D5 D6 A14 A15 A13 WE D7 A10 A11 SAE. G D15 CIO . H A18 A8 A9 22 2048 Row Memory Array Decoder 2048 x 4096 4096 VCC D13 A12 DICE BGA-48-0810 BGA-48-0912 DICE BGA-48-0810 BGA-48-0912 A15 A14 A13 . . . . OE UB LB CIO 16(8) Buffer Column I/O Write Driver 16(8) Data Output CE1 CE2 WE Data Input Buffer 16(8) D15 F PKG TYPE BLOCK DIAGRAM 2 D11 Vcc=2.0V 1.8V ~ 2.3V 1 VSS (ICC, Max) Vcc=2.0V O B D (ICCSB1, Max) Vcc=2.0V O +0 C to +70 C PIN CONFIGURATIONS A POWER DISSIPATION STANDBY Operating SPEED (ns) Sense Amp 256(512) Column Decoder 16(18) Control Address Input Buffer A16 A0 A1 A2 A3 A4 A5 A18 (SAE) Vdd Vss 48-Ball CSP top View Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. R0201-BS616UV8021 1 Revision 2.2 April 2001 Preliminary BSI BS616UV8021 PIN DESCRIPTIONS Name Function A0-A18 Address Input These 19 address inputs select one of the 524,288 x 16-bit words in the RAM. SAE Address Input This address input incorporate with the above 19 address inputs select one of the 1,048,576 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH. CIO x8/x16 select input This input selects the organization of the SRAM. 524,288 x 16-bit words configuration is selected if CIO is HIGH. 1,048,576 x 8-bit bytes configuration is selected if CIO is LOW. CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. The chip is deselected when both LB and UB pins are HIGH. D0 - D15 Data Input/Output Ports These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground R0201-BS616UV8021 2 Revision 2.2 April 2001 BSI BS616UV8021 TRUTH TABLE MODE CE1 CE2 H X Fully Standby Output Disable Read from SRAM X L L H L H OE WE CIO X X X H L H X H H ( WORD mode ) Write to SRAM L H X L H ( WORD mode ) Read from SRAM LB UB SAE D0~7 D8~15 X X X X X X L H H L X High- Z High- Z X High-Z High- Z Dout High- Z High-Z Dout L L Dout Dout L H Din X H L X Din L L Din Din X X VCC Current ICCSB, ICCSB1 ICC ICC ICC L H L H L X X A-1 Dout High-Z L H X L L X X A-1 Din X ICC ( BYTE Mode ) Write to SRAM ( BYTE Mode ) ABSOLUTE MAXIMUM RATINGS(1) SYMBOL V TERM PARAMETER Terminal Voltage Respect to GND with ICC OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V AMBIENT TEMPERATURE RANGE O O Vcc T BIAS Temperature Under Bias -40 to +125 O C Commercial 0 C to +70 C 1.8V ~ 2.3V T STG Storage Temperature -60 to +150 O C Industrial -40 O C to +85 O C 1.8V ~ 2.3V PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. R0201-BS616UV8021 3 CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. Revision 2.2 April 2001 BSI BS616UV8021 DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC) PARAMETER NAME VIL VIH PARAMETER TEST CONDITIONS Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) MIN. TYP.(1) MAX. UNITS Vcc=2.0V -0.5 -- 0.6 V Vcc=2.0V 1.4 -- Vcc+0.2 V IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA I OL Output Leakage Current Vcc = Max, CE1 = VIH, or CE2 = ViL, or OE = VIH, VI/O = 0V to Vcc -- -- 1 uA VOL Output Low Voltage Vcc= max, IOL= 1mA Vcc=2.0V -- -- 0.4 V VOH Output High Voltage Vcc= Min, IOH= -0.5mA Vcc=2.0V 1.6 -- -- V ICC Operating Power Supply Vcc= max, CE1=V IL and CE2 = VIH, Current IDQ = 0mA, F =Fmax (3) Vcc=2.0V -- -- 20 mA ICCSB Standby Current-TTL Vcc= max, CE1 = VIH or CE2 = VIL, IDQ = 0mA Vcc=2.0V -- -- 0.6 mA I CCSB1 Standby CurrentC - MOS Vcc= max,CE1ЊVcc-0.2V, or CE2Љ0.2V;VINЊ Vcc - 0.2V or VIN Љ 0.2V Vcc=2.0V -- 0.6 15 uA 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/ tRC . R0201-BS616UV8021 4 Revision 2.2 April 2001 BSI BS616UV8021 DATA RETENTION CHARACTERISTICS ( TA = 0oC to +70oC ) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS VDR Vcc for Data Retention CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V ; VIN Њ Vcc - 0.2V or VIN Љ 0.2V 1.5 -- -- V ICCDR Data Retention Current CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V VIN Њ Vcc - 0.2V or VIN Љ 0.2V -- 0.4 10 uA tCDR Chip Deselect to Data Retention Time 0 -- -- ns TRC (2) -- -- ns See Retention Waveform tR Operation Recovery Time 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode Vcc VDR Њ 1.5V Vcc CE1 Vcc tR t CDR CE1 Њ Vcc - 0.2V VIH LOW VCC DATA RETENTION WAVEFORM (2) VIH ( CE2 Controlled ) Data Retention Mode Vcc VDR Њ 1.5V Vcc CE2 R0201-BS616UV8021 VIL Vcc tR t CDR CE2 Љ 0.2V 5 VIL Revision 2.2 April 2001 BSI BS616UV8021 AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level KEY TO SWITCHING WAVEFORMS Vcc/0V 5ns WAVEFORM INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L 1333 MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H 5PF DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE 0.5Vcc AC TEST LOADS AND WAVEFORMS 1333 2V 2V OUTPUT OUTPUT , 100PF INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE 2000 Ω 2000 Ω FIGURE 1A FIGURE 1B THEVENIN EQUIVALENT 800 Ω OUTPUT 1.2V ALL INPUT PULSES Vcc GND 90% 90% 10% → ← → 10% ← 5ns FIGURE 2 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to +70oC, Vcc=2.0V ) READ CYCLE JEDEC PARAMETER NAME tAVAX tAVQV tE1LQV tE2LQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tAXQX R0201-BS616UV8021 PARAMETER NAME tRC tAA tACS1 tACS2 tBA tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH DESCRIPTION BS616UV8021-70 BS616UV8021-10 MIN. TYP. MAX. MIN. TYP. MAX. 70 Read Cycle Time 70 100 ns ns (CE1) (CE2) 70 100 ns 70 100 ns (LB,UB) 50 60 ns 50 60 ns Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time 100 UNIT Output Enable to Output Valid Chip Select to Output Low Z (CE2,CE1) Data Byte Control to Output Low Z (LB,UB) Output Enable to Output in Low Z 10 15 ns 10 15 ns 10 15 Chip Deselect to Output in High Z (CE2,CE1) Data Byte Control to Output High Z (LB,UB) Output Disable to Output in High Z 0 35 0 40 ns 0 30 0 35 ns 0 30 0 35 ns Output Disable to Output Address Change 6 10 15 ns ns Revision 2.2 April 2001 BSI BS616UV8021 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t AA t OH t OH D OUT READ CYCLE2 (1,3,4) CE2 t ACS2 t ACS1 CE1 t t CHZ(5) (5) CLZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t CE2 t t CE1 t t t OE OH ACS2 OLZ t ACS1 (5) CLZ OHZ (5) (1,5) t CHZ t BDO LB,UB t BE t BA D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. R0201-BS616UV8021 7 Revision 2.2 April 2001 BSI BS616UV8021 AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to +70oC, Vcc=2.0V) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tBW tWLQZ tDVWH tWHDX tGHQZ tWHQX tWC tCW tAS tAW tWP tWR tBW tWHZ tDW tDH tOHZ tOW BS616UV8021-10 BS616UV8021-70 DESCRIPTION MIN. TYP. MIN. MAX. TYP. UNIT MAX. Write Cycle Time 70 100 Chip Select to End of Write 70 100 ns ns 0 0 ns Address Valid to End of Write 70 100 ns Write Pulse Width 50 70 ns (CE2, CE1, WE) 0 0 ns Data Byte Control to End of Write (LB,UB) 60 80 Address Set up Time Write Recovery Time 0 Write to Output in High Z 0 30 30 40 Data Hold from Write Time Output Disable to Output in High Z 0 0 End of Write to Output Active 5 Data to Write Time Overlap 0 0 30 10 ns 40 ns ns ns 40 ns ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS (3) t WR OE CE2 (5) (11) t CW (5) CE1 t BW (5) LB,UB t AW WE (3) t WP t AS (2) (4,10) t OHZ D OUT t DH t DW D IN R0201-BS616UV8021 8 Revision 2.2 April 2001 BSI BS616UV8021 WRITE CYCLE2 (1,6) t WC ADDRESS CE2 (11) t (5) CE1 t BW (5) LB,UB t WE CW AW t WR t WP (3) (2) t t AS DH (4,10) t WHZ D OUT (7) (8) t DW t DH (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured± 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write. R0201-BS616UV8021 9 Revision 2.2 April 2001 BSI BS616UV8021 ORDERING INFORMATION BS616UV8021 X X -- Y Y SPEED 70: 70ns 10: 100ns GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE B :BGA - 48 PIN(8x10mm) F :BGA - 48 PIN(9x12mm) D :DICE 1.4 Max. 0.25 ̈́ 0.05 PACKAGE DIMENSIONS NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. SIDE VIEW D 0.1 D1 N D E D1 E1 e 48 10.0 8.0 5.25 3.75 0.75 0.35̈́ 0.05 E 0.1 E1 e SOLDER BALL VIEW A 48 mini-BGA (8 x 10mm) R0201-BS616UV8021 10 Revision 2.2 April 2001 BSI BS616UV8021 1.4 Max. 0.25̈́ 0.05 PACKAGE DIMENSIONS (continued) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. SIDE VIEW D 0.1 3.375 D1 N D E D1 E1 e 48 12.0 9.0 5.25 3.75 0.75 E1 2.625 E ̈́ 0.1 e SOLDER BALL 0.35̈́0.05 VIEW A 48 mini-BGA (9 x 12mm) R0201-BS616UV8021 11 Revision 2.2 April 2001 BSI BS616UV8021 REVISION HISTORY Revision Description Date 2.2 2001 Data Sheet release Apr. 15, 2001 R0201-BS616UV8021 12 Note Revision 2.2 April 2001