TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 TWO-PHASE, SYNCHRONOUS BUCK CONTROLLER WITH INTEGRATED MOSFET DRIVERS FEATURES • • • • • • • • • • • • • Two-Phase Interleaved Operation 3-V to 40-V Power Stage Operation Range Supports Up to 6-V VOUT With External Divider Requires VIN5 @ 50 mA, Typical, Depending on External MOSFETs and Switching Frequency 1-µA Shutdown Current Programmable Switching Frequency up to 1 MHz/Phase Current Mode Control with Forced Current Sharing Better than 1% Internal 0.7-V Reference Resistive Divider Sets Direct Output Over Voltage Threshold and Sets Input Undervoltage Lockout True Remote Sensing Differential Amplifier Resistive or Inductor’s DCR Current Sensing 30-pin TSSOP Package Can Be Used with TPS40120 to Provide a 6-Bit Digitally Controlled Output APPLICATIONS • • • • • Graphic Cards Internet Servers Networking Equipment Telecommunications Equipment DC Power Distributed Systems DBT PACKAGE (TOP VIEW) LDRV1 VIN5 SW1 HDRV1 BOOT1 OVSET VOUT GSNS DIFFO CS1 CSRT1 COMP VREF DROOP FB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PGND LDRV2 SW2 HDRV2 BOOT2 SS UVLO BP5 AGND CS2 CSRT2 RT PGOOD ILIM EN/SYNC DESCRIPTION The TPS40130 is a two-phase synchronous buck controller that is optimized for low-output voltage, high-output current applications powered from a supply between 3 V and 40 V. A multi-phase converter offers several advantages over a single power stage including lower current ripple on the input and output capacitors, faster transient response to load steps, improved power handling capabilities, and higher system efficiency. Each phase can be operated at a switching frequency up to 1 MHz, resulting in an effective ripple frequency of up to 2 MHz at the input and the output. The two phases operates 180 degrees out-of-phase. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SIMPLIFIED APPLICATION DIAGRAM VOUT VIN VIN 5V TPS40130DBT DIFFO 1 LDRV1 PGND 30 2 VIN5 LDRV2 29 3 SW1 SW2 28 4 HDRV1 HDRV2 27 VIN 5 BOOT1 BOOT2 26 6 OVSET VOUT SS 25 7 VOUT UVLO 24 LOAD BP5 23 5V 8 GSNS 9 DIFFO AGND 22 10 CS1 CS2 21 11 CSRT1 CSRT2 20 12 COMP RT 19 13 VREF PGOOD 18 14 DROOP 15 FB VREF ILIM 17 EN/SYNC 16 5V UDG−04017 ORDERING INFORMATION TA -40°C to 85°C (1) 2 PACKAGE Plastic TSSOP(DBT) (1) PART NUMBER TPS40130DBT The DBTpackage is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40130DBTR). TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 ABSOLUTE MAXIMUM RATING over operating free-air temperature range unless otherwise noted (1) TPS40130 SW1, SW2 Input voltage range BOOT1, BOOT2 Sourcing current RT UNITS -1 to 44 -0.3 to VSW + 6.0 All other pins V -0.3 to 6.0 200 µA TJ Operating junction temperature range -40 to 125 °C Tstg Storage temperature -55 to 150 °C 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VIN Input voltage 3.0 40 V TA Operating free-air temperature -40 85 °C 3 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS TA = -40°C to 85°C, VIN = 12 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.5 5.0 5.5 V 1 5 µA 0.5 1.0 1.5 mA 4.3 5.0 5.5 2 3 5 4.00 4.25 4.45 VIN5 INPUT SUPPLY VIN Operating voltage range, VIN5 IIN Shutdown current, VIN5 EN/SYNC = GND Operating current Outputs switching, No load BP5 INPUT SUPPLY Operating voltage range IBP5 Operating current VFB < VREF, Outputs switching, no external FETs Turn-on BP5 rising Turn-off hysteresis (1) 150 V mA V mV OSCILLATOR/SYNCHRONIZATION Phase frequency accuracy RT = 64.9 kΩ 360 415 455 Phase frequency set range (1) 100 1200 Synchronization frequency range (1) 800 9600 Synchronization input threshold (1) VBP5/2 kHz V EN/SYNC Enable threshold Pulse width > 50 ns 0.8 Voltage capability (1) 1.0 1.5 VBP5 V PWM Maximum duty cycle per channel (1) 87.5% Minimum duty cycle per channel (1) 0 VREF Voltage reference ILOAD = 100 µA 0.687 0.700 0.709 0.691 0.700 0.705 0.0 0.7 2.0 55 150 V ERROR AMPLIFIER Voltage feedback, trimmed (including differential amplifier) VFB CMRR Input common mode range (1) Input bias current VFB = 0.7 V nA Input offset voltage Value trimmed to zero ISRC Output source current (1) VCOMP = 1.1 V, VFB = 0.6 V 1 2 ISINK Output sink current (1) VCOMP = 1.1 V, VFB =VBP5 1 2 VOH High-level output voltage ICOMP = -1 mA 2.5 2.9 VOL low-level output voltage ICOMP = 1 mA GBW Gain bandwidth (1) 3 5 MHz AVOL Open loop gain (1) 60 90 dB (1) 4 Ensured by design. Not production tested. 0 V 0.5 V mA 0.8 V TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS (continued) TA = -40°C to 85°C, VIN = 12 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.5 5.0 6.5 µA 0.95 1.00 1.05 V SOFT START ISS Soft-start source current VSS Fault enable threshold voltage 32 clocks after EN/SYNC before SS current begins CURRENT SENSE AMPLIFIER Input offset voltage CS1, CS2 Gain transfer to PWM comparator -100 mV ≤ VCS≤ 100 mV, VCSRT = 1.5 V Transconductance to DROOP VCS - VCSRTn = 100 mV Gain variance between phases VCS - VCSRTn = 100 mV -4% 0 4% Input offset variance VCS = 0 V -3.5 0 3.5 mV Offset current at DROOP VCS - VCSRTn = 0 V 6 µA Input common mode (2) -5 4 10 mV 5.1 5.6 6.1 V/V 40 0 Bandwidth (2) µA VBP5-0.7 18 V MHz DIFFERENTIAL AMPLIFIER Gain 1 Gain tolerance CMRR VOUT = 4 V vs VOUT = 0.7 V, VGSNS = 0 V -0.5% Common mode rejection ratio (2) 0.7 V≤ VOUT ≤ 4.0 V Output source current VOUT - VGSNS = 2.0 V, VDIFFO≥ 1.98 V 2 4 Output sink current VOUT - VGSNS = 2.0 V, VDIFFO≥ 2.02 V 2 4 Input offset voltage (2) 0.7 V≤ VOUT ≤ 4.0 V Bandwidth (2) V/V 0.5% 60 dB mA 5 5 mV MHz Input impedance, non-inverting (2) VOUT to GND 40 Input impedance, inverting (2) VGSNS to VDIFFO 40 kΩ GATE DRIVERS Source on-resistance, HDRV1, HDRV2 VBOOT1 = 5 V, VBOOT2 = 5 V, VSW1 = 0 V, VSW2 = 0 V, Sourcing 100 mA 1.0 2.0 3.5 Sink on-resistance, HDRV1, HDRV2 VBOOT1 = 5 V, VBOOT2 = 5 V, VVIN5 = 5 V, VSW1 = 0 V, VSW2 = 0 V, Sinking 100 mA 0.5 1.0 2.0 Source on-resistance, LDRV1, LDRV2 VVIN5 = 5 V, VSW1 = 0 V, VSW2 = 0 V, Sourcing 100 mA 1 2 3.5 Sink on-resistance, LDRV1, LDRV2 VVIN5 = 5 V, VSW1 = 0 V, VSW2 = 0 V, Sinking 100 mA 0.30 0.75 1.50 tRISE Rise time, HDRV (2) CLOAD = 3.3 nF 25 75 tFALL Fall time, HDRV (2) CLOAD = 3.3 nF 25 75 tRISE Rise time, LDRV (2) CLOAD = 3.3 nF 25 75 CLOAD = 3.3 nF 25 60 ns SW falling to LDRV rising 50 LDRV falling to SW rising 30 mV tFALL tDEAD tON Fall time, LDRV (2) Dead time (2) Minimum controllable on-time (2) Ω Ω CLOAD = 3.3 nF 150 OUTPUT UNDERVOLTAGE FAULT Undervoltage fault threshold VFB relative to GND VFB relative to VVREF 560 588 610 -20% -16% -13% OUTPUT OVERVOLTAGE SET Overvoltage threshold (2) VOVSET relative to GND 796 817 832 VOVSET relative to VVREF 14% 16% 19% mV Ensured by design. Not production tested. 5 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS (continued) TA = -40°C to 85°C, VIN = 12 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.4 0.5 0.6 UNIT RAMP Ramp amplitude Ramp (3) valley (3) 1.4 V POWER GOOD VOL ILEAK PGOOD high threshold VFB relative to VREF 10% 14% PGOOD low threshold VFB relative to VREF -14% -10% Low-level output voltage IPGOOD = 4 mA PGOOD bias current VPGOOD = 5.0 V Current sense fault (3) Current from CS1, CS2 0.35 0.60 50 80 5 V µA INPUT UVLO PROGRAMMABLE Input threshold voltage, turn-on 0.9 Input threshold voltage, turn-off 1.0 1.1 0.810 V LOAD LINE PROGRAMMING IDROOP (3) 6 Pull-down current Ensured by design. Not production tested. VCS = 100 mV 30 40 50 µA TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 DBT PACKAGE (TOP VIEW) LDRV1 VIN5 SW1 HDRV1 BOOT1 OVSET VOUT GSNS DIFFO CS1 CSRT1 COMP VREF DROOP FB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PGND LDRV2 SW2 HDRV2 BOOT2 SS UVLO BP5 AGND CS2 CSRT2 RT PGOOD ILIM EN/SYNC Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AGND 22 - Low noise ground connection to the device. BOOT1 5 I Provides a bootstrapped supply for the high-side FET driver for PWM1, enabling the gate of the high-side FET to be driven above the input supply rail. Connect a capacitor from this pin to SW1 pin and a Schottky diode from this pin to VIN5. BOOT2 26 I Provides a bootstrapped supply for the high-side FET driver for PWM2, enabling the gate of the high-side FET to be driven above the input supply rail. Connect a capacitor from this pin to SW2 pin and a Schottky diode from this pin to VIN5. BP5 23 O Filtered input from the VIN5 pin. A 10-Ω resistor should be connected between VIN5 and BP5 and a 1.0-µF ceramic capacitor should be connected from this pin to ground. COMP 12 O Output of the error amplifier. The voltage at this pin determines the duty cycle for the PWM. CS1 10 I CS2 21 I These pins are used to sense the inductor phase current. Inductor current can be sensed with an external current sense resistor or by using an external R-C circuit and the inductor's DC resistance. The traces for these signals must be connected directly at the current sense element. See Layout Guidelines for more information. After the device is enabled and prior to the device starting (during the first 32 clock cycles), a 5-µA current flows out of these pins. The current flows through the external components: current sense resistor, RCS, the output inductor and the output capacitor(s) to ground. If the voltage on the CS1, and CS2 pins exceed 0.2 V (resistance greater than 40 kΩ), a fault is declared and the device does not start. This is a fault detection feature that insures the output inductor, current sense resistor and output capacitors are installed properly on the board. CSRT1 11 O CSRT2 20 O DIFFO 9 O Output of the differential amplifier. The voltage at this pin represents the true output voltage without IR drops that result from high-current in the PCB traces. The VOUT and GSNS pins must be connected directly at the point of load where regulation is required. See Layout Guidelines for more information. DROOP 14 I This is the input to the non-inverting input of the Error Amplifier. This pin is normally connected to the VREF pin and is the voltage that the feedback loop regulates to. This pin is also used to program droop function. A resistor between this pin and the VREF pin sets the desired droop value. The value of the DROOP resistor is described in Equation 20. EN/SYNC 16 I A logic high signal on this input enables the controller operation. A pulsing signal to this pin synchronizes the rising edge of SW to the falling edge of an external clock source. These pulses must be greater than 8.2 times the free running frequency of the main oscillator set by the RT resistor. FB 15 I Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is the internal reference level of 700 mV. This pin is also used for the PGOOD and undervoltage comparators. GSNS 8 I Inverting input of the differential amplifier. This pin should be connected to ground at the point of load. HDRV1 4 O Gate drive output for the high-side N-channel MOSFET switch for PWM1. Output is referenced to SW1 and is bootstrapped for enhancement of the high-side switch. Return point of current sense voltage. The traces for these signals must be connected directly at the current sense element. See Layout Guidelines for more information. 7 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 Terminal Functions (continued) TERMINAL NAME HDRV2 NO. 27 I/O DESCRIPTION O Gate drive output for the high-side N-channel MOSFET switch for PWM2. Output is referenced to SW2 and is bootstrapped for enhancement of the high-side switch ILIM 17 I Used to set the cycle-by-cycle current limit threshold. If ILIM threshold is reached, the PWM cycle is terminated and the converter delivers limited current to the output. Under these conditions the undervoltage threshold eventually is reached and the controller enters the hiccup mode. The controller stays in the hiccup mode for seven (7) consecutive cycles of SS voltage rising from zero to 1.0 V. At the eighth cycle the controller attempts a full start-up sequence. The relationship between ILIM and the maximum phase current is described in Equation 2 and Equation 3. See the Overcurrent Protection section for more details. LDRV1 1 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for PWM1. See Layout Considerations section. LDRV2 29 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for PWM2. See Layout Considerations section. OVSET 6 I A resistor divider, on this pin connected to the output voltage sets the overvoltage sense point. PGOOD 18 O Power good indicator of the output voltage. This open-drain output connects to a voltage via an external resistor. When the FB pin voltage is between 0.616 V to 0.784 V (88% to 112% of VREF), the PGOOD output is in a high impedance state. If the DROOP function is implemented, the programmed droop voltage must be within this window. PGND 30 - Power ground reference for the controller lower gate drivers. There should be a high-current return path from the sources of the lower MOSFETs to this pin. RT 19 I Connecting a resistor from this pin to ground sets the oscillator frequency. SS 25 I Provides user programmable soft-start by means of a capacitor connected to the pin. If an undervoltage fault is detected the soft-start capacitor cycles 7 times with no switching before a normal soft-start sequence allowed. SW1 3 I Connect to the switched node on converter 1. Power return for the channel 1 upper gate driver. There should be a high-current return path from the source of the upper MOSFET to this pin. It is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. SW2 28 I Connect to the switched node on converter 2. Power return for the channel 2 upper gate driver. There should be a high-current return path from the source of the upper MOSFET to this pin. It is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. UVLO 24 O A voltage divider from VIN to this pin, set to 1V, determines the input voltage that starts the controller. VOUT 7 O Non-inverting input of the differential amplifier. This pin should be connected to VOUT at the point of load. VREF 13 O Output of an internal reference voltage. The load may be up to 100 µA DC. VIN5 2 I Power input for the device. A 1.0-µF ceramic capacitor should be connected from this pin to ground. 8 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 FUNCTIONAL BLOCK DIAGRAM BP5 23 AGND 22 CS1 10 CSRT1 11 VOUT 7 TPS40130 U1 + 20 kΩ 20 kΩ GSNS 8 + U7 20 kΩ U6 5 BOOT1 4 HDRV1 3 SW1 2 VIN5 1 LDRV1 30 PGND 26 BOOT2 27 HDRV2 28 SW2 29 LDRV2 18 PGOOD 20 kΩ DIFFO 13 0.7 V + VREF 9 Ramp1 U2 U8 U11 DROOP 14 FB 15 SS 25 U12 U3 PWM1 + U9 ICTLR U10 + U4 PWM LOGIC U13 5 µA COMP 12 CS2 21 CSRT2 20 ILIM 17 U15 U18 + 24 EN/SYNC 16 RT 19 OVSET 6 + U17 Ramp2 U14 UV Power-On Reset FB UVLO U5 Anti Cross Conduction VIN5 BP5 U22 Power−On Reset U23 Clock U19 OC/UV Detect U24 Ramp Gen U20 SS PWM2 U16 Anti Cross Conduction VIN5 OV OC U21 Ramp1 Ramp2 U25 OV Detect UDG−04030 FUNCTIONAL DESCRIPTION The TPS40130 uses programmable fixed-frequency, peak current mode control with forced phase current balancing. When compared to voltage-mode control, current mode results in a simplified feedback network and reduced input line sensitivity. Phase current is sensed by using either the DCR (direct current resistance) of the filter inductors or current sense resistors installed in series with output. The first method involves generation of a current signal with an R-C circuit (shown in the applications diagram). The R-C values are selected by matching time constants of the RC circuit and the inductor time constant, R×C = L/DCR. With either current sense method, the current signal is amplified and superimposed on the amplified voltage error signal to provide current mode PWM control. Output voltage droop can be programmed to improve the transient window and reduce size of the output filter. Other features include: a true differential output sense amplifier, programmable current limit, programmable output over-voltage set-point, capacitor set soft-start, power good indicator, programmable input undervoltage lockout (UVLO), user programmable operation frequency for design flexibility, external synchronization capability, programmable pulse-by-pulse overcurrent protection, output undervoltage shutdown and restart. Startup Sequence Figure 1 shows a typical start up with the VIN5 and BP5 applied to the controller and then the EN/SYNC being enabled. Shut down occurs when the VIN5 is removed 9 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 FUNCTIONAL DESCRIPTION (continued) VIN5 BP5 EN/SYNC 1.0V 0.7V SS SSWAIT VOUT PGOOD POR UDG−04031 Figure 1. Startup and Shutdown Sequence Differential Amplifier (U7) The unity gain differential amplifier with high bandwidth allows improved regulation at a user-defined point and eases layout constraints. The output voltage is sensed between the VOUT and GSNS pins. The output voltage programming divider is connected to the output of the amplifier (DIFFO). The differential amplifier input voltage must be lower than (VBP5 - 0.7 V). If there is no need for a differential amplifer, the differential amplifier can be disabled by connecting the GSNS pin to the BP5 pin and leaving VOUT and DIFFO open. The voltage programming divider in this case should be connected directly to the output of the converter. TPS40130 VOUT 20 kΩ 7 20 kΩ GSNS 20 kΩ Differential Amplifier + DIFFO 9 20 kΩ 8 UDG−04081 Figure 2. Differential Amplifier Configuration Because of the resistor configuration of the differential amplifier, the input impedance must be kept very low or there will be error in setting the output voltage. 10 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 FUNCTIONAL DESCRIPTION (continued) Current Sensing and Balancing (U1, U9 and U18) The controller employs peak current mode control scheme, thus naturally provides certain degree of current balancing. With current mode, the level of current feedback should comply with certain guidelines depending on duty factor known as “slope compensation” to avoid the sub-harmonic instability. This requirement can prohibit achieving a higher degree of phase current balance. To avoid the controversy, a separate current loop that forces phase currents to match is added to the proprietary control scheme. This effectively provides high degree of current sharing independent of the controller’s small signal response and is implemented in U9, ICTLR. High bandwidth current amplifiers, U1 and U18 can accept as an input voltage either the voltage drop across dedicated precise current sense resistors, or inductor’s DCR voltage derived by an RC network, or thermally compensated voltage derived from the inductor’s DCR. The wide range of current sense arrangements ease the cost/complexity constrains and provides superior performance compared to controllers utilizing the low-side MOSFET current sensing. The current sense amplifier inputs must not exceed 4 V. See the Inductor DCR Current Sense section for more information on selecting component values for the R-C network. PowerGood The PGOOD pin indicates when the inputs and output are within their specified ranges of operation. Also monitored are the EN/SYNC and SS pins. PGOOD has high impedance when indicating inputs and outputs are within specified limits and is pulled low to indicate an out-of-limits condition. Soft-Start A capacitor connected to the soft start pin (SS) sets the power-up time. When EN is high and POR is cleared, the calibrated current source, U13, starts charging the external soft start capacitor. The PGOOD pin is held low during the start up. The rising voltage across the capacitor serves as a reference for the error amplifier, U12. When the soft-start voltage reaches the level of the reference voltage, U8 (VVREF=0.7V), the converter’s output reaches the regulation point and further voltage rise of the soft start voltage has no effect on the output. When the soft start voltage reaches 1.0 V, the power good (PGOOD) function is cleared to be reported on the PGOOD pin. Normally the PGOOD pin goes high at this time. Equation 1 is used to calculate the value of the soft-start capacitor. 0.7 C SS t SS + 5 10 *6 (1) Overcurrent Protection The overcurrent function, U19, monitors the output of current sense amplifiers U1 and U18. These currents are converted to voltages and compared to the voltage on the ILIM pin. The relationship between the maximum phase current and the current sense resistance is given in the following equation. In case a threshold of VILIM/2.7 is exceeded the PWM cycle on the associated phase is terminated. The overcurrent threshold, IPH(max), and the voltage to set on the ILIM pin is determined by Equation 2 and Equation 3. V ILIM + 2.7 I PH(max) R CS I PH(max) + ǒV IN * VOUTǓ VOUT I OUT ) 2 2 L OUT f SW V IN (2) (3) where • • • IPH(max) is a maximum value of the phase current allowed IOUT is the total maximum DC output current RCS is a value of the current sense resistor used or the DCR value of the output inductor, LOUT If the overcurrent condition persists, both phases have PWM cycles terminated by the overcurrent signals. This puts a converter in a constant current mode with the output current programmed by the ILIM voltage. Eventually the supply-and-demand equilibrium on the converter output is not satisfied and the output voltage starts to decline. When the undervoltage threshold is reached, the converter enters a hiccup mode. The controller is stopped and the output is not regulated any more, the soft-start pin function changes. 11 TPS40130 SLUS602 – JUNE 2004 – REVISED AUGUST 2004 www.ti.com FUNCTIONAL DESCRIPTION (continued) It now serves as a hiccup timing capacitor controlled by U20, the fault control circuit. The soft-start pin is periodically charged and discharged by U20. After seven hiccup cycles, the controller attempts another soft-start cycle to restore normal operation. If the overload condition persists, the controller returns to the hiccup mode. This condition may continue indefinitely. In such conditions the average current delivered to the load is approximately 1/8 of the set overcurrent value. Current Sense Fault Protection Multiphase controllers with forced current sharing are inherently sensitive to a failure of the current sense component or a defect in the assembly process. In case of such failure the entire load current can be steered with catastrophic consequences into a single channel where the fault has occurred. A dedicated circuit in the TPS40130 controller detects this defect and prevents the controller from starting up. This fault detection circuit is active only during chip initialization and does not protect should current sense failure happen during normal operation. After the device is enabled and prior to the IC starting (during the first 32 clock cycles), a 5-µA current flows out of the CS1 and CS2 pins. The current flows through the external components: current sense resistor, RCS, the output inductor and the output capacitor(s) to ground. If the voltage on the CS1 and CS2 pins exceed 0.2 V (resistance greater than 40 kΩ), a fault is declared and the device does not start. This is a fault detection feature that insures the output inductor, current sense resistor and output capacitors are installed properly on the board. Overvoltage Protection The voltage on OVSET is compared with 0.817 V, 16% higher than VREF, in U25 to determine the output overvoltage point. When an overvoltage is detected, the output drivers command the upper MOSFETs off and the lower MOSFETs on. If the overvoltage is caused by a shorted upper MOSFET, latching on the lower MOSFET should blow the input fuse and protect the output. Hiccup mode consisting of seven (7) soft-start timing cycles is initiated and then attempts to restart. If the overvoltage condition has been cleared and the input fuse has not opened, the output comes up and normal operation continues. If the overvoltage condition persists, the controller restarts to allow the output to rise to the overvoltage level and return to the hiccup mode. Using a voltage divider with the same ratio, that sets the output voltage, an output overvoltage is declared when the output rises 16% above nominal. Output Undervoltage Protection If the output voltage, as sensed by U19 on the FB pin becomes less than 0.588 V, the undervoltage protection threshold (84% of VREF), the controller enters the hiccup mode as it is described in the Overcurrent Protection section. Programmable Input Undervoltage Lockout Protection A voltage divider that sets 1V on the UVLO pin determines when the controller starts operating. Operation commences when the voltage on the UVLO pin exceeds 1.0 V. Power-On Reset (POR) The power-on reset (POR) function, U22, insures the VIN5 and BP5 voltages are within their regulation windows before the controller is allowed to start. Fault Masking Operation If the SS pin voltage is externally limited below the 1-V threshold, the controller does not respond to most faults and the PGOOD output is always low. Only the overcurrent function and current sense fault remain active. The overcurrent protection still continues to terminate PWM cycle every time when the threshold is exceeded but the hiccup mode is not entered. Fault Conditions and MOSFET Control Table 1 shows a summary of the fault conditions and the state of the MOSFETs. 12 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 FUNCTIONAL DESCRIPTION (continued) Table 1. Fault Condifions FAULT MODE UPPER MOSFET EN/SYNC = LOW OFF LOWER MOSFET OFF FIXED UVLO, VBP5 < 4.25 V OFF OFF Programmable UVLO, < 1.0 V OFF ON Output undervoltage OFF, Hiccup mode ON, Hiccup mode Output overvoltage OFF, Hiccup mode ON, Hiccup mode ISF, current sense fault OFF ON Setting the Switching Frequency The clock frequency is programmed by the value of the timing resistor connected from the RT pin to ground. See Equation 4. R T + 0.8 ƪǒ 36 Ǔ ƫ 103 * 9 f PH (4) fPH is a single phase frequency, kHz. The RT resistor value is expressed in kΩ. See Figure 3. 500 RT − Timing Resistance − kΩ 450 400 350 300 250 200 150 100 50 0 0 200 400 600 800 1000 fSW − Phase Switching Frequency − kHz Figure 3. Phase Switching Frequency vs. Timing Resistance EN/SYNC Function The output ripple frequency is twice that of the single phase frequency. The switching frequency of the controller can be synchronized to an external clock applied to the EN/SYNC pin. The external clock synchronizes the rising edge of HDRV and the falling edge of an external clock source. The external clock pulses must be at a frequency at least 8.2 times higher than the switching frequency set by the RT resistor. 13 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 Setting Overcurrent Protection Setting the overcurrent protection is given in the following equations. Care must be taken when calculating VILIM to include the increase in RCS caused by the output current as it approaches the overcurrent trip point. The DCR (RCS in the equation) of the inductor increases approximately 0.39% per degree Centigrade. V ILIM + 2.7 I PH(max) R CS I PH(max) + ǒV IN * VOUTǓ I OUT ) 2 2 L OUT f SW (5) VOUT V IN (6) where • • • • • • • IPH(max) is a maximum value of the phase current allowed IOUT is the total maximum DC output current LOUT is the output inductor value fSW is the switching frequency VOUT is the output voltage VIN is the input voltage RCS is a value of the current sense resistor used or the DCR value of the output inductor, LOUT Resistor Divider Calculation for VOUT, ILIM, OVSET and UVLO Use Figure 8 for setting the output voltage, current limit voltage and overvoltage setting voltage. Select RBIAS using Equation 7. With a voltage divider from VREF, select R6 using Equation 8. WIth a voltage from DIFFO select R4 using Equation 9. With a voltage divider from VIN, select R8 using Equation 10. R1 R BIAS + 0.7 ǒV OUT * 0.7Ǔ (7) R6 + R5 R4 + 0.812 R8 + 1.0 VILIM ǒ0.7 * V ILIMǓ (8) R3 ǒVOUT(ov) * 0.812Ǔ R7 ǒVIN * 1.0Ǔ (9) (10) Feedback Loop Compensation The TPS40130 operates in a peak-current mode and the converter exhibits a single pole response with ESR zero for which Type II compensation network is usually adequate as shown in Figure 4. The load pole is situated at a value calculated using Equation 11. 1 f OP + 2p R OUT C OUT (11) and the ESR zero is situated at a value calculated using Equation 12. 1 f ESRZ + 2p R ESR C OUT (12) To achieve the desired bandwidth the error amplifier has to compensate for modulator gain loss at the crossover frequency. A zero placed at the load pole frequency facilitates that. The ESR zero alters the modulator -1 slope at higher frequencies. To compensate for the ESR zero, a pole in the error amplifier transfer function should be placed at the ESR zero frequency. 14 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 VOUT DIFFO 7 + 9 GSNS 8 COMP C1 R1 12 C2 R2 FB 15 Modulator DROOP + 14 RBIAS LOUT VOUT COUT ROUT 13 VREF + VREF RESR Figure 4. Compensation Components The following expressions help in choosing components of the EA compensation network. It is recommended to fix value of the resistor R1 first as it further simplifies adjustments of the output voltage without altering the compensation network. R1 R2 + AMOD(f) (13) AMOD + V VIN 0.4 (14) where AMOD is the modulator gain at DC f OP AMOD(f) + AMOD fC (15) where AMOD(f) is the modulator gain at the crossover frequency 1 C1 + ǒ2p fOP R2Ǔ (16) C2 + ǒ2p 1 f ESRZ R2Ǔ (17) Introduction of output voltage droop as a measure to reduce amount of filter capacitors changes the transfer function of the modulator as it is shown in Figure 5 and Figure 6. The droop function introduces another zero in the modulator gain function. 15 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 GAIN AND PHASE vs FREQUENCY WITHOUT DROOP 80 80 60 GAIN AND PHASE vs FREQUENCY WITH DROOP Converter Overall Converter Overall EA 60 EA 20 Type II G − Gain − dB G − Gain − dB 40 Modulator 40 Droop Zero 20 Modulator 0 0 Load Pole Load Pole ESR Zero −20 −20 ESR Zero −40 −40 200 200 EA 150 150 Phase EA 100 Phase − ° Phase − ° 100 Converter Overall 50 Converter Overall 50 0 0 Modulator Modulator −50 −50 −100 10 100 1k 10 k f − Frequency − Hz Figure 5. 100 k 1M −100 10 100 1k 10 k f − Frequency − Hz 100 k 1M Figure 6. The droop function, as well as the the output capacitor ESR, introduce a zero on some frequency left from the crossover point. See Equation 18 1 f DROOPZ + VDROOP 2p COUT I OUT(max) ǒ Ǔ (18) To compensate for this zero, pole on the same frequency should be added to the error amplifier transfer function. With Type II compensation network a new value for the capacitor C2 is required compared to the case without droop. 16 TPS40130 www.ti.com C2 + SLUS602 – JUNE 2004 – REVISED AUGUST 2004 C1 2p R2 C1 ǒf DROOPZ * 1 Ǔ (19) When attempting closing the feedback loop at frequency that is close to the theoretical limit, use the above considerations as a first approximation and perform on bench measurements of closed loop parameters as effects of switching frequency proximity and finite bandwidth of voltage and current amplifiers may substantially alter them as it is shown in Figure 7. GAIN AND PHASE vs FREQUENCY 60 Phase 80 50 G − Gain − dB 30 40 20 10 Phase − ° 60 40 20 Gain 0 0 −10 −20 100 VIN = 12 V VOUT = 1.5 V 1k 10 k 100 k f − Frequency − Hz −20 1M Figure 7. Setting the Output Voltage Droop In many applications the output voltage of the converter intentionally allowed to droop as load current increases. This approach also called active load line programming and allows for better use of regulation window and reduces the amount of the output capacitors required to handle a load current step. A resistor from the VREF pin to the DROOP pin sets the desired value of the output voltage droop. See Equation 20. 5000 V DROOP R BIAS R DROOP + I OUT R CS R1 ) RBIAS (20) where • • VDROOP is the value of droop at maximum load current (ILOAD) RCS is a value of the current sense resistor used or the DCR value of the output inductor 17 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 TPS40130 OVSET 6 GSNS Differential Amplifier 8 VOUT 7 + DIFFO 9 R2 R3 C1 COMP 12 R1 Error Amplifier FB 15 R4 + DROOP RBIAS VIN 14 VREF RDROOP IDROOP 13 ILIM R5 17 R6 UVLO R7 24 + R8 700 mV Figure 8. Implementing the Droop Function, Resistor Between DROOP and VREF. VOUT − Output Voltage − V VOUT VDROOP IOUT(max) 0 IOUT − Output Current − A UDG−03116 Figure 9. Output Voltage Droop Characteristic as Output Current Varies. 18 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 Inductor DCR Current Sense Inductor DCR current sensing is a known lossless technique to retrieve current proportional signal. Referring to Figure 10. VDCR L DCR VIN VOUT C R VC UDG−03142 Figure 10. Inductor Current Sense Configuration At any given frequency the DCR voltage can be calculated using Equation 21 and Equation 22. DCR V DCR + ǒVIN * VOUTǓ DCR ) w L 1 V C + ǒVIN * VOUTǓ R) 1 w C w C ǒ Ǔ (21) (22) Voltage across the capacitor is equal to voltage drop across the inductor DCR, VC=VDCR when time constant of the inductor and the time constant of the RC network are equal, see Equation 23. Setting the value of the capacitor to 0.1 µF or 0.01 µF provides for reasonable resistor values. DCR 1 L + R C; t VC + + ; DCRL + t RC DCR ) w L DCR 1 R) w C w C (23) ǒ Ǔ The output signal generated by the network shown in Figure 10 is temperature dependent due to positive thermal coefficient of copper specific resistance KT=1+0.0039 ×(T-25). The temperature variation of the inductor coil can easily exceed 100°C in a practical application leading to approximately 40% variation in the output signal and, in turn, respectively moving the overcurrent threshold and the load line. Thermal Compensation of DCR Current Sensing L DCR C R R2 R1 RNTC RTHE UDG−03142 Figure 11. Temperature Compensating the Inductor DCR 19 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 The relatively simple network shown in Figure 11 is made of passive components including one NTC resistor can provide almost complete compensation for copper thermal variations. The following algorithm and expressions help in determining components of the network. 1. Calculate equivalent impedance of the network at 25°C that matches the inductor parameters RE=L/DCR/C. It is recommended to use COG type capacitors for this application. For example, for L=0.4 µH, DCR=1.22 mΩ, C=10 nF; RE=33.3 kΩ. It is recommended to keep RE< 50 kΩ as higher values may produce false triggering of the current sense fault protection. 2. It is necessary to set the network attenuation value KDIV(25) at 25°C. For example, KDIV(25)=0.85. The attenuation values KDIV(25)>0.9 produces higher values for NTC resistors that are harder to get from suppliers. Attenuation values lower than 0.7 may substantially reduce the network output signal. 3. Based on calculated RE and KDIV(25) values, calculate and pick the closest standard value for the resistor R, R=RE/KDIV(25). For the given example, R=33 kΩ/0.85=38.8 kΩ. The closest standard value from 1% line is R=39.2 kΩ. 4. Pick two temperature values at which curve fitting is to be made. For example T1=50°C and T2=90°C. 5. Find the relative values of RTHE required on each of these temperatures. (T1) (T2) R R R E1 + THE R E2 + THE R THE(25) R THE(25) R THE(T) + K DIV(T) + K DIV(T) 1 * K DIV(T) R K DIV(25) 1 ) 0.0039 (T * 25) 6. For the given example RE1= 0.606, RE2=0.372 7. From the NTC resistor datasheet get relative resistance for resistors with desired curve. For the given example and curve 17 for NTHS NTC resistors from Vishay RNTC1=0.3507 and RNTC2=0.08652 8. Calculate the relative values for network resistors including the NTC resistor. For the given example: R1R=0.281, R2R=2.079, RNTCR=1.1 R1 R + ǒRNTC1 * RNTC2Ǔ RNTC1 RE1 R E2 * R NTC1 ƪ + ƪǒ1 * R1 Ǔ R *1 R E2 ǒ1 * R NTC2Ǔ * RNTC2 ƫ R NTC1 1 * 1 * R1R RE1 * R1 R R2 R + ǒ1 * R NTC1Ǔ RNTC R RE1 * ǒR2RǓ ƫ *1 ǒ1 * RNTC2Ǔ ) RNTC2 R E1 ǒ1 * RNTC1Ǔ RE2 ǒ1 * R NTC1Ǔ * ǒR NTC1 * R NTC2Ǔ *1 *1 9. Calculate absolute value of the NTC resistor as RTHE(25). In given example RNTC=244.3 kΩ 10. Find a standard value for the NTC resistor with chosen curve type. In case the close value does not exist in a desired form factor or curve type. Chose a different type of the NTC resistor and repeat steps 6 to 9. In the example, the NTC resistor with the part number NTHS0402N17N2503J with RNTCS(25)=250 kΩ is close enough to the calculated value. 11. Calculate a scaling factor for the chosen NTC resistor as a ratio between selected and calculated NTC values In the example, l - 1.023. RNTC S k+ RNTC C 12. Calculate values of the remaining network resistors. In the example, R1C=58.7 kΩ and R2C=472.8 kΩ. Pick the closest available 1% standard values: R1=39.2 kΩ; R2=475 kΩ. This completes design of the thermally compensated network for the DCR current sensor. 20 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 R2 C + RTHE(25) k R2 R R1 C + RTHE(25) ƪǒ(1 * k) ) k R1 RǓƫ In the example, R1C = 58.7 kΩ and R2C =472.8 kΩ. Pick the closest available 1% standard values: R1 = 39.2 kΩ; R2 = 475 kΩ. This completes the design of the thermally compensated network for the DCR current sensor. Figure 12 illustrates the fit of the designed network to the required function. RTHE (T5C) − Current Sense Impedance − kΩ 400 r Measured Acquired 300 r 200 100 10 r 20 r 40 60 80 100 TA − Ambient Temperature − °C 120 Figure 12. Temperature Coefficiant vs. Temperature 21 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 APPLICATION INFORMATION Applications Circuit Figure 13 shows a typical applications circuit providing 1.5 VOUT at 40 A. VOUT R2 C5 C4 R1 C19 L1 12 V L2 12 V 5V C1 0.1 µF Q1 D1 BAT54A C13 C21 C12 C20 C2 0.1 µF D2 Q3, Q4 Q2 1 LDRV1 PGND 30 2 VIN5 LDRV2 29 3 SW1 SW2 28 Q5, Q6 1.0 Ω PGND DIFFO R13 10 kΩ VOUT R21 51 Ω R20 51 Ω 4 HDRV1 HDRV2 27 5 BOOT1 BOOT2 26 6 OVSET SS 25 7 VOUT UVLO 24 8 GSNS BP5 23 9 VOUT DIFFO 10 CS1 R10 10 kΩ LOAD 11 CSRT1 C8 R11 C10 12 COMP 13 VREF C9 0.1 µF C15 TPS40130 1.0 Ω R14 10 kΩ C17 R12 10 kΩ 14 DROOP FB 15 FB PGND 5V 12 V C7 2200 pF R22 10 kΩ R6 R7 C6 0.1 µF AGND 22 CS2 21 CSRT2 20 VREF R5 90.9 kΩ RT 19 PGOOD 18 R8 10 kΩ R17 ILIM 17 R16 10 kΩ EN/SYNC 16 5V R18 EN/SYNC R19 UDG−04018 Figure 13. Typical Application Circuit 22 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 APPLICATION INFORMATION (continued) Additional Application Circuits Figure 14 shows a VRM10.x compliant solution where the output voltage is controlled by the VID code of the TPS40120. The six-bit controller provides outputs from 0.8375 V to 1.600 V in 12.5 mV steps for VRM 10.x or provides five-bit control for other Intel processors. When the TPS40120 receives a VID of x11111, indicating the no CPU state, output NCPU1# pulls the soft-start (SS) pin low insuring the output voltage soft-starts with a valid VID code. VOUT R2 C5 C4 R1 C19 L1 12 V L2 12 V 5V Q1 C1 0.1 µF D2 Q3, Q4 D1 BAT54A C13 C21 1 LDRV1 DIFFO LDRV2 29 3 SW1 SW2 28 VCC 14 2 VID0 VOUT 8 6 OVSET R21 51 Ω R20 51 Ω N/C 11 6 VID4 FB 9 7 GND BIAS 10 PGND 5V C7 2200 pF R22 10 Ω 12 V SS 25 7 VOUT UVLO 24 8 GSNS BP5 23 9 DIFFO 10 CS1 SS 11 CSRT1 C8 5 VID3 C15 R6 R7 BP5 3 VID1 NCPU2 13 4 VID2 NCPU1 12 C17 Q5, Q6 1.0 Ω HDRV2 27 5 BOOT1 BOOT2 26 R13 10 kΩ 1 VID5 PGND 30 2 VIN5 4 HDRV1 TPS40120 C2 0.1 µF TPS40130 PGND VOUT C20 Q2 1.0 Ω R14 10 kΩ C12 R11 12 COMP C10 AGND 22 C6 0.1 µF CS2 21 CSRT2 20 RT 19 VREF R5 90.9 kΩ PGOOD 18 13 VREF R12 10 Ω C9 0.1 µF ILIM 17 14 DROOP EN/SYNC 16 R17 R8 10 kΩ R16 10 kΩ 15 FB FB 5V R18 EN/SYNC UDG−04088 Figure 14. Application Circuit with VID Control Figure 15 shows the configuration with the TPS40130 processing power from two different input power sources, 12 V and 5 V is shown. This is useful when there is not sufficient power from a single input source to provide the required output power. The inductor currents are not equal and the difference in the peak currents are approximately: 23 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 APPLICATION INFORMATION (continued) DI PEAK ^ 0.067 (D1 * D2) DCR h (24) where • D1 is the duty cycle for VIN1 • D2 is the duty cycle for VIN2 • DCR is the resistance of the output inductor • η is the efficiency of the converter VOUT R2 C5 C4 R1 C19 L1 12 V L2 5V 5V Q1 C1 0.1 µF D1 BAT54A D2 Q3, Q4 DIFFO R13 10 kΩ R21 51 Ω R20 51 Ω 1 LDRV1 PGND 30 2 VIN5 LDRV2 29 3 SW1 SW2 28 4 HDRV1 HDRV2 27 5 BOOT1 BOOT2 26 6 OVSET SS 25 7 VOUT UVLO 24 8 GSNS BP5 23 9 DIFFO VOUT LOAD AGND 22 10 CS1 R10 10 kΩ C2 0.1 µF C17 C15 12 COMP RT 19 PGOOD 18 13 VREF R12 10 Ω FB 14 DROOP 15 FB R19 Q5, Q6 1.0 Ω PGND 5V 12 V C7 2200 pF R22 10 Ω R6 R7 C6 0.1 µF CSRT2 20 R11 C10 C9 0.1 µF C20 CS2 21 11 CSRT1 C8 C12 TPS40130 PGND VOUT C21 Q2 1.0 Ω R14 10 kΩ C13 VREF R5 90.9 kΩ R8 10 kΩ R17 ILIM 17 EN/SYNC 16 R16 10 kΩ 5V R18 EN/SYNC UDG−04089 Figure 15. Application Circuit with Input Voltage Power Sharing from Two Separate Voltage Sources 24 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 APPLICATION INFORMATION (continued) Figure 16 shows the required 5-V input being generated with an external linear regulator. The regulator shown is the TL431 shunt regulator which is a very cost effective solution. Depending on the required current to the MOSFET gates, the 115 Ω resistor may need to be a ¼ W or ½ W resistor. VOUT R2 C5 C4 R1 C19 L1 L2 12 V 12 V 5V Q1 C1 0.1 µF D1 BAT54A C13 C21 C12 C20 C2 0.1 µF D2 12 V Q3, Q4 Q2 DIFFO TL431 1 LDRV1 2 VIN5 3 SW1 PGND 30 Q5, Q6 1.0 Ω REF 10 kΩ R13 10 kΩ 10 kΩ LDRV2 29 SW2 28 4 HDRV1 HDRV2 27 5 BOOT1 BOOT2 26 6 OVSET SS 25 7 VOUT 8 GSNS PGND 5V 12 V C7 2200 pF R22 10 kΩ R6 R21 51 Ω VOUT R14 10 kΩ R20 51 Ω 9 DIFFO 10 CS1 R10 10 kΩ 11 CSRT1 C8 R11 C10 12 COMP 13 VREF R12 10 Ω C9 0.1 µF C15 TPS40130 1.0 Ω PGND 115 Ω C17 14 DROOP FB 15 FB R19 UVLO 24 BP5 23 AGND 22 R7 C6 0.1 µF CS2 21 CSRT2 20 R5 90.9 kΩ VREF RT 19 PGOOD 18 R8 10 kΩ R17 ILIM 17 R16 10 kΩ EN/SYNC 16 5V R18 EN/SYNC UDG−04090 Figure 16. Application Circuit with an External Linear Regulator Providing VIN5 25 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 APPLICATION INFORMATION (continued) Figure 17 shows the configuration for efficiently operating at high frequencies. With the power stages input at 5 V, the switching losses in the upper MOSFET are significantly reduced. The upper MOSFET should be selected for lower RDS(on) because the conduction losses are somewhat higher at the higher duty cycle. VOUT R2 C5 C4 R1 C19 L1 5V L2 5V 5V Q1 C1 0.1 µF D1 BAT54A C13 C21 C12 C20 C2 0.1 µF D2 Q3, Q4 Q2 1 LDRV1 PGND 30 2 VIN5 LDRV2 29 3 SW1 SW2 28 Q5, Q6 1.0 Ω PGND DIFFO R13 10 kΩ 4 HDRV1 HDRV2 27 5 BOOT1 BOOT2 26 6 OVSET SS 25 7 VOUT UVLO 24 8 GSNS BP5 23 9 DIFFO PGND 5V C7 2200 pF R22 10 kΩ VOUT R20 51 Ω VOUT 10 CS1 R10 10 kΩ 11 CSRT1 C8 R11 C10 12 COMP 13 VREF R12 10 Ω C9 0.1 µF 14 DROOP FB 15 FB R19 AGND 22 5V R6 R21 51 Ω LOAD C15 TPS40130 1.0 Ω R14 10 kΩ C17 R7 C6 0.1 µF CS2 21 CSRT2 20 VREF R5 33.2 kΩ RT 19 PGOOD 18 R8 10 kΩ R17 ILIM 17 R16 10 kΩ EN/SYNC 16 5V R18 EN/SYNC UDG−04091 Figure 17. Application Circuit For High-Frequency Operation With Input Voltage of 5 V 26 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 APPLICATION INFORMATION (continued) Figure 18 shows how to configure for a 5-V output. The resistor dividers on the CSx and CSRTx inputs are necessary to reduce the common mode voltage into the current sense amplifiers. The differential amplifier is not used because with a 5-V output, remote sensing is not generally necessary. If the differential Amplifier is necessary, a voltage divider of 2/3 should be used and the magnitude of the resistors should be about 500 Ω and 1 kΩ. VOUT R2 C5 C4 R1 C19 L1 12 V Q1 C1 0.1 µF D1 BAT54A C30 1000 pF R32 16.9 kΩ 0.1% R33 16.9 kΩ 0.1% BP5 R41 40 kΩ 0.1% VOUT C21 R42 40 kΩ 0.1% R10 10 kΩ 1 LDRV1 PGND 30 2 VIN5 LDRV2 29 3 SW1 SW2 28 4 HDRV1 HDRV2 27 5 BOOT1 BOOT2 26 6 OVSET SS 25 7 VOUT UVLO 24 8 GSNS BP5 23 9 DIFFO AGND 22 10 CS1 12 COMP RT 19 PGOOD 18 13 VREF C9 0.1 µF C2 0.1 µF C17 C15 R12 10 Ω FB 14 DROOP 15 FB R19 1.62 kΩ 1.0 Ω Q5, Q6 PGND 5V C7 2200 pF R22 10 kΩ R34 16.9 kΩ 0.1% 12 V C31 1000 pF R6 R35 16.9 kΩ 0.1% R7 C6 0.1 µF CSRT2 20 R11 C10 LOAD C20 CS2 21 11 CSRT1 C8 C12 TPS40130 1.0 Ω PGND R14 10 kΩ C13 Q2 DIFFO R13 10 kΩ 12 V 5V D2 Q3, Q4 L2 R5 90.9 kΩ R44 40 kΩ 0.1% R8 10 kΩ R43 40 kΩ 0.1% VREF R17 ILIM 17 EN/SYNC 16 R16 10 kΩ 5V R18 EN/SYNC UDG−04092 Figure 18. Application Circuit for Providing 5-V Output 27 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 TYPICAL CHARACTERISTRICS VDIFFOUT (50 mV/div) VDIFFOUT (50 mV/div) IL1 (5 A / div) IL1, IL2 (5 A/div) IL2 (5 A / div) VSW2 (10 V / div) VSW2 (10 V / div) t − Time − 20 µs/div Figure 19. Load Transient t − Time − 4 µs/div Figure 20. Load Transient Rising Edge VSW1 (10 V/div) VDIFFOUT (50 mV/div) IL1 (5 A / div) IL2 (5 A / div) VEN/SYNC (5 V / div) VSS (100 mV / div) VSW2 (10 V / div) t − Time − 4 µs/div Figure 21. Load Transient Falling Edge 28 VDIFFOUT (500 mV/div) t − Time − 40 µs/div Figure 22. Start-Up with EN/SYNC and Showing Soft-Wait Time TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 TYPICAL CHARACTERISTRICS (continued) VDIFFOUT (500 mV/div) VSS (500 mV / div) VEN/SYNC (5 V / div) VHDRV1 (10 V / div) VEN/SYNC (5 V/div) VHDRV2 (10 V / div) t − Time − 400 µs/div t − Time − 400 ns/div Figure 23. Start-Up with EN/SYNC VEN/SYNC (5 V/div) Figure 24. External Clock on EN/SYNC VSS (500 mV / div) VLDRV1 (5 V / div) VHDRV1 (10 V / div) VHDRV2 (10 V / div) VOVSET (1 V / div) t − Time − 40 ns/div Figure 25. External Clock on EN/SYN and Delay to HDRV t − Time − 4 ms/div Figure 26. Overvoltage, Latch and Re-Start 29 TPS40130 www.ti.com SLUS602 – JUNE 2004 – REVISED AUGUST 2004 TYPICAL CHARACTERISTRICS (continued) VFB (200 mV / div) VFB (200 mV/ div) VSS (1 V/ div) VSS (1 V/div) IL2, IL2 (10 A / div) IL2, IL2 (10 A / div) VFB = 0.588 V t − Time − 4 ms/div t − Time − 40 µs/div Figure 27. Overcurrent, Hiccup Mode Figure 28. Overcurrent LAYOUT CONSIDERATIONS Introduction There are two general classes of signals to consider for proper layout, high-current switching and low-level analog. Refer to Figure 13 for references to components. A printed wiring board (PWB) with a minimum of four layers should be used. Two Ground Planes A basic requirement is two separate ground planes that ultimately get connected together at a point where no switching currents are present, the power ground (PGND) and the analog ground (AGND). They should be implemented as split planes on the top and bottom layers. The PGND is used for all high-current signals including LDRV1, LDRV2, lower MOSFETs and input and output decoupling capacitors. PGND should be used on the top layer around the high current components and on the bottom layer as a minimum. The AGND is used for low level signals such as: soft-start, RT, VREF, FB, BP5 decoupling to AGND. AGND should be used on the top layer around the device and low level components and on the bottom layer as a minimum. The signals which connect to the two different ground planes are shown in Figure 13 using different symbols for each ground. Low-Level Signal Connections and Routing Current Sense Signals Using inductor current sense has advantages over using a low-value, high-power current-sense resistor, but attention must be paid to how the current sense signals are generated and routed. Connection Resistor R2 and capacitor C5 generate the current sense signal for phase 1 and resister R1 and capacitor C4 generate the current sense signal for phase 2. The R2-C5 and R1-C4 components must be connected directly to the pads for L1 and L2, respectively. 30 www.ti.com TPS40130 SLUS602 – JUNE 2004 – REVISED AUGUST 2004 LAYOUT CONSIDERATIONS (continued) Routing The traces that connect to C5 and C4 should be made directly at the capacitor(s) and routed on an internal signal plane to CS1, CSRT1 and CS2, CSRT2, respectively. In addition, a small value of R-C filter may be used on the CSx and CSRTx lines, with these components placed close to the device. A 5.1-Ω resistor in series with the CSx and CSRTx lines and a 100-pF capacitor between the CSx and CSRTx lines, provides additional filtering, a prudent measure since the level of switching noise in a given layout is not fully known until the board is being tested for the first time. Differential Amplifier Signals The differential amplifier provides optimum regulation at the load point. Connection The signal connections for VOUT and GSNS should be made across the closest capacitor to the load point. This ensures the most accurate DC sensing and most noise free connection also. Routing Since the load point may be physically several inches, or more, from the device, it is very likely that the VOUT and GSNS inputs to the differential amplifier are corrupted by switching noise. The signals should be routed on an internal layer, and the R-C filter approach recommended for the CSx and CSRTx lines is applicable for these lines as well. High-Current Connections and Routing Device Decoupling for VIN5 and BP5 The 1.0-µF decoupling capacitor for VIN5 should be placed close to pins 1 and 30 of the device. The decoupling capacitor for BP5 should be placed close to pins 22 and 23 of the device. Symmetry Symmetry is especially important in the power processing components when considering the device placement between the two phases. Input ceramic decoupling capacitors should be placed close to the upper MOSFETs and the current path from the upper MOSFET drain to the lower MOSFET source should be on the PGND with maximum copper area. Output capacitors should be placed symmetrically between the output inductor and lower MOSFET for each phase. SW Node The SW node consists of the source of the upper MOSFET, the drain of the lower MOSFET,and the output inductor. These components should be placed to minimize the area of the SW node. The area of the SW node determines the amount of stray capacitance and inductance that causes ringing during switching transitions. Lower MOSFET Gate Drive, LDRV1 and LDRV2 A resistor, with a value of between approximately 1.0 Ω and 2.2 Ω should be placed between LDRVx and the gate of the respective MOSFET. The resistors are necessary if the falling SW node pulls the gate voltage below GND. This can occur if the MOSFET QGD is larger than QGS. The traces for LDRVx should be wide, (0.05 to 0.1 inches) and routed on the top layer if possible. If routing must go to another layer, use multiple vias for interconnect. The return signal from the MOSFET drain to PGND on the device should be as wide as the return for LDRVx. Upper MOSFET Gate Drive, HDRV1 and HDRV2 The traces for HDRVx and SWx should be wide, (0.05 to 0.1inches), and routed on the top layer if possible. If routing must go to another layer, use multiple vias for interconnect. 31 MECHANICAL DATA MPDS019D – FEBRUARY 1996 – REVISED FEBRUARY 2002 DBT (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 30 PINS SHOWN 0,50 0,27 0,17 30 16 0,08 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 15 0°–ā8° 0,75 0,50 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 20 24 28 30 38 44 50 A MAX 5,10 6,60 7,90 7,90 9,80 11,10 12,60 A MIN 4.90 6,40 7,70 7,70 9,60 10,90 12,40 DIM 4073252/E 02/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated