CMLMICRO MX929BDS

MX929B
COMMUNICATION SEMICONDUCTORS
DATA BULLETIN
4-Level FSK Modem Data Pump
PRELIMINARY INFORMATION
Features
Applications
4-Level Root Raised Cosine FSK Modulation
RD-LAP¥
¥ Systems
Half Duplex, 4800 to 19.2kbps
RCR STD-47 Systems
Increase Channel Bit Rate/Hz
Two Way Paging Systems
Full Data Packet Framing
Mobile Data Systems
Impulse and NRZ Signal Modes
Wireless Telemetry
Enhanced Performance in Noisy Conditions
DataTAC¥
¥ Terminals
Error Detection and Error Correction
Portable Wireless Data Equipment
Low Power 3.3V/5.0V Operation
MX929B
RADIO
MODULATOR
ANALOG TX
RF
DISCRIMINATOR
ANALOG RX
MODEM
DATA
PUMP
HOST µC
DATA AND
CONTROL BUS
SYSTEM
APPLICATION
PROCESSING
The MX929B is a low voltage CMOS device containing all of the baseband signal processing and Medium
Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data
Modem. It interfaces with the modem host C and the radio modulation/demodulation circuits to deliver
reliable two-way transfer of the application data over a wireless link.
The MX929B assembles application data received from the host C, adds forward error correction (FEC) and
error detection (CRC) information, and interleaves the result for burst-error protection. After automatically
adding symbol and frame sync codewords, the data packet is converted into filtered 4-level analog signals for
modulating the radio transmitter.
In receive mode, the MX929B performs the reverse function using the analog signals from the receiver
discriminator. After error correction and removal of the packet overhead, the recovered application data is
supplied to the host C. CRC detected residual uncorrected data errors will be flagged. Readout of the SNR
value during receipt of a packet is also provided.
The MX929B uses data block sizes and FEC/CRC Algorithms that are compatible with RD-LAP and
RCR STD-47 over-air-standards. The device is programmable to operate at standard bit rates from a wide
range of Xtal/clock frequencies.
The MX929B may be used with a 3.0V to 5.5V power supply and is available in the following package styles:
24-pin SSOP (MX929BDS), 24-pin SOIC (MX929BDW), and 24-pin PDIP (MX929BP).
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 2 of 50
MX929B PRELIMINARY INFORMATION
CONTENTS
Section
Page
1. Block Diagram ............................................................................................................... 6
2. Signal List ...................................................................................................................... 7
3. External Components ................................................................................................... 8
4. General Description .................................................................................................... 10
4.1
Description of Blocks ....................................................................................................... 10
4.1.1
Data Bus Buffers................................................................................................................... 10
4.1.2
Address and R/W Decode .................................................................................................... 10
4.1.3
Status and Data Quality Registers ........................................................................................ 10
4.1.4
Command, Mode, and Control Registers ............................................................................. 10
4.1.5
Data Buffer............................................................................................................................ 10
4.1.6
CRC Generator/Checker ...................................................................................................... 10
4.1.7
FEC Generator/Checker ....................................................................................................... 10
4.1.8
Interleave/De-Interleave Buffer ............................................................................................. 10
4.1.9
Frame Sync Detect ............................................................................................................... 10
4.1.10 Rx Input Amp ........................................................................................................................ 11
4.1.11 RRC Low Pass Filter............................................................................................................. 11
4.1.12 Tx Output Buffer ................................................................................................................... 12
4.1.13 Rx Level/Clock Extraction ..................................................................................................... 13
4.1.14 Clock Oscillator and Dividers ................................................................................................ 13
4.2
Modem - µC Interaction ................................................................................................... 13
4.3
Binary to Symbol Translation ........................................................................................... 14
4.4
Frame Structure............................................................................................................... 15
4.5
The Programmer's View .................................................................................................. 16
4.5.1
Data Block Buffer .................................................................................................................. 16
4.5.2
Command Register ............................................................................................................... 17
4.5.2.1
Command Register B7: AQSC - Acquire Symbol Clock ............................................ 17
4.5.2.2
Command Register B6: AQLEV - Acquire Receive Signal Levels ............................. 17
4.5.2.3
Command Register B5: CRC .................................................................................... 17
4.5.2.4
Command Register B4: TXIMP - Tx Level/Impulse Shape ........................................ 17
4.5.2.5
Command Register B3 - Reserved ............................................................................ 17
4.5.2.6
Command Register B2, B1, B0: TASK....................................................................... 18
4.5.2.7
NULL: No effect .......................................................................................................... 19
4.5.2.8
SFP: Search for Frame Preamble .............................................................................. 19
4.5.2.9
RHB: Read Header Block........................................................................................... 20
4.5.2.10
RILB: Read 'Intermediate' or 'Last' Block ................................................................... 20
4.5.2.11
SFS: Search for Frame Sync...................................................................................... 20
4.5.2.12
R4S: Read 4 Symbols ................................................................................................ 20
4.5.2.13
RSID: Read Station ID................................................................................................ 20
4.5.2.14
T24S: Transmit 24 Symbols ....................................................................................... 21
4.5.2.15
THB: Transmit Header Block...................................................................................... 21
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
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4-Level FSK Modem Data Pump
TIB: Transmit Intermediate Block ............................................................................... 21
4.5.2.17
TLB: Transmit Last Block ........................................................................................... 21
4.5.2.18
T4S: Transmit 4 Symbols ........................................................................................... 21
4.5.2.19
TSID: Transmit Station ID ............................................................................................ 22
4.5.2.20
RESET: Stop any current action................................................................................. 22
4.5.2.21
Task Timing................................................................................................................ 22
4.5.2.22
RRC Filter Delay......................................................................................................... 23
Control Register .................................................................................................................... 24
4.5.3.1
Control Register B7, B6: CKDIV - Clock Division Ratio.............................................. 24
4.5.3.2
Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches ......... 24
4.5.3.3
Control Register B3, B2: LEVRES - Level Measurement Modes ............................... 25
4.5.3.4
Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes............... 25
4.5.4
Mode Register....................................................................................................................... 26
4.5.4.1
Mode Register B7: IRQEN - IRQ Output Enable....................................................... 26
4.5.4.2
Mode Register B6: INVSYM - Invert Symbols ............................................................ 26
4.5.4.3
Mode Register B5: TX/RX - Tx/Rx Mode.................................................................. 26
4.5.4.4
Mode Register B4: RXEYE - Show Rx Eye ................................................................ 27
4.5.4.5
Mode Register B3: PSAVE - Powersave.................................................................... 27
4.5.4.6
Mode Register B2: SSIEN - 'S' Symbol IRQ Enable .................................................. 27
4.5.4.7
Mode Register B1, B0: SSYM - 'S' Symbol To Be Transmitted................................. 27
4.5.5
Status Register ..................................................................................................................... 28
4.5.5.1
Status Register B7: IRQ - Interrupt Request .............................................................. 28
4.5.5.2
Status Register B6: BFREE - Data Block Buffer Free................................................ 28
4.5.5.3
Status Register B5: IBEMPTY - Interleave Buffer Empty........................................... 28
4.5.5.4
Status Register B4: DIBOVF - De-Interleave Buffer Overflow ................................... 29
4.5.5.5
Status Register B3: CRCERR - CRC Checksum Error .............................................. 29
4.5.5.6
Status Register B2: 'S' Symbol Ready........................................................................ 29
4.5.5.7
Status Register B1, B0: SVAL - Received 'S' Symbol Value ...................................... 29
4.5.6
Data Quality Register ............................................................................................................ 29
CRC, FEC and Interleaving.............................................................................................. 30
4.6.1
4.7
MX929B PRELIMINARY INFORMATION
4.5.2.16
4.5.3
4.6
Page 3 of 50
Cyclic Redundancy Codes .................................................................................................... 30
4.6.1.1
CRC0.......................................................................................................................... 30
4.6.1.2
CRC1.......................................................................................................................... 30
4.6.1.3
CRC2.......................................................................................................................... 30
4.6.1.4
Forward Error Correction............................................................................................ 30
4.6.1.5
Interleaving ................................................................................................................. 31
Transmitted Symbol Shape.............................................................................................. 31
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
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4-Level FSK Modem Data Pump
Page 4 of 50
MX929B PRELIMINARY INFORMATION
5. Application................................................................................................................... 33
5.1
Transmit Frame Example................................................................................................. 33
5.2
Receive Frame Example.................................................................................................. 36
5.3
Clock Extraction and Level Measurement Systems ......................................................... 39
5.3.1
Supported Types of Systems................................................................................................ 39
5.3.2
Clock and Level Acquisition Procedures with RF Carrier Detect .......................................... 39
5.3.3
Clock and Level Acquisition Procedure without RF Carrier Detect....................................... 39
5.3.4
Automatic Acquisition Functions ........................................................................................... 40
5.4
AC Coupling..................................................................................................................... 40
5.5
Radio Performance.......................................................................................................... 42
5.6
Received Signal Quality Monitor ...................................................................................... 43
6. Performance Specification......................................................................................... 44
6.1
Electrical Performance..................................................................................................... 44
6.1.1
Absolute Maximum Ratings .................................................................................................. 44
6.1.2
Operating Limits.................................................................................................................... 44
6.1.3
Operating Characteristics ..................................................................................................... 45
6.1.3.1
6.1.4
6.1.4.1
6.1.5
6.2
Operating Characteristics Notes: ............................................................................... 46
Timing ................................................................................................................................... 46
Timing Notes: ............................................................................................................. 46
Typical Bit Error Rate ............................................................................................................ 48
Packaging........................................................................................................................ 49
MX-COM, Inc. Reserves the right to change specifications at any time and without notice
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
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4-Level FSK Modem Data Pump
Page 5 of 50
MX929B PRELIMINARY INFORMATION
Figures
Figure
Page
Figure 1: Block Diagram ................................................................................................................................... 6
Figure 2: Recommended External Components .............................................................................................. 8
Figure 3: Typical Modem C connections ...................................................................................................... 10
Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode................................................ 11
Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5) .................. 12
Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5)........... 12
Figure 7: Over-Air Signal Format.................................................................................................................... 15
Figure 8: Alternative Frame Structures........................................................................................................... 16
Figure 9: Transmit Task Overlapping ............................................................................................................. 18
Figure 10: Receive Task Overlapping ............................................................................................................ 19
Figure 11: Transmit Task Timing Diagram ..................................................................................................... 23
Figure 12: Receive Task Timing Diagram ...................................................................................................... 23
Figure 13: RRC Low Pass Filter Delay ........................................................................................................... 23
Figure 14: Ideal 'RXEYE' Signal ..................................................................................................................... 27
Figure 15: Typical Data Quality Reading vs S/N............................................................................................. 29
Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 1 ......................................................... 31
Figure 17: Tx Signal Eye TXIMP = 0 .............................................................................................................. 31
Figure 18: Tx Signal Eye TXIMP = 1 .............................................................................................................. 32
Figure 19: Transmit Frame Example Flowchart, Main Program .................................................................... 34
Figure 20: Tx Interrupt Service Routine.......................................................................................................... 35
Figure 21: Receive Frame Example Flowchart, Main Program....................................................................... 37
Figure 22: Rx Interrupt Service routine........................................................................................................... 38
Figure 23: Acquisition Sequence Timing ........................................................................................................ 39
Figure 24: Effect of AC Coupling on BER (without FEC)................................................................................ 40
Figure 25: Decay Time - AC Coupling ............................................................................................................ 41
Figure 26: Typical Connections between Radio and MX929B ....................................................................... 42
Figure 27: Received Signal Quality Monitor Flowchart ................................................................................... 43
Figure 28: C Parallel Interface Timings ........................................................................................................ 47
Figure 29: Typical Bit Error Rate With and Without FEC ............................................................................... 48
Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX929BDW ................................................ 49
Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX929BDS................................................ 49
Figure 32: 24-pin PDIP Mechanical Outline: Order as part no. MX929BP .................................................... 50
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
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4-Level FSK Modem Data Pump
Page 6 of 50
MX929B PRELIMINARY INFORMATION
1. Block Diagram
STATUS
REGISTER
IRQ
DATA
QUALITY
REGISTER
µCONTROLLER
INTERFACE
8
D0
D1
D2
D3
D4
D5
D6
D7
COMMAND
REGISTER
DATA
BUS
BUFFERS
CONTROL
REGISTER
DATA
BUFFER
WR
RD
CRC
GENERATOR/
CHECKER
FEC
ENCODER/
DECODER
ADDRESS
AND
R/W
DECODE
CS
A0
A1
FRAME
SYNC DETECT
INTERLEAVE/
DE-INTERLEAVE
VDD
VDD
MODE
REGISTER
VBIAS
Tx Symbols
Rx Symbols
VSS
RXAMPOUT
Rx Input Amp
VBIAS
RXIN
DOC1
Tx
Rx
RRC
LOW PASS
FILTER
XTAL
VBIAS
CLOCK
OSCILLATOR
AND
DIVIDERS
Rx
Tx
Rx LEVEL/CLOCK
EXTRACTION
DOC2
RxEye
Rx
TXOUT
Tx
Tx Output Buffer
XTAL /
CLOCK
Figure 1: Block Diagram
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
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4-Level FSK Modem Data Pump
Page 7 of 50
MX929B PRELIMINARY INFORMATION
2. Signal List
Pin No.
Signal
Type
1
IRQ
output
2
D7
BUS
3
D6
BUS
4
D5
BUS
5
D4
BUS
6
D3
BUS
7
D2
BUS
8
D1
BUS
9
Description
A 'wire-ORable' output for connection to the host C's Interrupt
Request input. When active, this output has a low impedance
pull down to VSS. It has high impedance when inactive.
Pins 2-9 (D7-D0) are 8-bit, bi-directional,
3-state C interface data lines
D0
BUS
10
RD
input
Read. An active low logic level input used to control the reading
of data from the modem into the host C.
11
WR
input
Write. An active low logic level input used to control the writing
of data into the modem from the host C.
12
VSS
power
Negative supply (ground).
13
CS
input
Chip Select. An active low logic level input to the modem used
to enable a data read or write operation.
14
A0
input
Logic level modem register select input
15
A1
input
16
XTAL
output
Logic level modem register select input
17
XTAL/CLOCK
input
18
DOC 2
output
Connection to the Rx level measurement circuitry. Should be
capacitive coupled to VSS.
19
DOC 1
output
Connection to the Rx level measurement circuitry. Should be
capacitive coupled to VSS
20
TXOUT
output
Tx signal output from the modem.
21
VBIAS
output
A bias line for the internal circuitry held at VDD /2. This pin must
be bypassed to VSS by a capacitor mounted close to the device
pins.
22
RXIN
input
23
RXAMPOUT
output
Output of the Rx input amplifier.
24
VDD
power
Positive supply. Levels and voltages are dependent upon this
supply. This pin should be bypassed to VSS by a capacitor
mounted close to the device pins.
Output of the on-chip oscillator.
Input to the on-chip oscillator, for an external Xtal circuit or
clock.
Input to the Rx input amplifier.
Note: Internal protection diodes are connected from each signal pin to VDD and VSS.
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
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4-Level FSK Modem Data Pump
Page 8 of 50
MX929B PRELIMINARY INFORMATION
3. External Components
µCONTROLLER INTERFACE
VDD
1
2
3
4
IRQ
D7
D6
D5
D4
D3
D2
D1
D0
RD
WR
5
6
7
8
9
VSS
CS
A0
A1
MX929B
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
C8
C1
R2
RXAMPOUT
RXIN
VBIAS
TXOUT
To Tx Frequency
Modulator
R4
DOC1
DOC2
XTAL/CLOCK
XTAL
A1
A0
CS
From Rx FM
Discriminator
R1
C6
C7
17
C5
C2
XTAL/CLOCK
C3
X1
R3
16
C4
XTAL
Figure 2: Recommended External Components
Component
R1
R2
R3
R4
C1
C2
C3
©2001 MX-COM, INC.
Notes
1
Value
100k
1M
100k
0.1 µF
0.1 µF
3
Tolerance
20%
5%
20%
5%
20%
20%
20%
Component
C4
C5
C6
C7
C8
Notes
3
4
5
5
4
X1
2
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Value
Fax: 336 744 5054
Tolerance
20%
5%
20%
20%
5%
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4-Level FSK Modem Data Pump
Page 9 of 50
MX929B PRELIMINARY INFORMATION
Recommended External Component Notes:
1. See Section 4.1.10.
2. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least
40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain
crystal oscillator design assistance, consult your crystal manufacturer.
3. The values used for C3 and C4 should be suitable for the frequency of the crystal X1. As a guide, values
(including stray capacitance) of 33pF at 1MHz falling to 18pF at 10MHz will generally prove suitable.
Crystal frequency tolerances are discussed in Section 4.5.3.4.
4. Values C5 and C8 should be equal to 750,000 / symbol rate, e.g.
Symbol Rate
C5 and C8
2400 symbols/second
330pF
4800 symbols/second
150pF
9600 symbols/second
82pF
5. Values C6 and C7 should be equal to 50,000 / symbol rate, e.g.
©2001 MX-COM, INC.
Symbol Rate
C6 and C7
2400 symbols/second
0.022F
4800 symbols/second
0.01F
9600 symbols/second
4700pF
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Fax: 336 744 5054
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4-Level FSK Modem Data Pump
Page 10 of 50
MX929B PRELIMINARY INFORMATION
4. General Description
4.1
4.1.1
Description of Blocks
Data Bus Buffers
Eight bi-directional 3-state logic level buffers between the modem's internal registers and the host µC's data
bus lines.
4.1.2
Address and R/W Decode
This block controls the transfer of data bytes between the µC and the modem's internal registers according to
the state of the Write and Read Enable inputs ( WR and RD ), the Chip Select input ( CS ), and the Register
Address inputs A0 and A1.
The Data Bus Buffers, Address, and R/W Decode blocks provide a byte-wide parallel µC interface, which can
be memory-mapped, as shown in Figure 3.
D0:7
D0:7
Data Bus
A0:1
A0:1
Address Bus
A2:7
µC
Address Decode
Circuit
MODEM
VDD
IRQ pull up
resistor
IRQ
CS
IRQ
WR
RD
WR
RD
Figure 3: Typical Modem 2C connections
4.1.3
Status and Data Quality Registers
Two 8-bit registers which the µC can read to determine the status of the modem and received data quality.
4.1.4
Command, Mode, and Control Registers
The values written by the µC to these 8-bit registers control the operation of the modem.
4.1.5
Data Buffer
A 12-byte buffer used to hold, receive or transmit data to or from the µC.
4.1.6
CRC Generator/Checker
A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum
bits, which may be included in the transmitted data blocks so the receive modem can detect transmission
errors.
4.1.7
FEC Generator/Checker
In transmit mode, this circuit adds Forward Error Correction bits to the transmitted data, resulting in the
conversion of binary data to 4-level symbols. In receive mode, this circuit translates received 4-level symbols
to binary data, using the FEC information to correct a large proportion of transmission errors.
4.1.8
Interleave/De-Interleave Buffer
This circuit interleaves data symbols within a block before transmission and de-interleaves the received data
so that the FEC system is best able to handle short noise bursts or fades.
4.1.9
Frame Sync Detect
This circuit, which is only active in receive mode, is used to look for the 24-symbol Frame Synchronization
pattern that is transmitted to mark the start of every frame.
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
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4-Level FSK Modem Data Pump
Page 11 of 50
MX929B PRELIMINARY INFORMATION
4.1.10 Rx Input Amp
This amplifier allows the received signal input to the modem to be set to the optimum level by suitable
selection of the external components R1 and R2. The value of R1 should be calculated to give 0.2 x VDD
voltsP-P at the RXAMPOUT pin for a received '...+3 +3 -3 -3 ...' sequence.
A capacitor may be placed in series with R1 if ac coupling of the received signal is desired (see Section 5.4),
otherwise the DC level of the received signal should be adjusted so that the signal at the modem's
RXAMPOUT pin is centered around VBIAS (VDD/2).
4.1.11 RRC Low Pass Filter
This filter, which is used in both transmit and receive modes, is a linear-phase lowpass filter with a 'Root
Raised Cosine' frequency response defined by:
H( f ) = 1 for 0 < f <
1- b
2T
5
( 5Tf - )
2
1 sin
1- b
b
for
2
2
2T
H( f ) =
H( f ) = 0 for f >
Where
<f <
1+ b
2T
1+ b
2T
b = 0.2,
T=
1
symbol rate
This frequency response is illustrated in Figure 5 and Figure 6.
In transmit mode, the 4-level symbols are passed through this filter to eliminate the high frequency
components which would otherwise cause interference into adjacent radio channels. The input applied to the
RRC Tx filter may be impulses or full-width symbols depending on the setting of the Command Register
TXIMP bit. See Section 4.7.
+3
MX929B
Bit
pairs
Data
Encoding
+1
-1
-3
binary symbol
Symbols
Transmit
filter
Frequency
modulator
Modem
Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Mode
In receive mode, the filter is used to reject HF noise and to equalize the received signal to a form suitable for
extracting the 4-level symbols. The equalization characteristics are determined by the setting of the Command
Register TXIMP bit.
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
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4-Level FSK Modem Data Pump
Page 12 of 50
MX929B PRELIMINARY INFORMATION
0
-5
-10
dB -15
-20
-25
-30
0
0.1
0.2
0.3
0.4
0.5
Frequency / Bit Rate
Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5)
0
-5
-10
dB -15
-20
-25
-30
0
0.2
0.4
0.6
0.8
1.0
Frequency / Symbol Rate
Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5)
4.1.12 Tx Output Buffer
This is a unity gain amplifier used in the transmit mode to buffer the output of the Tx low pass filter. In receive
mode, the input of this buffer is connected to VBIAS, unless the RXEYE bit of the Control Register is '1', in
which case it is connected to the received signal. When changing from Rx to Tx mode, the input to this buffer
will be connected to VBIAS for 8 symbol times while the RRC filter settles.
Note: The RC low pass filter formed by the external components R4 and C5 between the TXOUT pin and the
input to the radio's frequency modulator forms an important part of the transmit signal filtering. These
components may form part of any DC level-shifting and gain adjustment circuitry. The value used for
C5 should take into account stray circuit capacitance, and its ground connection should be positioned to
give maximum attenuation of high frequency noise into the modulator.
The signal at the TXOUT pin is centered around VBIAS. It is approximately 0.2 x VDD voltsP-P for a
continuous ’+3 +3 -3 -3...' pattern with TXIMP = 0. For typical Tx Eye Diagrams refer to Section
4.7, Figure 17 and Figure 18. For typical Rx Eye Diagrams refer to Section 4.5.4.4, Figure 14.
A capacitor may be placed in series with the input to the frequency modulator if AC coupling is desired.
See Section 5.4.
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4-Level FSK Modem Data Pump
Page 13 of 50
MX929B PRELIMINARY INFORMATION
4.1.13 Rx Level/Clock Extraction
These circuits, which operate only in receive mode, derive a symbol rate clock from the received signal and
measure the received signal amplitude and DC offset. This information is then used to extract the received 4level symbols and also to provide an input to the received Data Quality measuring circuit. The external
capacitors C6 and C7 form part of the received signal level measuring circuit.
The capacitors C6 and C7 are driven from a very high impedance source so any measurement of the voltages
on the DOC pins must be made via high input impedance (MOS input) voltage followers to avoid disturbance
of the level measurement circuits.
Further details of the level and clock extraction functions are given in Section 5.3.
4.1.14 Clock Oscillator and Dividers
These circuits derive the transmit symbol rate (and the nominal receive symbol rate) by frequency division of a
reference frequency which may be generated by the on-chip Xtal oscillator or applied from an external source.
Note: If the on-chip Xtal oscillator is to be used, then the external components X1, C3, C4, and R3 are
required. If an external clock source is to be used, then it should be connected to the XTAL/CLOCK
input pin, the XTAL pin should be left unconnected, and X1, C3, C4, and R3 should not be installed.
4.2
Modem - µC Interaction
In general, data is transmitted over-air in the form of messages, or 'Frames', consisting of a 'Frame Preamble'
followed by one or more formatted data blocks. The Frame Preamble includes a Frame Synchronization
pattern designed to allow the receiving modem to identify the start of a frame. The following data blocks are
constructed from the 'raw' data using a combination of CRC (Cyclic Redundancy Checksum) generation,
Forward Error Correction coding, and Interleaving. Details of the message formats handled by the modem are
provided in Section 4.3, Figure 7, and Figure 8.
To reduce the processing load on the associated C, the MX929B modem has been designed to perform as
much of the computationally intensive work involved in Frame formatting and de-formatting and (when in
receive mode) searching for and synchronizing onto the Frame Preamble. In normal operation, the modem
will only require servicing by the µC once per received or transmitted block.
Therefore, to transmit a block, the controlling µC needs only to load the unformatted 'raw' binary data into the
modem's Data Block Buffer, then instruct the modem to format and transmit that data. The modem will then
calculate and add the CRC bits as required, encode the result as 4-level symbols (with Forward Error
Correction coding), and interleave the symbols before transmission.
In receive mode, the modem can be instructed to assemble a block's worth of received symbols, de-interleave
the symbols, translate them to binary, perform Forward Error Correction, and check the resulting CRC before
placing the received binary data into the Data Block Buffer for the µC to read.
The modem can also handle the transmission and reception of unformatted data using the T4S, T24S, and
R4S tasks as described in Sections 4.3 and 4.5.2. These tasks are normally used for the transmission of
Symbol and Frame Synchronization sequences. These tasks may also be used for the transmission and
reception of special test patterns or special data formats. In such a case, care should be taken to ensure that
the transmitted TXOUT signal contains enough level and timing information for the receiving modem's level
and clock extraction circuits to function correctly. See Section 5.3.
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4-Level FSK Modem Data Pump
4.3
Page 14 of 50
MX929B PRELIMINARY INFORMATION
Binary to Symbol Translation
Although the over-air signal, and therefore the signals at the modem TXOUT and RXIN pins, consists of 4level symbols, the raw data passing between the modem and the µC is in binary form. Translation between
binary data and the 4-level symbols is done in one of two ways, depending on the task being performed.
1. Direct way: (simplest form) - converts between two binary bits and a single symbol, such as the 'S'
Channel Status symbol.
SYMBOL
MSB
LSB
+3
+1
-1
-3
1
1
0
0
1
0
0
1
Accordingly, 1 byte = 4 symbols = 8 bits, and one byte translates to four symbols for the T4S and R4S tasks
and six bytes translates to twenty-four symbols for the T24S task described in Section 4.5.2.
MSB
Bits:
Symbols:
LSB
7
6
a
5
4
3
b
2
c
send first
1
0
d
send last
2. FEC way: (more complicated) - essentially translates groups of 3 binary bits to pairs of 4-level symbols
using a Forward Error Correcting coding scheme for the block oriented tasks THB, TIB, TLB, RHB, RILB,
and RSID described in Section 4.5.2.
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4-Level FSK Modem Data Pump
4.4
Page 15 of 50
MX929B PRELIMINARY INFORMATION
Frame Structure
The MX929B Frame Structure as used in a RD-LAP system is illustrated in Figure 7, and consists of a
Frame Preamble (comprising a 24-symbol Frame Synchronization pattern and Station ID block), followed by a
'Header Block', one or more 'Intermediate Blocks', and a 'Last Block'. Channel Status (S) symbols are
included at regular intervals. The first Frame of any transmission is preceded by a Symbol Synchronization
pattern.
msb
Station ID
lsb
Byte 7 6 5 4 3 2 1 0
System ID
0
Domain ID
1
Base ID
2
3
CRC0
Byte
0
1
2
3
4
5
6
7
8
9
10
11
µC binary data stored
in MX929B data block
memory configured as
header, intermediate, or
last block by MX929B
task being executed.
7
07
Byte 0
0
Byte 1
7
Byte 2
Header Block
Intermediate Blocks
Last Block
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Address
&
Control
Data Bytes
(10 bytes)
(12 bytes)
Data Bytes
(0-8)
-------------Pad Bytes
(0-8)
CRC2
(4 bytes)
CRC1
(2 bytes)
07
7
2 0
Byte 3
Byte 0
0
7
Byte 1
0
Byte 11
'000'
'000'
0
1
8
2
9
10
0
tri-bits
1
FEC TRELLIS CODING / DECODING
(ERROR CORRECTION)
0
20 21
1
3
2
4
5
29 30 31 32
FEC TRELLIS CODING / DECODING
(ERROR CORRECTION)
4-level
symbols
0
1
64 65
2
INTERLEAVING / DE-INTERLEAVING
22 Symbols
Block:
Over-air Signal
(symbols)
Symbol Frame
'Header'
Station
S
Sync
Sync S
Block
ID
69
24
24
1
22
1
S
22 Symbols
Intermediate Blocks
69
Frame
Preamble
69
S
22 Symbols
'Last'
Block
69
Frame
Sync
S
Packet (1 to 44 Blocks)
Next Frame
(Optional)
Frame
S: Channel Status Symbol: +3 = Busy, +1 = Unknown, -1 = Unknown, -3 = Idle
Frame Sync:
-1 +1 -1 +1 -1 +3 -3 +3 -3 -1 +1 -3 +3 +3 -1 +1 -3 -3 +1 +3 -1 -3 +1 +3
Symbol Sync:
+3 +3 -3 -3 +3 +3 -3
-3 +3 +3 -3 -3 +3 +3 -3 -3 +3 +3 -3 -3
sent first
-3 -3 +3 +3
last
Figure 7: Over-Air Signal Format
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4-Level FSK Modem Data Pump
Page 16 of 50
MX929B PRELIMINARY INFORMATION
The 'Header' block is self-contained and includes its own checksum (CRC1). It would normally carry
information such as the address of the calling and called parties, the number of following blocks in the frame
(if any), and miscellaneous control information. The number of following blocks (if any) is required to allow the
Rx device software to expect the Last Block and interpret it as a Last Block rather than an Intermediate Block.
There is no other indicator to differentiate a Last Block and an Intermediate Block.
The 'Intermediate' block(s) contain only data, the checksum at the end of the 'Last' block (CRC2) also checks
the data in any preceding 'Intermediate' blocks.
Proprietary systems that do not use RD-LAP format may use the block structures provided by the MX929B
to build alternative frame formats more suited to the particular application. Some examples are shown in
Figure 7.
A
B
C
SYMBOL
SYNC
FRAME
SYNC
'HEADER' BLOCKS
SYMBOL
SYNC
FRAME
SYNC
'INTERMEDIATE' BLOCKS
SYMBOL
SYNC
FRAME
SYNC
'INTERMEDIATE' BLOCKS
'LAST'
BLOCK
Figure 8: Alternative Frame Structures
The MX929B performs the entire block formatting and de-formatting required to convert data between the C
binary form and the Over-Air form as shown in Figure 7.
4.5
The Programmer's View
To the programmer, the modem appears as 4 write only 8-bit registers, shadowed by 3 read only registers.
The individual registers are selected by the A0 and A1 chip inputs:
A1
A0
0
0
Data Buffer
Write to Modem
Data Buffer
Read from Modem
0
1
Command Register
Status Register
1
0
Control Register
Data Quality Register
1
1
Mode Register
not used
Note: There is a minimum time allowance between accesses of the modem's registers, see Section 6.1.4.
4.5.1
Data Block Buffer
This is a 12-byte read/write buffer used to transfer data (as opposed to command, status, mode, and data
quality or control information) between the modem and the host µC.
To the µC, the Data Block Buffer appears as a single 8-bit register. The modem ensures that sequential µC
reads or writes to the buffer are routed to the correct locations within the buffer.
The µC should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'.
The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in receive
mode, the modem will function correctly even if the received data is not read from the Data Buffer by the C.
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4.5.2
Page 17 of 50
MX929B PRELIMINARY INFORMATION
Command Register
Writing to this register tells the modem to perform a specific task as indicated by the TASK bits and modified
by the AQSC, AQLEV, CRC, and TXIMP bits.
Command Register
7
6
AQSC AQLEV
5
CRC
4
3
2
TXIMP Reserved
Set to '0'
1
0
TASK
When there is no action to perform, the modem will be in an 'idle' state. If the modem is in transmit mode, the
input to the Tx RRC filter will be connected to VBIAS. In receive mode, the modem will continue to measure
the received data quality and extract symbols from the received signal, supplying them to the de-interleave
buffer, but otherwise these received symbols are ignored.
4.5.2.1
Command Register B7: AQSC - Acquire Symbol Clock
This bit has no effect in transmit mode.
In receive mode, when a byte with the AQSC bit set to '1' is written to the Command Register, and TASK is not
set to RESET, it initiates an automatic sequence designed to achieve symbol timing synchronization with the
received signal as quickly as possible. This involves setting the Phase Locked Loop of the received bit timing
extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing synchronization is
achieved, until it reaches the 'normal' value set by the PLLBW bits of the Control Register.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be restarted every time a byte written to the Command Register has AQSC = '1'.
The use of the symbol clock acquisition sequence is described in Section 5.3.
4.5.2.2
Command Register B6: AQLEV - Acquire Receive Signal Levels
This bit has no effect in transmit mode.
In receive mode, when a byte with the AQLEV bit set to '1' is written to the Command Register and TASK is
not set to RESET, it initiates an automatic sequence designed to measure the amplitude and DC offset of the
received signal as rapidly as possible. This sequence involves setting the measurement circuits to respond
quickly at first, then gradually increasing their response time, therefore improving the measurement accuracy,
until the 'normal' value set by the LEVRES bits of the Control Register is reached.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be restarted every time a byte written to the Command Register has AQLEV = '1'.
The use of the level measurement acquisition sequence (AQLEV) is described in Section 5.3.
4.5.2.3
Command Register B5: CRC
This bit allows the user to select between two different initial states of the CRC0, CRC1 and CRC2 checksum
generators. When this bit is set to '1' the CRC generators are initialized to 'all zeros', as required by RD-LAP
systems. When this bit is set to ‘0’, the CRC generators are initialized to ‘all ones’ as required by CCITT X25
CRC based systems. It should always be set to '1' for RD-LAP compatibility. Other systems may set this bit
as required.
4.5.2.4
Command Register B4: TXIMP - Tx Level/Impulse Shape
This bit allows the user to choose between two transmit symbol waveform shapes as described in Section
4.7.
Note: This bit must be set correctly every time the Command Register is written to.
4.5.2.5
Command Register B3 - Reserved
This bit should always be set to '0'.
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4-Level FSK Modem Data Pump
4.5.2.6
Page 18 of 50
MX929B PRELIMINARY INFORMATION
Command Register B2, B1, B0: TASK
Operations such as transmitting or receiving a data block are treated by the modem as 'tasks' and are initiated
when the µC writes a byte to the Command Register with the TASK bits set to anything other than the 'NULL'
code.
The µC should not write a task (other than NULL or RESET) to the Command Register or write to or read from
the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is '0'.
Different tasks apply in receive and transmit modes.
When the modem is in transmit mode, all tasks other than NULL or RESET instruct the modem to transmit
data from the Data Buffer, formatting it as required. The µC should therefore wait until the BFREE (Buffer
Free) bit of the Status Register is '1', before writing the data to the Data Block Buffer, then it should write the
desired task to the Command Register. If more than 1 byte needs to be written to the Data Block Buffer, byte
number 0 of the block should be written first.
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE (Buffer Free) bit of the Status Register to '0'.
Take the data from the Data Block Buffer as quickly as it can - transferring it to the Interleave Buffer for
eventual transmission. This operation will start immediately if the modem is 'idle' (i.e. not transmitting
data from a previous task), otherwise it will be delayed until there is sufficient room in the Interleave
Buffer.
Once all of the data has been transferred from the Data Block Buffer, the modem will set the BFREE and
IRQ bits of the Status Register to '1', (causing the chip IRQ output to go low if the IRQEN bit of the Mode
Register has been set to '1') to tell the µC that it may write new data and the next task to the modem.
This lets the µC write the next task and its associated data to the modem while the modem is still transmitting
the data from its previous task.
Data from µC to Block Buffer
Task 1 data
Task 2 data
Task from µC to Command
Register
BFREE Bit of Status Register
IRQ Bit of Status Register
IRQ Output (IRQEN = '1')
TXOUT Signal
from Task 1
from Task 2
Figure 9: Transmit Task Overlapping
When the modem is in receive mode, the µC should wait until the BFREE bit of the Status Register is '1', then
write the desired task to the Command Register.
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE bit of the Status Register to '0'.
Wait until enough received symbols are in the De-interleave Buffer.
Decode them as needed and transfer the resulting binary data to the Data Block Buffer
Then the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the IRQ output
to go low if the IRQEN bit of the Mode Register has been set to '1') to tell the µC that it may read from the
Data Block Buffer and write the next task to the modem. If more than 1 byte is contained in the buffer,
byte number 0 of the data will be read out first.
In this way, the µC can read data and write a new task to the modem while the received symbols needed for
this new task are being received and stored in the De-interleave Buffer.
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4-Level FSK Modem Data Pump
Page 19 of 50
RXIN Signal
MX929B PRELIMINARY INFORMATION
for Task 1
for Task 2
IRQ Output (IRQEN = '1')
IRQ Bit of Status Register
BFREE Bit of Status Register
Task from µC to Command
Register
Task 1
Task 2
Data from Block Buffer to µC
Task 1 data
Figure 10: Receive Task Overlapping
Detailed timings for the various tasks are provide in Figure 11 and Figure 12.
MX929B Modem Tasks:
B2
B1
B0
0
0
0
NULL
0
0
1
SFP
Search for Frame Preamble
T24S
Transmit 24 symbols
0
1
0
RHB
Read Header Block
THB
Transmit Header Block
4.5.2.7
Receive Mode
Transmit Mode
NULL
0
1
1
RILB
Read Intermediate or Last Block
TIB
Transmit Intermediate Block
1
0
0
SFS
Search for Frame Sync
TLB
Transmit Last Block
1
0
1
R4S
Read 4 symbols
T4S
Transmit 4 symbols
1
1
0
RSID
Read Station ID
TSID
Transmit Station ID
1
1
1
RESET
Cancel any current action
RESET
Cancel any current action
NULL: No effect
This is provided so an AQSC or AQLEV command can be initiated without loading a new task.
4.5.2.8
SFP: Search for Frame Preamble
This task causes the modem to search the received signal for a valid 24-symbol Frame Preamble, consisting
of a 24-symbol Frame Sync sequence followed by Station ID Block which has a correct CRC0 checksum.
The task continues until a valid Frame Preamble has been found.
The search consists of four stages:
First the modem will attempt to match the incoming symbols against the Frame Synchronization pattern
to within the tolerance defined by the FSTOL bits of the Control Register.
Once a match has been found, the modem will read in the following 'S' symbol, place it in the SVAL bits
of the Status Register then set the SRDY bit to '1'. (The IRQ bit of the Status Register will also be set to
'1' at this time if the SSIEN bit of the Mode Register is '1').
The modem will then read the next 22 symbols as station ID data. They will be decoded and the CRC0
checked. If this is incorrect, the modem will resume the search, looking for a fresh Frame Sync pattern.
If the received CRC0 is correct, the following 'S' symbol will be read into the SVAL bits of the Status
Register and the SRDY, BFREE, and IRQ bits set to '1', the CRCERR bit cleared to '0', and the three
decoded Station ID bytes placed into the Data Block Buffer.
Upon detecting that the BFREE bit of the Status Register has gone to '1', the µC should read the three Station
ID bytes from the Data Block Buffer and then write the next task to the modem's Command Register.
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4-Level FSK Modem Data Pump
4.5.2.9
Page 20 of 50
MX929B PRELIMINARY INFORMATION
RHB: Read Header Block
This task causes the modem to read the next 69 symbols as a 'Header' Block. It will strip out the 'S' symbols
then de-interleave and decode the remaining 66 symbols, placing the resulting 10 data bytes and the 2
received CRC1 bytes into the Data Block Buffer and, when the task is complete, setting the BFREE and IRQ
bits of the Status Register to '1'to indicate that the µC may read the data from the Data Block Buffer and write
the next task to the modem's Command Register.
The CRCERR bit of the Status Register will be set to '1' or '0' depending on the validity of the received CRC1
checksum bytes.
As each of the three 'S' symbols of a block is received, the SVAL bits of the Status Register will be updated
and the SRDY bit set to '1'. (If the SSIEN bit of the Mode Register is '1', then the Status Register IRQ bit will
also be set to '1'.) Note that when the third 'S' symbol is received, the SRDY bit will be set to '1' coincidentally
with the BFREE bit also being set to '1'.
4.5.2.10 RILB: Read 'Intermediate' or 'Last' Block
This task causes the modem to read the next 69 symbols as an 'Intermediate' or 'Last' block. (The µC can tell
from the 'Header' block how many blocks are in the frame and therefore when to expect the 'Last' block).
In each case, it will strip out the three 'S' symbols, de-interleave, and decode the remaining 66 symbols and
place the resulting 12 bytes into the Data Block Buffer, setting the BFREE and IRQ bits of the Status Register
to '1' when the task is complete.
If an 'Intermediate' block is received, then the µC should read out all 12 bytes from the Data Block Buffer and
ignore the CRCERR bit of the Status Register. For a 'Last' block the µC need only read the first 8 bytes from
the Data Block Buffer, and the CRCERR bit in the Status Register will reflect the validity of the received CRC2
checksum.
As each of the three 'S' symbols of the block is received, the SVAL bits of the Status Register will be updated
and the SRDY bit set to '1'. (If the SSIEN bit of the Mode Register is '1', then the Status Register IRQ bit will
also be set to '1'.) Note that when the third 'S' symbol is received, the SRDY bit will be set to '1' coincidentally
with the BFREE bit also being set to '1'.
4.5.2.11 SFS: Search for Frame Sync
This task, which is intended for special test and channel monitoring purposes, performs the first two parts only
of a SFP task. It causes the modem to search the received signal for a 24-symbol sequence, which matches
the required Frame Synchronization pattern to within the tolerance defined by the FSTOL bits of the Mode
Register.
When a match is found the modem will read in the following 'S' symbol, then set the BFREE, IRQ, and SRDY
bits of the Status Register to '1' and update the SVAL bits. The µC may then write the next task to the
Command Register.
4.5.2.12 R4S: Read 4 Symbols
This task causes the modem to read the next 4 symbols and translate them directly (without de-interleaving or
FEC) to an 8-bit byte which is placed into the Data Block Buffer. The BFREE and IRQ bits of the Status
Register are then set to '1' to indicate that the µC may read the data byte from the Data Block Buffer and write
the next task to the Command Register.
This task is intended for special tests and channel monitoring - perhaps preceded by a SFS task.
Note: It is possible to construct message formats, which do not rely on the block formatting of the THB, TIB,
and TLB tasks. This can be accomplished by using T4S or T24S tasks to transmit and R4S to receive the
user's data. One should be aware, that the receive level and timing measurement circuits need to see a
reasonably 'random' distribution of all four possible symbols in the received signal to operate correctly.
Accordingly, binary data may benefit from scrambling before transmission if it is not reasonably 'random' to
start with.
4.5.2.13 RSID: Read Station ID
This task causes the modem to read in and decode the following 23 symbols as Station ID data followed by an
'S' symbol. It is similar to the last two parts of a SFP task except that it will not restart if the received CRC0 is
incorrect. It would normally follow a SFS task.
The three decoded bytes will be placed into the Data Block Buffer, and the CRCERR bit of the Status Register
set to '1' if the received CRC0 is incorrect, otherwise it will be cleared to '0'. The SVAL bits of the Status
Register will be updated and the BFREE, SRDY, and IRQ bits set to '1' to indicate that the C may read the
three received bytes from the Data Block buffer and write the next task to the modem's Command Register.
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4-Level FSK Modem Data Pump
Page 21 of 50
MX929B PRELIMINARY INFORMATION
4.5.2.14 T24S: Transmit 24 Symbols
This task, which is intended to facilitate the transmission of Symbol and Frame Sync patterns as well as
special test sequences, takes 6 bytes of data from the Data Block Buffer and transmits them as 24 4-level
symbols without any CRC, FEC, interleaving, or adding any 'S' symbols.
Byte 0 of the Data Block Buffer is sent first, byte 5 last.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1', indicating to the µC that it may write the data and command byte for the next task to
the modem.
The tables below show what data needs to be written to the Data Block Buffer to transmit the MX929B Symbol
and Frame Sync sequences:
'Symbol Sync'
Values written to Data Block Buffer
Symbols
Binary
Hex
+3
+3
-3
-3
Byte 0:
11110101
F5
+3
+3
-3
-3
Byte 1:
11110101
F5
+3
+3
-3
-3
Byte 2:
11110101
F5
+3
+3
-3
-3
Byte 3:
11110101
F5
+3
+3
-3
-3
Byte 4:
11110101
F5
-3
-3
+3
+3
Byte 5:
01011111
5F
'Frame Sync'
Values written to Data Block Buffer
Symbols
Binary
Hex
-1
+1
-1
+1
Byte 0:
00100010
22
-1
+3
-3
+3
Byte 1:
00110111
37
-3
-1
+1
-3
Byte 2:
01001001
49
+3
+3
-1
+1
Byte 3:
11110010
F2
-3
-3
+1
+3
Byte 4:
01011011
5B
-1
-3
+1
+3
Byte 5:
00011011
1B
4.5.2.15 THB: Transmit Header Block
This task takes 10 bytes of data (Address and Control) from the Data Block Buffer, calculates and appends
the 2-byte CRC1 checksum, translates the result to 4-level symbols (with FEC), interleaves the symbols, and
transmits the result as a formatted 'Header' Block, inserting 'S' symbols at 22 symbol intervals.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1'.
4.5.2.16 TIB: Transmit Intermediate Block
This task takes 12 bytes of data from the Data Block Buffer, updates the 4-byte CRC2 checksum for inclusion
in the 'Last' block, translates the 12 data bytes to 4-level symbols (with FEC), interleaves the symbols, and
transmits the result as a formatted 'Intermediate' Block, inserting 'S' symbols at 22-symbol intervals.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1'.
4.5.2.17 TLB: Transmit Last Block
This task takes 8 bytes of data from the Data Block Buffer, updates and appends the 4-byte CRC2 checksum,
translates the resulting 12 bytes to 4-level symbols (with FEC), interleaves the symbols, and transmits the
result as a formatted 'Last' Block, inserting 'S' symbols at 22-symbol intervals.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1'.
4.5.2.18 T4S: Transmit 4 Symbols
This task is similar to T24S but takes only one byte from the Data Block Buffer, transmitting it as four 4-level
symbols.
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4-Level FSK Modem Data Pump
Page 22 of 50
MX929B PRELIMINARY INFORMATION
4.5.2.19 TSID: Transmit Station ID
This task takes three ID bytes from the Data Block Buffer, calculates and appends the 6-bit CRC0 checksum,
translates the result to 4-level symbols (with FEC) and transmits the resulting 22 symbols preceded and
followed by 'S' symbols.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1'.
4.5.2.20 RESET: Stop any current action
This task takes effect immediately, and terminates any current action (task, AQSC or AQLEV) the modem
may be performing and sets the BFREE bit of the Status Register to '1', without setting the IRQ bit. It should
be used after VDD is applied first to set the modem into a known state.
Note: Due to delays in the RRC filter, it will take several symbol times for any change caused by RESET to
appear at the TXOUT pin.
4.5.2.21 Task Timing
The following table and figures describe the duration of tasks and timing sequences for Tx and Rx operation.
Task
t1 Modem in idle state. Time from writing first task to application of first Any
transmit bit to Tx RRC filter
Time
(symbol times)
1 to 2
t2 Time from application of first symbol of the task to the Tx RRC
filter until BFREE goes to a logic ‘1’
T24S
TSID
THB/TIB/TLB
T4S
5
6
16
0
t3 Time to transmit all symbols of the task
T24S/TSID
THB/TIB/TLB
T4S
24
69
4
t4 Max time allowed from BFREE going to a logic '1' (high) for next
task (and data) to be written to modem
T24S
TSID
THB/TIB/TLB
T4S
18
17
52
3
t5 Time to receive all symbols of task
SFS
SFP
RSID
RHB/RILB
R4S
25 (minimum)
48 (minimum)
23
69
4
t6 Maximum time between first symbol of task entering the deinterleave
circuit and the task being written to modem
SFS
SFP
RSID
RHB/RILB
R4S
21
21
15
51
3
t7 Maximum time from the last bit of the task entering the de interleave
circuit to BFREE going to a logic '1' (high)
Any
1
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4-Level FSK Modem Data Pump
Data to Data Block Buffer
Task to Command Register
Page 23 of 50
1
MX929B PRELIMINARY INFORMATION
3
2
1
2
t4
3
t4
t4
IBEMPTY Bit
BFREE Bit
t2
t2
t2
t3
t3
t3
t1
Symbols to RRC Filter
from Task 3
from Task 2
from Task 1
Modem Tx Output
Figure 11: Transmit Task Timing Diagram
Modem Rx Input
Symbols to De-Interleave
Circuit
for Task 1
for Task 2
for Task 3
t5
t5
t5
Data from Data Block Buffer
Task to Command Register
t6
1
t6
3
2
1
2
t7
t6
t7
3
t7
BFREE Bit
Figure 12: Receive Task Timing Diagram
4.5.2.22 RRC Filter Delay
The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the
input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times
through to the RRC filter in both transmit and receive modes, as illustrated below:
Delay from Tx Input
symbol to TXOUT
response.
Delay from Rx Input
(from FM discriminator)
to interpreted data in
internal buffer.
Tx Symbol to RRC Filter
Tx Symbol at TXOUT pin / Rx Symbol from FM discriminator
RX Symbol to De-Interleave Buffer
Symbol-times
Figure 13: RRC Low Pass Filter Delay
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4.5.3
Page 24 of 50
MX929B PRELIMINARY INFORMATION
Control Register
This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock
extraction, signal level measurement circuits, and the Frame Sync pattern recognition tolerance to inexact
matches.
Control Register
7
6
5
CKDIV
4.5.3.1
4
FSTOL
3
2
1
LEVRES
0
PLLBW
Control Register B7, B6: CKDIV - Clock Division Ratio
These bits control a frequency divider driven from the clock signal present at the XTAL pin, therefore
determining the nominal symbol rate. Because each symbol represents two bits, bit rates are 2x the symbol
rates. The table below shows how symbol rates of 2400/4800/9600 symbols/sec (4800/9600/19200bps) may
be obtained from common Xtal frequencies:
Xtal Frequency (MHz)
2.4576
4.9152
9.8304
Division Ratio:
Symbol Rate (symbols/sec) / Bit Rate (bps)
Xtal Frequency/Symbol Rate
512
4800/9600
9600/19200
B7
B6
0
0
0
1
1024
1
0
2048
1
1
4096
2400/4800
4800/9600
9600/19200
2400/4800
4800/9600
2400/4800
Note: Device operation is not guaranteed below 2400 symbols/sec (4800bps) or above 9600
symbols/sec (19200bps).
4.5.3.2
Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches
These two bits have no effect in transmit mode. In receive mode, they define the maximum number of
mismatches allowed during a search for the Frame Sync pattern:
B5
B4
Mismatches allowed
0
0
0
0
1
2
1
0
4
1
1
6
Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus if the symbol
'+1' were expected, then received symbol values of '+3' and '-1' would count as 1 mismatch, a received
symbol value of '-3' would count as 2 mismatches. A setting of '4 mismatches' is recommended for
normal use.
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4.5.3.3
Page 25 of 50
MX929B PRELIMINARY INFORMATION
Control Register B3, B2: LEVRES - Level Measurement Modes
These two bits have no effect in transmit mode. In receive mode they set the 'normal' or 'steady state'
operating mode of the Rx signal amplitude and DC offset measuring and tracking circuits. These circuits
analyze the Rx signal envelope and charge the DOC1 and DOC2 capacitors to 'store' signal maximum and
minimum references that are used in the data reception process. This setting is temporarily overridden during
the automatic sequencing triggered by an AQLEV command when level is initially being acquired as described
in Section 5.3.
B3
B2
Mode
0
0
Hold
0
1
Level Track
1
0
Lossy Peak Detect
1
1
Slow Peak Detect
In normal use the LEVRES bits should be set to '0 1' (Level Track). The other modes are intended for special
purposes, for device testing, or are invoked automatically during an AQLEV sequence.
In 'Slow Peak Detect' modes, the positive and negative excursions of the received signal (after filtering) are
measured by peak rectifiers driving the DOC1 and DOC2 capacitors to establish the amplitude of the signal
and any DC offset with regards to VBIAS. This mode provides good overall performance, particularly when
acquiring level information at the start of a received message, but does not work as well with certain long
sequences of repeated data byte values. It is also susceptible to large amplitude noise spikes, which can be
caused by deep fades.
The 'Lossy Peak Detect' mode is similar to 'Slow Peak Detect' but the capacitor discharge time constant is
much shorter so this mode is not suitable for normal data reception and is only used within part of the
automatic AQLEV acquisition sequence.
In 'Level Track' mode the DOC capacitor voltages are slowly adjusted by the MX929B in such a way as to
minimize the average errors seen in the received signal. This mode provides the best overall performance,
being much more accurate than 'Slow Peak Detect' when receiving large amplitude noise spikes on long
sequences of repeated data byte values. It does, however, depend on the measured levels and timing being
approximately correct. If either of these is significantly wrong then the correction algorithm used by the 'Level
Track' mode can actually drive the voltages on the DOC capacitors away from their optimum levels. For this
reason, the automatic AQLEV acquisition sequence (see Section 5.3) forces the level measuring circuits into
'Slow Peak Detect' mode until a Frame Sync pattern has been found.
In 'HOLD' mode the DOC Capacitors are isolated from the charging and discharging circuits, allowing their
voltages to remain constant.
4.5.3.4
Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes
These two bits have no effect in transmit mode. In receive mode, they set the 'normal' or 'steady state'
bandwidth of the Rx clock extraction Phase Locked Loop circuit. The PLL circuit synchronizes itself with the
Rx Signal to develop a local clock signal used in the data clock recovery process. This setting will be
temporarily overridden during the automatic sequencing of an AQSC command when Rx clock extraction
circuits are initially being trained as described in
Section 5.3.
B1
B0
PLL Mode
0
0
Hold
0
1
Narrow Bandwidth
1
0
Medium Bandwidth
1
1
Wide Bandwidth
The normal setting for the PLLBW bits should be 'Medium Bandwidth' when the received symbol rate and the
frequency of the receiving modem's crystal are both within 100ppm of nominal, except at the start of a
symbol clock acquisition sequence (AQSC) when 'Wide Bandwidth' should be selected as described in
Section 5.3.
If the received symbol rate and the crystal frequency are both within 20ppm of nominal then selection of the
'Narrow Bandwidth' setting will provide better performance especially through fades or noise bursts which may
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4-Level FSK Modem Data Pump
Page 26 of 50
MX929B PRELIMINARY INFORMATION
otherwise pull the PLL away from its optimum timing. In this case however; it is recommended that the
PLLBW bits only be set to 'Narrow Bandwidth' after the modem has been running in 'Medium Bandwidth'
mode for about 200 symbol times to ensure accurate lock has first been achieved.
The 'Hold' setting disables the feedback loop of the PLL which continues to run at a rate determined only by
the actual crystal frequency and the setting of the Control Register CKDIV bits, not the PLL's operating
frequency immediately prior to the 'Hold' setting.
4.5.4
Mode Register
The contents of this 8-bit write only register control the basic operating modes of the modem:
Mode Register
7
6
5
IRQEN INVSYM Tx/Rx
4.5.4.1
4
3
2
RXEYE PSAVE SSIEN
1
0
SSYM
Mode Register B7: IRQEN - IRQ Output Enable
When this bit is set to '1', the IRQ chip output pin is pulled low (VSS) given the IRQ bit of the Status Register
is a '1'.
4.5.4.2
Mode Register B6: INVSYM - Invert Symbols
This bit controls the polarity of the transmitted and received symbol voltages.
B6
Symbol
Signal at TXOUT
Signal at RXAMPOUT
0
'+3'
Above VBIAS
Below VBIAS
'-3'
Below VBIAS
Above VBIAS
'+3'
Below VBIAS
Above VBIAS
'-3'
Above VBIAS
Below VBIAS
1
Note: B6 must be normally set to the same value in Tx and Rx devices for successful communication between
them.
4.5.4.3
Mode Register B5: TX/RX - Tx/Rx Mode
Setting this bit to '1' places the modem into the Transmit mode, clearing it to '0' puts the modem into the
Receive mode.
Note: Changing between receive and transmit modes will cancel any current task.
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4.5.4.4
Page 27 of 50
MX929B PRELIMINARY INFORMATION
Mode Register B4: RXEYE - Show Rx Eye
This bit should normally be set to '0'. Setting it to '1' when the modem is in receive mode configures the
modem for a special test mode, in which the input of the Tx output buffer is connected to the Rx Symbol/Clock
extraction circuit at a point which carries the equalized receive signal. This may be monitored with an
oscilloscope (at the TXOUT pin itself), to assess the quality of the complete radio channel including the Tx and
Rx modem filters, the Tx modulator and the Rx IF filters, and FM demodulator.
This mode is provided because observation of the direct discriminator output of a root raised cosine Tx filtered
signal (before Rx equalization) is not very recognizable so it is generally not useful.
The resulting eye diagram (for reasonably random data) should ideally be as shown Figure 14, with 4 distinct
and equally spaced level crossing points.
Figure 14: Ideal 'RXEYE' Signal
4.5.4.5
Mode Register B3: PSAVE - Powersave
When this bit is a ‘1’, the modem will be in a ‘powersave’ mode in which the internal filters, the Rx Symbol and
Clock extraction circuits, and the Tx output buffer will be disabled. The TXOUT pin will be connected to VBIAS
through a high value internal resistance. The Xtal clock oscillator, Rx input amplifier and the C interface logic
will continue to operate.
Setting the PSAVE bit to ‘0’ restores power to all of the chip circuitry.
Note: The internal filters, and therefore the TXOUT pin in transmit mode, will take approximately 20 symboltimes to settle after the PSAVE bit has gone from ‘1’ to ‘0’.
4.5.4.6
Mode Register B2: SSIEN - 'S' Symbol IRQ Enable
In receive mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1' whenever a new
'S' symbol has been received. (The SRDY bit of the Status Register will also be set to '1' at the same time,
and the SVAL bits updated to reflect the received 'S' symbol.)
In transmit mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1' whenever a 'S'
symbol has been transmitted. (The SRDY bit of the Status Register will also be set to '1' at the same time.)
4.5.4.7
Mode Register B1, B0: SSYM - 'S' Symbol To Be Transmitted
In transmit mode, these two bits define the next 'S' symbol to be transmitted. These bits have no effect in
receive mode.
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4.5.5
Page 28 of 50
MX929B PRELIMINARY INFORMATION
Status Register
This register may be read by the C to determine the current state of the modem.
Status Register
7
IRQ
4.5.5.1
6
5
4
3
2
CRCERR
IBEMPTY
BFREE
DIBOVF
SRDY
1
0
SVAL
Status Register B7: IRQ - Interrupt Request
This bit is set to '1' by:
The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET task or by a
change to the Mode Register TX / RX or PSAVE bits
or
The Status Register IBEMPTY bit going from '0' to '1', unless this is caused by a RESET task or by
changing the Mode Register TX / RX or PSAVE bits.
or
The Status Register DIBOVF bit going from '0' to '1'.
or
The Status Register SRDY bit being set to '1' (due to a 'S' symbol being received or transmitted) if the
Mode Register SSIEN bit is '1'.
The IRQ bit is cleared to '0' immediately after a read of the Status Register.
If the IRQEN bit of the Mode Register is '1', then the chip IRQ output will be pulled low (VSS) when the IRQ bit
is set to '1', and will go high impedance when the Status Register is read.
4.5.5.2
Status Register B6: BFREE - Data Block Buffer Free
This bit reflects the availability of the Data Block Buffer and is cleared to '0' when a task other than NULL or
RESET is written to the Command Register.
In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by the modem
when the modem is ready for the µC to write new data to the Data Block Buffer and the next task to the
Command Register.
In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the modem when
it has completed a task and any data associated with that task has been placed into the Data Block Buffer.
The µC may then read that data and write the next task to the Command Register.
The BFREE bit is also set to '1' - but without setting the IRQ bit - by a RESET task or when the Mode Register
TX / RX or PSAVE bits are changed.
4.5.5.3
Status Register B5: IBEMPTY - Interleave Buffer Empty
In transmit mode, this bit will be set to '1' - also setting the IRQ bit - when less than two symbols remain in the
Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to avoid a gap
in the transmit output signal.
The bit is also set to '1' by a RESET task or by a change of the Mode Register TX / RX or PSAVE bits, but in
these cases the IRQ bit will not be set.
The bit is cleared to '0' within one symbol time after a task other than NULL or RESET is written to the
Command Register.
Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid-level (halfway between
'+1' and '-1') signal will be sent to the RRC filter.
In receive mode this bit will be '0'.
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4-Level FSK Modem Data Pump
4.5.5.4
Page 29 of 50
MX929B PRELIMINARY INFORMATION
Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB, RSID, or R4S task is
written to the Command Register too late to allow continuous reception.
The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the
Command Register or by changing the TX / RX or PSAVE bits of the Mode Register.
In transmit mode this bit is '0'.
4.5.5.5
Status Register B3: CRCERR - CRC Checksum Error
In receive mode, this bit will be updated at the end of a SFP, RHB, RILB, or RSID task to reflect the result of
the receive CRC check. '0' indicates that the CRC was received correctly, '1' indicates an error.
Note: This bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is
received.
The bit is cleared to '0' by a RESET task or by changing the TX / RX , or PSAVE bits of the Mode Register. In
transmit mode this bit is '0'.
4.5.5.6
Status Register B2: 'S' Symbol Ready
In receive mode, this bit is set to '1' whenever an 'S' symbol has been received. The C may then read the
value of the symbol from the SVAL field of the Status Register. In transmit mode, this bit is set to '1' whenever
an 'S' symbol has been transmitted.
The bit is cleared to '0' immediately after a read of the Status Register, by a RESET task or by changing the
TX / RX or PSAVE bits of the Mode Register.
4.5.5.7
Status Register B1, B0: SVAL - Received 'S' Symbol Value
In receive mode, these two bits reflect the value of the latest received 'S' symbol. In transmit mode, these two
bits
will be '0'.
4.5.6
Data Quality Register
In receive mode, the MX929B continually measures the 'quality' of the received signal, by comparing the
actual received waveform over the previous 64 symbol times against an internally generated 'ideal' 4-level
FSK baseband signal.
The result is placed into bits 3-7 of the Data Quality Register for the µC to read at any time, bits 0-2 being
always set to '0'. Figure 15 shows how the value (0-255) read from the Data Quality Register varies with
received signal-to-noise ratio:
250
200
150
DQ
100
50
0
8
9
10
11
12
13
14
15
16
S/N dB (Noise in 2 x Symbol Rate Bandwidth)
Figure 15: Typical Data Quality Reading vs S/N
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Page 30 of 50
MX929B PRELIMINARY INFORMATION
The Data Quality readings are only valid when the modem has successfully acquired signal level and timing
lock for at least 64 symbol times. It is invalid when an AQSC or AQLEV sequence is being performed or when
the LEVRES setting is 'Lossy Peak Detect'. A low reading will be obtained if the PLLBW bits are set to 'Wide'
or if the received signal waveform is distorted in any significant way.
Section 5.6 describes how monitoring the Data Quality reading can help improve the overall system
performance in some applications.
4.6
CRC, FEC and Interleaving
4.6.1
Cyclic Redundancy Codes
4.6.1.1
CRC0
This is a six-bit CRC check code used in the Station ID Block. It is calculated by the modem from the first 24
bits of the block (Bytes 0, 1, and 2) as follows:
The 24 bits are considered as the coefficients of a polynomial M(x) of degree 23 such that the MSB bit (7) of
23
byte 0 is the coefficient of x , and bit 0 of byte 2 is the coefficient of x0.
The polynomial F(x) of degree 5 is calculated as being the remainder of the modulo-2 division.
x 6 M( x )
( x 6 x 4 x 3 1)
5
4
3
2
1
0
The polynomial x + x + x + x + x + x is added (modulo-2) to F(x).
5
The coefficients of F(x) are placed in the 6-bit CRC0 field, such that the coefficient of x corresponds to the
MSB of CRC0
4.6.1.2
CRC1
This is a sixteen-bit CRC check code contained in bytes 10 and 11 of the Header Block, which provides error
detection coverage for the Header Block of a message. It is calculated by the modem from the first 80 bits of
the Header Block (Bytes 0 to 9 inclusive) using the generator polynomial:
x16 + x12 + x5 + 1
4.6.1.3
CRC2
This is a thirty-two-bit CRC check code contained in bytes 8 to 11 of the 'Last' Block, which provides error
detection coverage for the combined Intermediate Blocks and Last Block of a message. It is calculated by the
modem from all of the data and pad bytes in the Intermediate Blocks and in the first 8 bytes of the Last Block
using the generator polynomial:
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
Note: In receive mode the CRC2 checksum circuits are initialized on completion of any task other than NULL
or RILB. In transmit mode the CRC2 checksum circuits are initialized on completion of any task other
than NULL, TIB, or TLB.
Command Register bit B5 (CRC) allows the user to select between two different forms of the CRC0,
CRC1 and CRC2 checksums. When this bit is set to ‘1’ the CRC generators are initialized to ‘all zeros’,
as required by RD-LAP systems. When this bit is set to '0', the CRC generators are initialized to 'all
ones' for calculations such as CCITT X25 based systems. It should always be set to ‘1’ for RD-LAP
compatibility, other systems may set this bit as required.
4.6.1.4
Forward Error Correction
In transmit mode, the MX929B uses a Trellis Encoder to translate the 96 bits (12 bytes) of a 'Header',
'Intermediate', 'Last' Block, into a 66 symbol (132 bits) sequence which includes FEC information. Station ID
Blocks (30 bits) are translated into a 22 symbol (44 bit) sequence which includes FEC information.
In receive mode, the MX929B decodes the received 22 or 66 symbols of a block into 30 or 96 bits of binary
data using a 'Soft Decision' Viterbi algorithm to perform decoding and error correction.
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4.6.1.5
Page 31 of 50
MX929B PRELIMINARY INFORMATION
Interleaving
The 66 symbols of a 'Header', 'Intermediate' or 'Last' block are interleaved by the modem before transmission
(and before the ‘S’ symbols are added) to provide protection against the effects of noise bursts and short
fades. The 22 symbols of a ‘Station ID’ Block are not interleaved.
In receive mode, the MX929B strips out the 'S' symbols and then de-interleaves the received symbols. FEC
and decoding follow.
4.7
Transmitted Symbol Shape
Bit 4 of the Command Register (TXIMP) selects the transmit baseband signal and the receive signal
equalization as follows:
If the TXIMP bit is '0', then the transmit baseband signal is generated by feeding full-symbol-time-width 4-level
symbols into the RRC lowpass filter and the receive signal equalization is optimized for this type of signal.
With this setting, the MX929B is compatible with the MX929A device, another member of the MX929 device
family.
If the TXIMP bit is set to '1,' impulses, rather than full-symbol-time-width symbols are fed into the RRC filter
when in TX mode and the receive signal equalization is suitably adjusted in RX mode.
TXIMP = 0
TXIMP = 1
+3
+3
+1
+1
-1
-1
-3
-3
1 symbol
time
1 symbol
time
Figure 16: Input Signal to RRC Filter in Tx Mode for TXIMP = 0 and 1
Figure 17: Tx Signal Eye TXIMP = 0
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4-Level FSK Modem Data Pump
Page 32 of 50
MX929B PRELIMINARY INFORMATION
Figure 18: Tx Signal Eye TXIMP = 1
Note: Setting TXIMP to '1' affects the Tx output signal level as shown in Section 6.1 and the table below.
TXIMP = 0
TXIMP = 1
Nominal Voltage difference between continuous '+3' and
continuous '-3' symbol outputs.
0.157VDD
0.157VDD
Nominal VP-P for continuous '+3 +3 -3 -3…" symbol pattern.
0.20VDD
0.22VDD
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4-Level FSK Modem Data Pump
Page 33 of 50
MX929B PRELIMINARY INFORMATION
5. Application
5.1
Transmit Frame Example
The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one
each Header, Intermediate and Last blocks are provided below:
1. Ensure that the Control Register has been loaded with a suitable CKDIV value, that the IRQEN and
TX / RX bits of the Mode Register are '1', the RXEYE, PSAVE, and SSIEN bits are '0', and the INVSYM bit
is set appropriately.
2. Read the Status Register to ensure that the BFREE bit is '1', then write 6 Symbol Sync bytes (a preamble)
to the Data Block Buffer and a T24S task to the Command Register.
3. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the IBEMPTY bit should be '0'.
4. Write the 6 byte Frame Sync to the Data Block Buffer and a T24S task to the Command Register.
5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the IBEMPTY bit should be '0'.
6. Write 3 Station ID bytes to the Data Block Buffer and a TSID task to the Command Register.
7. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the IBEMPTY bit should be '0'.
8. Write 10 Header Block bytes to the Data Block Buffer and a THB task to the Command Register.
9. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the IBEMPTY bit should be '0'.
10. Write 12 Intermediate Block bytes to the Data Block Buffer and a TIB task to the Command Register.
11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the IBEMPTY bit should be '0'.
12. Write 8 Last Block bytes to the Data Block Buffer and a TLB task to the Command Register.
13. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be ‘1’ and
the IBEMPTY bit should be ‘0’.
14. Wait for another interrupt from the modem, read the Status Register; the IRQ, BFREE and IBEMPTY bits
should be '1'.
Notes:
1. The final symbol of the frame will start to appear approximately 2 symbol times after the Status Register
IBEMPTY bit goes to '1'; a further 16 symbol times should be allowed for the symbol to pass completely
through the RRC filter.
2. The SSYM bits of the Mode Register may be altered at any time to change the transmitted ‘S’ symbols. If
a timing reference is required, then setting the Mode Register SSIEN bit to ‘1’ will cause a C interrupt
after every ‘S’ symbol transmitted, in which case the C will have to distinguish between interrupts caused
by the BFREE bit going to ‘1’, and those caused by the SRDY bit being set to ‘1’.
3. Figure 19 and Figure 20 illustrate the host C routines needed to send a single Frame consisting of
Symbol and Frame Sync patterns, a Station ID Block, a Header block, and any number of Intermediate
blocks and one Last Block. It is assumed that the Tx Interrupt Service Routine Figure 20 is called every
time the MX929B IRQ output line goes low.
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4-Level FSK Modem Data Pump
Page 34 of 50
MX929B PRELIMINARY INFORMATION
START
Ensure that the Control Register
has been loaded with
a suitable CKDIV value
Set µC variable 'IBLOCKS'
to the number of Intermediate blocks
to be transmitted
Ensure that the Mode Register
IRQEN, PSAVE, RXEYE and SSIEN bits are '0',
the TX/RX bit is '1'
and the INVSYM and SSYM bits are
set appropriately
Set µC variable 'STATE' to 0
Set the Mode Register IRQEN bit to '1'
Write a RESET task to the Command Register
Enable µC's MX929B Tx Interrupt Service Routine
Read the Status Register
Write 6 bytes of Symbol Sync
pattern to the Data Buffer
BFREE bit = 1 ?
Yes
Write a T24S task to the Command Register
No
Note: during this time the µC may
perform other functions, as the
µC variable 'STATE' is updated
by the interrupt service routine
Yes
'STATE' < 6 ?
No
Disable µC's MX929B Tx Interrupt Service Routine
Set the Mode Register IRQEN bit to '0'
No
'STATE' = 6 ?
Yes
END
with error
END
Figure 19: Transmit Frame Example Flowchart, Main Program
Notes:
1. The RESET command in Figure 19 and the practice of disabling the MX929B’s IRQ output when not
needed are not essential but can eliminate problems during debugging and if errors occur in operation
2. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command
Register.
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4-Level FSK Modem Data Pump
Page 35 of 50
MX929B PRELIMINARY INFORMATION
Value of µC variable 'STATE' on entry to IRQ routine
and corresponding MX929B's actions:
0: Symbol Sync pattern being transmitted,
load Frame Sync pattern & T24S task.
1: Frame Sync pattern being transmitted,
load Station ID bytes and TSID task.
2: Station ID Block being transmitted,
load Header Block bytes &THB task.
3: Header or Intermediate
Block being trransmitted
.
load Intermediate or Last Block bytes & TIB or TLB task.
4: Last block being transmitted,
ignore this interrupt.
5: Waiting for end of transmission,
finish on interrupt with IBEMPTY bit set.
START
( IRQ line goes low )
Read Status Register
RETURN
No
( Not MX929B IRQ )
IRQ bit = 1 ?
Yes
E
No
BFREE bit = 1 ?
Yes
Yes
'STATE' = 5 ?
No
E
Yes
No
E
IBEMPTY bit = 1 ?
Yes
IBEMPTY bit = 1 ?
No
E
Write 6 bytes Frame Sync
pattern to the Data Buffer
then write a T24S task to
the Command Register
Yes
'STATE' = 0 ?
No
Set µC variable 'STATE' to 9
Write 3 Station ID bytes
to the Data Buffer
then write a TSID task to
the Command Register
Yes
'STATE' = 1 ?
RETURN
( Error )
No
Write 10 Header Block
data bytes to the Data Buffer
then write a THB task to
the Command Register
Yes
'STATE' = 2 ?
No
No
'STATE' = 3 ?
Yes
No
E
Write 12 Intermediate Block
data bytes to the Data Buffer
then write a TIB task to
the Command Register
No
'IBLOCKS' = 0 ?
Yes
'STATE' = 4 ?
Yes
Write 8 Last Block
data bytes to the Data Buffer
then write a TLB task to
the Command Register
Decrement µC variable
'IBLOCKS'
Increment µC variable
'STATE'
RETURN
RETURN
Figure 20: Tx Interrupt Service Routine
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4-Level FSK Modem Data Pump
5.2
Page 36 of 50
MX929B PRELIMINARY INFORMATION
Receive Frame Example
The operations needed to receive a single Frame consisting of Symbol and Frame Sync sequences, Station
ID Block, and one each Header, Intermediate and Last blocks are shown below;
1. Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVRES and PLLBW
values, and that the IRQEN bit of the Mode Register is '1', the TX / RX , RXEYE, PSAVE, and SSIEN bits
are '0', and the INVSYM bit is set appropriately.
2. Wait until the received carrier has been present for at least 8 symbol times (see Section 5.3).
3. Read the Status Register to ensure that the BFREE bit is '1'.
4. Write a byte containing a SFP task and with the AQSC and AQLEV bits set to '1' to the Command
Register.
5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the CRCERR and DIBOVF bits should be '0'.
6. Read 3 Station ID bytes from the Data Block Buffer.
7. Write a RHB task to the Command Register.
8. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the DIBOVF bit '0'.
9. Check that the CRCERR bit of the Status Register is ‘0’ and read 10 Header Block bytes from the Data
Block Buffer.
10. Write a RILB task to the Command Register.
11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and
the DIBOVF bit '0'.
12. Read 12 Intermediate Block bytes from the Data Block Buffer.
13. Write a RILB task to the Command Register.
14. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be ‘1’ and
the DIBOVF bit ‘0’.
15. Check that the CRCERR bit of the Status Register is '0' and read the 8 Last Block bytes from the Data
Buffer.
Note:
1. The value of the latest ‘S’ symbol received will be contained in the SVAL bits each time the Status
Register is read. If desired, the Mode Register SSIEN bit may be set to ‘1’, which will cause a C interrupt
after every ‘S’ symbol received, in which case the C will have to distinguish between interrupts caused by
the BFREE bit going to ’1’ and those caused by SRDY bit being set to ‘1’.
2. Figure 21 and Figure 22 illustrate the host C routines needed to receive a single Frame consisting of
Symbol and Frame Sync patterns, a Station ID Block, a Header Block, any number of Intermediate blocks
and one Last block. It is assumed that the Rx Interrupt Service Routine Figure 22 is called every time the
MX929B’s IRQ output goes low.
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4-Level FSK Modem Data Pump
Page 37 of 50
MX929B PRELIMINARY INFORMATION
START
Ensure that the Control Register
has been loaded with suitable
CKDIV, FSTOL, LEVRES and PLLBW values
Wait until the received carrier has been present
for at least 8 symbol times
Ensure that the Mode Register IRQEN,
PSAVE, RXEYE, TX/RX, and SSIEN bits are '0',
and the INVSYM bit is set appropriately
Set µC variable 'STATE' to 0
Write a RESET task to the Command Register
Set the Mode Register IRQEN bit to '1'
Read the Status Register
Enable µC's MX929B Rx Interrupt Service Routine
BFREE bit = 1 ?
Yes
Write a SFP task to the Command Register
with the AQSC and AQLEV bits set to '1'
No
Note: during this time the µC may
perform other functions, as the
µC variable 'STATE' is updated
by the interrupt service routine
Yes
'STATE' < 4 ?
No
Disable µC's MX929B Rx Interrupt Service Routine
Set the Mode Register IRQEN bit to '0'
No
'STATE' = 4 ?
Yes
END
with error
END
Figure 21: Receive Frame Example Flowchart, Main Program
Notes
1. The RESET command in Figure 21 and the practice of disabling the MX929B’s IRQ output when not
needed are not essential but can eliminate problems during debugging and if errors occur in operation.
2. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command
Register.
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4-Level FSK Modem Data Pump
Page 38 of 50
START
Value of µC variable 'STATE' on entry to IRQ routine
and corresponding MX929B's actions:
( IRQ line goes low )
0 : Frame Sync has been recognized
and Station ID block received,
read out data and load RHB task.
1 : Header block has been received,
read out data and load RILB task.
2 : Intermediate block has been received,
read out data and load RILB task.
Read Status Register
RETURN
No
IRQ bit = 1 ?
MX929B PRELIMINARY INFORMATION
( Not MX929B IRQ )
3 : Last block has been received,
read out data and finish.
Yes
BFREE bit = 1 ?
No
E
Yes
DIBOVF bit = 0 ?
No
E
Yes
No
'STATE' = 2 ?
Yes
CRCERR bit = 0 ?
Read 12 Intermediate Block
bytes from the Data Buffer
then write a RILB task to
the Command Register
No
E
Yes
Read 3 Station ID bytes
from the Data Buffer
then write a RHB task to
the Command Register
Yes
'STATE' = 0 ?
Decrement µC variable
'IBLOCKS'
No
Read 10 Header block bytes
from the Data Buffer then
write a RILB task to the
Command Register
Yes
'STATE' = 1 ?
No
Set µC variable 'IBLOCKS'
to the number of Intermediate
Blocks to be received
Yes
'STATE' = 3 ?
Read 8 Last Block data bytes
from the Data Buffer.
No
No
'IBLOCKS' = 0 ?
E
Yes
Set µC variable 'STATE' to 3
RETURN
Increment µC variable
'STATE'
Set µC variable 'STATE' to 9
RETURN
RETURN
( Error )
Figure 22: Rx Interrupt Service routine
Note: This routine assumes that the number of Intermediate blocks in the Frame is contained within the
Header Block Data.
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4-Level FSK Modem Data Pump
5.3
5.3.1
Page 39 of 50
MX929B PRELIMINARY INFORMATION
Clock Extraction and Level Measurement Systems
Supported Types of Systems
The MX929B is intended for use in systems where:
1. The Symbol Sync pattern is transmitted immediately on start-up of the transmitter, before the first Frame
Sync pattern (see Figure 23).
2. A Base Station may remain powered up indefinitely, transmitting concatenated Frames with or without
intervening Symbol Sync patterns (each Frame starting with the Frame Sync pattern and symbol timing
being maintained from one Frame to the next).
3. A receiving modem may be switched onto a channel before the distant transmitter has started up or may
be switched onto a channel where the transmitting station is already sending concatenated Frames.
5.3.2
Clock and Level Acquisition Procedures with RF Carrier Detect
When the receiving modem is enabled or switched onto a channel, it needs to establish the received symbol
levels, clock timing, and look for a Frame Sync pattern in the incoming signal. This is best done by the
following procedure:
1. Ensure that the Control Register's PLLBW bits are set to 'Wide' and the LEVRES bits to 'Level Track'.
2. Wait until a received carrier has been present for 8 symbol times. This 8-symbol delay gives time for the
received signal to propagate through the modem's RRC filter. An 'RF received 8 symbol times' qualifying
function can be included in a radio's carrier detect circuitry to take this into account.
3. Write a SFS or SFP task to the Command Register with the AQSC and the AQLEV bits set to '1'.
4. When the modem interrupts to signal that it has recognized a Frame Sync pattern (or completed the SFP
task) then change the PLLBW bits to 'Medium'.
Once the receiving modem has achieved level and symbol timing synchronization with a particular channel as evidenced by recognition of a Frame Sync pattern - then subsequent concatenated Frames can be read by
simply issuing SFS or SFP tasks at appropriate times, keeping the ASQSC and AQLEV bits at zero, and the
PLLBW and LEVRES bits at their current 'Medium' and 'Level Track' settings, respectively.
Noise
Frame Sync
Symbol Sync
Rest of Frame
Rx Signal from
FM discriminator
to Modem
8-Symbol delay
Set AQSC and AQLEV bits
to start Acquisition sequences
Level Measurement and Clock
Extraction Circuits
Increasing accuracy and lengthening response times
Figure 23: Acquisition Sequence Timing
5.3.3
Clock and Level Acquisition Procedure without RF Carrier Detect
It is also possible to use the modem in a non-standard system where there is an indeterminate delay between
the RF transmitter turn on time and the transmission moment of the Symbol Sync pattern, or where a receive
carrier detect signal is not available to the controlling C, or where the transmitting terminal can send separate
unsynchronized Frames. In these cases, each Frame should be preceded by a Symbol Sync pattern, which
should be extended to about 100 symbols, and the procedure provided in Section 5.3.2.
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4-Level FSK Modem Data Pump
5.3.4
Page 40 of 50
MX929B PRELIMINARY INFORMATION
Automatic Acquisition Functions
Setting the AQSC and AQLEV bits to '1' triggers the modem's automatic Symbol Clock Extraction and Level
Measurement acquisition sequences, which are designed to measure the received symbol timing, amplitude,
and DC offset as quickly as possible before switching to accurate - but slower - measurement modes. These
acquisition sequences act very quickly if triggered at the start of a received Symbol Sync pattern (as shown in
Figure 23), but will still function correctly, although more slowly, if started any time during a normal Frame as
when the receiver is switched onto a channel where the transmitter is operating continuously.
The automatic AQLEV Level Measurement acquisition sequence starts with the level measurement circuits
being put into 'Clamp' Mode for one symbol time to quickly set the voltages on the DOC pins to approximately
correct levels. The level measurement circuits are then automatically set to 'Lossy Peak Detect' mode for 15
symbol times, then 'Slow Peak Detect' until a received Frame Sync pattern is recognized, after which the
automatic sequence ends and the level measurement circuit mode reverts to the mode set by the LEVRES
bits of the Control Register (normally 'Level Track').
The peak detectors used in both 'Slow' and 'Lossy Peak Detect' modes include additional low pass filtering of
the received signal. This greatly reduces the effect of pattern noise on the reference voltages held on the
external DOC capacitors but means that pairs of '+3' (and '-3') symbols need to be received to establish the
correct levels. Two pairs of '+3' and two pairs of '-3' symbols received after the start of an AQLEV sequence
are sufficient to correctly set the levels on the DOC capacitors.
The automatic AQSC Symbol Clock acquisition sequence sets the PLL to 'Extra Wide Bandwidth' mode for 16
symbol times (this mode is not one of those which can be selected by the Control Register PLLBW bits) then
changes to 'Wide' bandwidth. After 45 symbol times, the PLL mode will revert to that set by the Control
Register PLLBW bits.
5.4
AC Coupling
For a practical circuit, ac coupling between the modem's transmit output to the frequency modulator and
between the receiver's frequency discriminator and the receive input of the modem may be desired. There
are, however, two issues which deserve consideration:
1. AC coupling of the signal degrades the Bit Error Rate performance of the modem. The following graph
illustrates the typical bit error rates at 4800 symbols/sec (9600bps) without FEC for reasonably random data
with differing degrees of AC coupling:
1.E-01
1.E-02
BER
1.E-03
Tx & Rx DC coupled
Tx 5Hz, RxDC
Tx 5Hz, Rx5Hz
Tx 5Hz, Rx10Hz
1.E-04
4
5
6
7
8
9
10
11
12
13
14
S/N dB (Noise in 20 to 9600Hz band)
Figure 24: Effect of AC Coupling on BER (without FEC)
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4-Level FSK Modem Data Pump
Page 41 of 50
MX929B PRELIMINARY INFORMATION
2. Any AC coupling at the receive input will transform any step in the voltage at the discriminator output to a
slowly decaying pulse which can confuse the modem's level measuring circuits. As illustrated in Figure 25
below, the time for this step to decay to 37% of its original value is 'RC' where:
RC =
1
25(3dB cut - off frequency of the RC network)
which is 32ms, or 153 symbol times at 4800 symbols/sec (9600bps) for a 5Hz network.
Step Input
to RC Circuit
100%
Output of
RC Circuit
37%
T = RC
Figure 25: Decay Time - AC Coupling
In general, it is best to DC couple the receiver discriminator to the modem and ensure that any AC coupling to
the transmitter's frequency modulator has a -3dB cut-off frequency of no higher than 5Hz for 4800
symbols/sec (9600bps).
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4-Level FSK Modem Data Pump
5.5
Page 42 of 50
MX929B PRELIMINARY INFORMATION
Radio Performance
The maximum data rate that can be transmitted over a radio channel using this modem depends on:
RF channel spacing.
Allowable adjacent channel interference.
Symbol rate.
Peak carrier deviation (modulation index).
Tx and Rx reference oscillator accuracy.
Modulator and demodulator linearity.
Receiver IF filter frequency and phase characteristics.
Use of error correction techniques.
Acceptable error rate.
As a guide, 4800 symbols/sec (9600bps) can be achieved (subject to local regulatory requirements) over a
system with 12.5kHz channel spacing if the transmitter frequency deviation is set to ±2.5kHz peak for a
repetitive ' +3 +3 -3 -3 ... ' pattern and the maximum difference between transmitter and receiver 'carrier'
frequencies is less than 2400Hz.
The modulation scheme employed by these modems is designed to achieve high data throughput by
exploiting as much as possible of the RF channel bandwidth. However, this does place constraints on the
performance of the radio. Particular attention must be paid to:
Linearity, frequency, and phase response of the Tx Frequency Modulator. For a 4800 symbols/sec
(9600bps) system, the frequency response should be within ±2dB over the range 3Hz to 5kHz, relative to
2400Hz.
The bandwidth and phase response of the receiver's IF filters.
Accuracy of the Tx and Rx reference oscillators, as any difference will shift the received signal towards the
skirts of the IF filter response and cause a DC offset at the discriminator output.
Viewing the equalized received signal eye diagram, using the Mode Register RXEYE function, provides a good
indication of the overall RF transmitter/receiver performance.
Tx FREQUENCY
MODULATOR
Rx FREQUENCY
DISCRIMINATOR
SIGNAL LEVEL
ADJUSTMENT
DC LEVEL
ADJUSTMENT
RXAMPOUT
RXIN
µC
D0 - D7
A0 - A1
CS
RD
WR
IRQ
SIGNAL AND
DC LEVEL
ADJUSTMENT
Rx
CIRCUITS
D0 - D7
A0 - A1
CS
RD
WR
IRQ
Tx
CIRCUITS
TXOUT
MX929A MODEM
Figure 26: Typical Connections between Radio and MX929B
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4-Level FSK Modem Data Pump
5.6
Page 43 of 50
MX929B PRELIMINARY INFORMATION
Received Signal Quality Monitor
In applications where the modem has to monitor a long transmission containing a number of concatenated
Frames, it is recommended that the controlling software include a function which regularly checks that the
modem is still receiving a good data signal and triggers a re-acquisition and possibly changes to another
channel if a problem is encountered. This strategy has been shown to improve the system's overall
performance in situations where fading, large noise bursts, severe co-channel interference, or loss of the
received signal for long periods are likely to occur.
Such a function can be simply implemented by regularly reading the Data Quality Register, which gives a
measure of the overall quality of the received signal, as well as the current effectiveness of the modem's clock
extraction and level measurement systems. Experience has shown that if two consecutive DQ readings are
both less than 50 then it is worth instructing the MX929B to re-acquire the received signal levels and timing
once it has been established that the received carrier level is satisfactory. Re-acquisition should follow the
procedure given in Section 5.3.
The interval between Data Quality readings is not critical, but should be a minimum of 64 symbol times except
for the first reading made after triggering the AQSC and AQLEV automatic acquisition sequences, which
should be delayed for about 250 symbol times.
A suitable algorithm is shown in Figure 27.
AQSC/AQLEV
task issued
Reset timer.
Set µC variable 'LAST_DQ' to 99
No
Note: Times are symbol times.
Timer > 250 ?
Read DQ register into
µC variable 'THIS_DQ'
'THIS_DQ' < 50 ?
No
Yes
'LAST_DQ' < 50 ?
No
Yes
Re Acquire
Copy 'THIS_DQ' to 'LAST DQ'.
Reset Timer.
No
Timer > 64 ?
Yes
Figure 27: Received Signal Quality Monitor Flowchart
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4-Level FSK Modem Data Pump
Page 44 of 50
MX929B PRELIMINARY INFORMATION
6. Performance Specification
6.1
Electrical Performance
6.1.1
Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
General
Min.
Max.
Units
Supply (VDD - VSS)
-0.3
7.0
V
Voltage on any pin to VSS
-0.3
VDD + 0.3
V
VDD
-30
30
mA
VSS
-30
30
mA
Any other pin
-20
20
mA
DW and P Packages
Min.
Max.
Units
800
mW
13
mW/°C above °C
Current
Total Allowable Power Dissipation at TAMB = 25°C
Derating above 25°C
Storage Temperature
-55
125
°C
Operating Temperature
-40
85
°C
Min.
Max.
Units
550
mW
DS Package
Total Allowable Power Dissipation at TAMB = 25°C
Derating above 25°C
6.1.2
9
mW/°C above °C
Storage Temperature
-55
125
°C
Operating Temperature
-40
85
°C
Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Min.
Max.
Units
3.0
5.5
V
Symbol Rate
2400
9600
Symbols/sec
Temperature
-40
85
°C
Xtal Frequency
1.0
10.0
MHz
Supply (VDD - VSS)
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
6.1.3
Page 45 of 50
MX929B PRELIMINARY INFORMATION
Operating Characteristics
For the following conditions unless otherwise specified:
Xtal Frequency = 4.9152MHz, Symbol Rate = 4800 symbols/sec (9600bps),
Noise Bandwidth = 0 to 9600Hz, VDD = 3.3V to 5.0V @ TAMB = 25°C
Notes
Min.
Typ.
Max.
Units
DC Parameters
IDD
1
4.0
10.0
mA
IDD (VDD = 3.3V)
1
2.5
6.3
mA
IDD (Powersave Mode)
1
1.5
mA
IDD (Powersave Mode, VDD = 3.3V)
1
0.6
mA
2
1.0
2.5
k
AC Parameters
Tx Output
TXOUT Impedance
Signal Level
TXIMP = 0
3
0.8
1.0
1.2
VP-P
TXIMP = 1
3
0.88
1.1
1.32
VP-P
4
-0.25
0.25
V
Output DC Offset with respect to VDD /2
Rx Input
RXIN Impedance (at 100Hz)
10.0
M
RXIN Amp Voltage Gain (input = 1mVRMS at 100Hz)
300
V/V
Input Signal Level
5
0.7
1.0
1.3
VP-P
DC Offset with respect to VDD /2
5
-0.5
0.5
V
'High' Pulse Width
6
40
ns
'Low' Pulse Width
6
40
ns
10.0
M
20
dB
70%
VDD
Xtal/Clock Input
Input Impedance (at 100Hz)
Inverter Gain (input = 1 mVRMS at 100Hz)
µC Interface
Input Logic "1" Level
7, 8
Input Logic "0" Level
7, 8
Input Leakage Current (VIN = 0 to VDD)
7, 8
Input Capacitance
7, 8
5.0
30%
VDD
5.0
µA
10.0
pF
Output Logic "1" Level (lOH = 120µA)
8
Output Logic "0" Level (lOL = 360µA)
8, 9
8%
VDD
9
10.0
µA
'Off' State Leakage Current (VOUT = VDD)
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
92%
Fax: 336 744 5054
VDD
Doc. # 20480171.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 46 of 50
MX929B PRELIMINARY INFORMATION
6.1.3.1 Operating Characteristics Notes:
1. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator.
2. Small signal impedance.
3. Measured after the external RC filter (R4/C5) for a "+3 +3 -3 -3...." symbol sequence. (Tx output level is
proportional to VDD).
4. Measured at the TXOUT pin with the modem in the Tx idle mode.
5. For optimum performance, measured at RXAMPOUT pin, for a "...+3 +3 -3 -3..." symbol sequence,
TXIMP = 0 or 1. The optimum level and DC offset values are proportional to VDD.
6. Timing for an external input to the XTAL/Clock pin.
7. WR , RD , CS , A0 and A1 pins.
8. D0 - D7 pins.
9.
IRQ pin.
6.1.4
Timing
C Parallel Interface Timings (ref. Figure 28)
6.1.4.1
Notes
Min.
Typ.
Max.
Units
Address valid to CS low time
0
ns
tAH
Address hold time
0
ns
tCSH
CS hold time
0
ns
tCSHI
CS high time
6.0
clock cycles
tCSRWL
CS to WR or RD low time
0
ns
tDHR
Read data hold time
0
ns
tDHW
Write data hold time
0
ns
tDSW
Write data setup time
90.0
ns
tRHCSL
RD high to CS low time (write)
0
ns
tRACL
Read access time from CS low
2
175
ns
tRARL
Read access time from RD low
2
145
ns
tRL
RD low time
tRX
RD high to D0-D7 3-state time
tWHCSL
WR high to CS low time (read)
tWL
WR low time
tACSL
1
200
ns
50
ns
0
ns
200
ns
Timing Notes:
1. Xtal/Clock cycles at the XTAL/CLOCK pin.
2. With 30pF max to VSS on D0 - D7 pins.
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 47 of 50
MX929B PRELIMINARY INFORMATION
WRITE CYCLE (DATA TO MODEM)
tAH
ADDRESS
A0, A1
ADDRESS VALID
tACSL
tCSH
tCSHI
CS
tWL
WR
tRHCSL
tCSRWL
RD
tDSW
tDHW
DATA
D0 to D7
DATA
VALID
READ CYCLE (DATA FROM MODEM)
tAH
ADDRESS
A0, A1
ADDRESS VALID
tACSL
tCSH
CS
tCSHI
tWHCSL
WR
tCSRWL
tRL
RD
tRX
tRARL
DATA
D0 to D7
tDHR
DATA VALID
tRACL
Figure 28: 2C Parallel Interface Timings
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
6.1.5
Page 48 of 50
MX929B PRELIMINARY INFORMATION
Typical Bit Error Rate
1E-1
BER with FEC
1E-2
BER without FEC
1E-3
BER
1E-4
1E-5
1E-6
8
9
10
11
12
13
14
15
16
S/N dB (Noise in 2 x Symbol RateBandwidth)
Figure 29: Typical Bit Error Rate With and Without FEC
Measured under nominal working conditions, LEVRES bits set to 'Level Track' or 'Slow Peak Detect' and
PLLBW bits set to 'Medium' or 'Narrow' Bandwidth, Command Register TXIMP bit set to '0' or '1' (same for Tx
and Rx devices), with pseudo-random data.
Note:
§ Signal Voltage ·
¸¸
S / N calculates as 20log10¨¨
© Noise Voltage ¹
Where:
Signal Voltage is the measured VRMS of a random 4-level signal.
Noise Voltage is the VRMS of a flat Gaussian noise signal having a bandwidth from a few Hz to
twice the symbol rate (e.g. to 9600Hz when measuring a 4800 symbol/sec (9600bps) system).
Both signals are measured at the same point in the test circuit.
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
6.2
Page 49 of 50
MX929B PRELIMINARY INFORMATION
Packaging
Package Tolerances
A
Z
B
ALTERNATIVE
PIN
LOCATION
MARKING
E
W
L
T
PIN 1
X
Y
C K
H
P
J
DIM.
A
B
C
E
H
J
K
L
P
T
W
X
Y
Z
MIN.
TYP.
MAX.
0.613 (15.57)
0.299 (7.59)
0.105 (2.67)
0.419 (10.64)
0.020 (0.51)
0.020 (0.51)
0.046 (1.17)
0.597 (15.16)
0.286 (7.26)
0.093 (2.36)
0.390 (9.90)
0.003 (0.08)
0.013 (0.33)
0.036 (0.91)
0.050 (1.27)
0.016 (0.41)
0.050 (1.27)
0.0125 (0.32)
0.009 (0.23)
45°
10°
0°
5°
7°
5°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
Figure 30: 24-pin SOIC Mechanical Outline: Order as part no. MX929BDW
Package Tolerances
A
Z
E
B
PIN 1
L
T
PIN 1
X
Y
H
J
P
C
DIM.
A
B
C
E
H
J
L
P
T
X
Y
Z
MIN.
TYP.
MAX.
0.318 (8.07)
0.328 (8.33)
0.205 (5.20)
0.213 (5.39)
0.066 (1.67)
0.079 (2.00)
0.312 (7.90)
0.301 (7.65)
0.002 (0.05)
0.008 (0.21)
0.010 (0.25)
0.015 (0.38)
0.022 (0.55)
0.037 (0.95)
0.026 (0.65)
0.005 (0.13)
0.009 (0.22)
0°
8°
7°
9°
4°
10°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
Figure 31: 24-pin SSOP Mechanical Outline: Order as part no. MX929BDS
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
All trademarks and service marks are held by their respective companies.
4-Level FSK Modem Data Pump
Page 50 of 50
MX929B PRELIMINARY INFORMATION
A
Package Tolerances
B
E
E1
Y
T
PIN1
K
H
L
C
J
J1
P
DIM.
A
B
C
E
E1
H
J
J1
K
L
P
T
Y
MIN.
TYP.
MAX.
1.270 (32.26)
1.200 (30.48)
0.555 (14.04)
0.500 (12.70)
0.151 (3.84)
0.220 (5.59)
0.600 (15.24)
0.670 (17.02)
0.590 (14.99)
0.625 (15.88)
0.015 (0.38)
0.045 (1.14)
0.015 (0.38)
0.023 (0.58)
0.040 (1.02)
0.065 (1.65)
0.066 (1.67)
0.074 (1.88)
0.121 (3.07)
0.160 (4.05)
0.100 (2.54)
0.008 (0.20)
0.015 (0.38)
7°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
Figure 32: 24-pin PDIP Mechanical Outline: Order as part no. MX929BP
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
Fax: 336 744 5054
Doc. # 20480171.003
All trademarks and service marks are held by their respective companies.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML
Microcircuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
CML Microcircuits (USA) [formerly MX-COM, Inc.] Product Textual Marking
On CML Microcircuits (USA) products, the ‘MX-COM’ textual logo is being replaced by a ‘CML’
textual logo.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
uk.sales@cmlmicro.com
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
us.sales@cmlmicro.com
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
sg.sales@cmlmicro.com
www.cmlmicro.com
D/CML (D)/2 May 2002