HB52RF648DC-B, HB52RD648DC-B 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword × 64-bit, 133/100 MHz Memory Bus, 2-Bank Module (16 pcs of 32 M × 8 components) PC133/100 SDRAM E0083H40 (Ver. 4.0) Nov. 16, 2001 (K) Japan Description The HB52RF648DC, HB52RD648DC are a 32M × 64 × 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 16 pieces of 256-Mbit SDRAM (HM5225805BTB) sealed in TCP package and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. Features • Fully compatible with: JEDEC standard outline 8-byte S.O.DIMM • 144-pin Zig Zag Dual tabs socket type (dual lead out) Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness) Lead pitch: 0.80 mm • 3.3 V power supply • Clock frequency: 133/100 MHz (max) • LVTTL interface • Data bus width: × 64 Non parity • Single pulsed RAS • 4 Banks can operates simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length : 1/2/4/8 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HB52RF648DC-B, HB52RD648DC-B • 2 variations of burst sequence Sequential Interleave • Programmable CE latency: 2/3 • Byte control by DQMB • Refresh cycles: 8192 refresh cycles/64 ms • 2 variations of refresh Auto refresh Self refresh • Low self refresh current: HB52RF648DC-xxBL (L-version) : HB52RD648DC-xxBL (L-version) Ordering Information Frequency CE latency Package HB52RF648DC-75B* HB52RF648DC-75BL*1 133 MHz 133 MHz 3 3 Small outline DIMM (144-pin) Gold HB52RD648DC-A6B*1 HB52RD648DC-A6BL*1 HB52RD648DC-B6B*2 HB52RD648DC-B6BL*2 100 MHz 100 MHz 100 MHz 100 MHz 2/3 2/3 3 3 Type No. 1 Notes: 1. 100 MHz operation at CE latency = 2. 2. 66 MHz operation at CE latency = 2. Data Sheet E0083H40 2 Contact pad HB52RF648DC-B, HB52RD648DC-B Pin Arrangement Front Side 1pin 59pin 61pin 143pin 2pin 60pin 62pin 144pin Back Side Front side Back side Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name 1 VSS 73 NC 2 VSS 74 CK1 3 DQ0 75 VSS 4 DQ32 76 VSS 5 DQ1 77 NC 6 DQ33 78 NC 7 DQ2 79 NC 8 DQ34 80 NC 9 DQ3 81 VCC 10 DQ35 82 VCC 11 VCC 83 DQ16 12 VCC 84 DQ48 13 DQ4 85 DQ17 14 DQ36 86 DQ49 15 DQ5 87 DQ18 16 DQ37 88 DQ50 17 DQ6 89 DQ19 18 DQ38 90 DQ51 19 DQ7 91 VSS 20 DQ39 92 VSS 21 VSS 93 DQ20 22 VSS 94 DQ52 23 DQMB0 95 DQ21 24 DQMB4 96 DQ53 25 DQMB1 97 DQ22 26 DQMB5 98 DQ54 27 VCC 99 DQ23 28 VCC 100 DQ55 29 A0 101 VCC 30 A3 102 VCC 31 A1 103 A6 32 A4 104 A7 33 A2 105 A8 34 A5 106 BA0 35 VSS 107 VSS 36 VSS 108 VSS 37 DQ8 109 A9 38 DQ40 110 BA1 39 DQ9 111 A10 (AP) 40 DQ41 112 A11 Data Sheet E0083H40 3 HB52RF648DC-B, HB52RD648DC-B Front side Back side Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name 41 DQ10 113 VCC 42 DQ42 114 VCC 43 DQ11 115 DQMB2 44 DQ43 116 DQMB6 45 VCC 117 DQMB3 46 VCC 118 DQMB7 47 DQ12 119 VSS 48 DQ44 120 VSS 49 DQ13 121 DQ24 50 DQ45 122 DQ56 51 DQ14 123 DQ25 52 DQ46 124 DQ57 53 DQ15 125 DQ26 54 DQ47 126 DQ58 55 VSS 127 DQ27 56 VSS 128 DQ59 57 NC 129 VCC 58 NC 130 VCC 59 NC 131 DQ28 60 NC 132 DQ60 61 CK0 133 DQ29 62 CKE0 134 DQ61 63 VCC 135 DQ30 64 VCC 136 DQ62 65 RE 137 DQ31 66 CE 138 DQ63 67 W 139 VSS 68 CKE1 140 VSS 69 S0 141 SDA 70 A12 142 SCL 71 S1 143 VCC 72 NC 144 VCC Data Sheet E0083H40 4 HB52RF648DC-B, HB52RD648DC-B Pin Description Pin name Function A0 to A12 Address input Row address A0 to A12 Column address A0 to A9 BA0/BA1 Bank select address DQ0 to DQ63 Data-input/output S0/S1 Chip select RE Row address asserted bank enable CE Column address asserted W Write enable DQMB0 to DQMB7 Byte input/output mask CK0/CK1 Clock input CKE0/CKE1 Clock enable SDA Data-input/output for serial PD SCL Clock input for serial PD VCC Power supply VSS Ground NC No connection Data Sheet E0083H40 5 HB52RF648DC-B, HB52RD648DC-B Serial PD Matrix*1 Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 Number of bytes used by module manufacturer 1 0 0 0 0 0 0 0 80 128 1 Total SPD memory size 0 0 0 0 1 0 0 0 08 256 byte 2 Memory type 0 0 0 0 0 1 0 0 04 SDRAM 3 Number of row addresses bits 0 0 0 0 1 1 0 1 0D 13 4 Number of column addresses bits 0 0 0 0 1 0 1 0 0A 10 5 Number of banks 0 0 0 0 0 0 1 0 02 2 6 Module data width 0 1 0 0 0 0 0 0 40 64 7 Module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+) 8 Module interface signal levels 0 0 0 0 0 0 0 1 01 LVTTL 9 0 1 1 1 0 1 0 1 75 CL = 3 1 0 1 0 0 0 0 0 A0 0 1 0 1 0 1 0 0 54 0 1 1 0 0 0 0 0 60 SDRAM cycle time (highest CE latency) (-75) 7.5 ns (-A6/B6) 10 ns 10 SDRAM access from Clock (highest CE latency) (-75) 5.4 ns (-A6/B6) 6 ns 11 Module configuration type 0 0 0 0 0 0 0 0 00 Non parity 12 Refresh rate/type 1 0 0 0 0 0 1 0 82 Normal (7.8125 µs) Self refresh 13 SDRAM width 0 0 0 0 1 0 0 0 08 ×8 14 Error checking SDRAM width 0 0 0 0 0 0 0 0 00 — 15 0 SDRAM device attributes: minimum clock delay for backto-back random column addresses 0 0 0 0 0 0 1 01 1 CLK 16 SDRAM device attributes: Burst lengths supported 0 0 0 0 1 1 1 1 0F 1, 2, 4, 8 17 SDRAM device attributes: number of banks on SDRAM device 0 0 0 0 0 1 0 0 04 4 18 SDRAM device attributes: CE latency 0 0 0 0 0 1 1 0 06 2, 3 19 SDRAM device attributes: S latency 0 0 0 0 0 0 0 1 01 0 Data Sheet E0083H40 6 HB52RF648DC-B, HB52RD648DC-B Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 20 SDRAM device attributes: W latency 0 0 0 0 0 0 0 1 01 0 21 SDRAM module attributes 0 0 0 0 0 0 0 0 00 Non buffer 22 SDRAM device attributes: General 0 0 0 0 1 1 1 0 0E VCC ± 10% 23 SDRAM cycle time (2nd highest CE latency) (-75/A6)10 ns 1 0 1 0 0 0 0 0 A0 CL = 2 1 1 1 1 0 0 0 0 F0 0 1 1 0 0 0 0 0 60 1 0 0 1 0 0 0 0 90 (-B6) 15 ns 24 SDRAM access from Clock (2nd highest CE latency) (-75/A6) 6 ns (-B6) 9 ns 25 SDRAM cycle time (3rd highest CE latency) Undefined 0 0 0 0 0 0 0 0 00 26 SDRAM access from Clock (3rd highest CE latency) Undefined 0 0 0 0 0 0 0 0 00 27 Minimum row precharge time 0 0 0 1 0 1 0 0 14 20 ns 28 Row active to row active min (-75) 0 0 0 0 1 1 1 1 0F 15 ns 0 0 0 1 0 1 0 0 14 20 ns (-A6/B6) 29 RE to CE delay min 0 0 0 1 0 1 0 0 14 20 ns 30 Minimum RE pulse width (-75) 0 0 1 0 1 1 0 1 2D 45 ns 0 0 1 1 0 0 1 0 32 50 ns (-A6/B6) 31 Density of each bank on module 0 1 0 0 0 0 0 0 40 256M byte 32 Address and command signal 0 input setup time (-75) 0 0 1 0 1 0 1 15 1.5 ns 0 0 1 0 0 0 0 0 20 2.0 ns Address and command signal 0 input hold time (-75) 0 0 0 1 0 0 0 08 0.8 ns 0 0 0 1 0 0 0 0 10 1.0 ns 0 0 0 1 0 1 0 1 15 1.5 ns 0 0 1 0 0 0 0 0 20 2.0 ns (-A6/B6) 33 (-A6/B6) 34 Data signal input setup time (-75) (-A6/B6) Data Sheet E0083H40 7 HB52RF648DC-B, HB52RD648DC-B Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 35 0 0 0 0 1 0 0 0 08 0.8 ns 0 0 0 1 0 0 0 0 10 1.0 ns 36 to 61 Superset information 0 0 0 0 0 0 0 0 00 Future use 62 SPD data revision code 0 0 0 1 0 0 1 0 12 Rev. 1.2B 63 Checksum for bytes 0 to 62 (-75) 0 1 0 1 0 0 1 1 53 83 (-A6) 1 0 1 1 1 0 1 0 BA 186 (-B6) 0 0 1 1 1 0 1 0 3A 58 Manuf act urer’s JEDEC ID c ode 0 0 0 0 0 1 1 1 07 HITACHI 65 to 71 Manuf act urer’s JEDEC ID c ode 0 0 0 0 0 0 0 0 00 72 Manufacturing location × × × × × × × × ×× * 2 (ASCII8bit code) 73 Manufacturer’s part number 0 1 0 0 1 0 0 0 48 H 74 Manufacturer’s part number 0 1 0 0 0 0 1 0 42 B 75 Manufacturer’s part number 0 0 1 1 0 1 0 1 35 5 76 Manufacturer’s part number 0 0 1 1 0 0 1 0 32 2 77 Manufacturer’s part number 0 1 0 1 0 0 1 0 52 R 78 Manufacturer’s part number (-75) 0 1 0 0 0 1 1 0 46 F 0 1 0 0 0 1 0 0 44 D Data signal input hold time (-75) (-A6/B6) 64 (-A6/B6) 79 Manufacturer’s part number 0 0 1 1 0 1 1 0 36 6 80 Manufacturer’s part number 0 0 1 1 0 1 0 0 34 4 81 Manufacturer’s part number 0 0 1 1 1 0 0 0 38 8 82 Manufacturer’s part number 0 1 0 0 0 1 0 0 44 D 83 Manufacturer’s part number 0 1 0 0 0 0 1 1 43 C 84 Manufacturer’s part number 0 0 1 0 1 1 0 1 2D 85 Manufacturer’s part number (-75) 0 0 1 1 0 1 1 1 37 7 (-A6) 0 1 0 0 0 0 0 1 41 A (-B6) 0 1 0 0 0 0 1 0 42 B Data Sheet E0083H40 8 HB52RF648DC-B, HB52RD648DC-B Byte No. Function described Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 86 0 0 1 1 0 1 0 1 35 5 0 0 1 1 0 1 1 0 36 6 Manufacturer’s part number (-75) (-A6/B6) 87 Manufacturer’s part number 0 1 0 0 0 0 1 0 42 B 88 Manufacturer’s part number (-xxB) 0 0 1 0 0 0 0 0 20 (Space) 0 1 0 0 1 1 0 0 4C L (-xxBL) 89 Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) 90 Manufacturer’s part number 0 0 1 0 0 0 0 0 20 (Space) 91 Revision code 0 0 1 1 0 0 0 0 30 Initial 92 Revision code 0 0 1 0 0 0 0 0 20 (Space) 93 Manufacturing date × × × × × × × × ×× Year code (BCD) 94 Manufacturing date × × × × × × × × ×× Week code (BCD) 95 to 98 Assembly serial number *3 99 to 125 Manufacturer specific data — — — — — — — — — *4 126 Intel specification frequency 0 1 1 0 0 1 0 0 64 100 MHz 127 Intel specification CE# latency 1 support (-75/A6) 1 0 0 1 1 1 1 CF CL = 2, 3 1 0 0 1 1 0 1 CD CL = 3 (-B6) 1 Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”. These SPD are based on Rev. 1.2B Specification. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 125 are not defined (“1” or “0”). Data Sheet E0083H40 9 HB52RF648DC-B, HB52RD648DC-B Block Diagram W S1 S0 CS WE DQMB0 DQ0 to DQ7 DQMB1 DQ8 to DQ15 DQM N0, N1 I/O0 to I/O7 D0 CS WE DQM N2, N3 I/O0 to I/O7 D1 CS WE DQMB2 DQ16 to DQ23 DQMB3 DQ24 to DQ31 DQM N4, N5 I/O0 to I/O7 D2 CS WE DQM N6, N7 I/O0 to I/O7 D3 CS WE CS WE DQM D8 I/O0 to I/O7 DQ32 to DQ39 CS WE DQM DQMB5 I/O0 to I/O7 DQ40 to DQ47 D9 CS WE DQM D4 I/O0 to I/O7 CS WE DQM CS WE DQM D5 D13 I/O0 to I/O7 CS WE D10 I/O0 to I/O7 DQ48 to DQ55 CS WE DQM DQMB7 I/O0 to I/O7 DQ56 to DQ63 D11 RAS (D0 to D15) CE CAS (D0 to D15) Ax (D0 to D15) BA0, BA1 BAx (D0 to D15) CKE0 CKE (D0 to D7) CKE1 CKE (D8 to D15) D12 I/O0 to I/O7 N10, N11 I/O0 to I/O7 DQM DQMB6 A0 to A12 N12, N13 I/O0 to I/O7 CS WE DQM D6 CS WE DQM N14, N15 I/O0 to I/O7 D14 I/O0 to I/O7 CS WE DQM D7 D15 I/O0 to I/O7 Serial PD SDA SCL SCL A0 U0 A1 A2 VSS CLK (D0, D4, D8, D12) CLK0 CLK (D1, D5, D9, D13) CLK (D2, D6, D10, D14) CLK1 CLK (D3, D7, D11, D15) VCC VCC (D0 to D15) C0 to C15 VSS (D0 to D15) Data Sheet E0083H40 10 N8, N9 CS WE DQM RE VSS DQM DQMB4 * D0 to D15 : HM5225805 U0 : 2-kbit EEPROM C0 to C15 : 0.1 µF N0 to N15 : Network resistors (10 Ω) SDA HB52RF648DC-B, HB52RD648DC-B Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to V SS VT –0.5 to VCC + 0.5 (≤ 4.6 (max)) V 1 Supply voltage relative to VSS VCC –0.5 to +4.6 V 1 Short circuit output current Iout 50 mA Power dissipation PT 8.0 W Operating temperature Topr 0 to +65 °C Storage temperature Tstg –55 to +125 °C Note: 1. Respect to V SS . DC Operating Conditions (Ta = 0 to +65°C) Parameter Symbol Min Max Unit Notes Supply voltage VCC 3.0 3.6 V 1, 2 VSS 0 0 V 3 Input high voltage VIH 2.0 VCC + 0.3 V 1, 4 Input low voltage VIL –0.3 0.8 V 1, 5 Ambient illuminance — — 100 lx Notes: 1. 2. 3. 4. 5. All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC. VIL (min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS . Data Sheet E0083H40 11 HB52RF648DC-B, HB52RD648DC-B DC Characteristics (Ta = 0 to +65˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V) HB52RF648DC/HB52RD648DC -75 -A6 -B6 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Operating current (CE latency = 2) I CC1 — 1120 — 1000 — 840 (CE latency = 3) I CC1 — 1120 — 1000 — 1000 mA Standby current in power down I CC2P — 48 — 48 — 48 Standby current in power down (input signal stable) I CC2PS — 32 — 32 — Standby current in non I CC2N power down — 320 — Active standby current I CC3P in power down — 64 Active standby current I CC3N in non power down — Notes Burst length = 1 t RC = min 1, 2, 3 mA CKE = VIL, t CK = 12 ns 6 32 mA CKE = VIL, t CK = ∞ 7 320 — 320 mA CKE, S = VIH, t CK = 12 ns 4 — 64 64 mA CKE = VIL, t CK = 12 ns 1, 2, 6 480 — 480 — 480 mA CKE, S = VIH, t CK = 12 ns 1, 2, 4 mA t CK = min, BL = 4 1, 2, 5 — mA Burst operating current (CE latency = 2) I CC4 — 1040 — 1040 — 840 (CE latency = 3) I CC4 — 1320 — 1040 — 1040 mA Refresh current I CC5 — 2000 — 2000 — 2000 mA t RC = min 3 Self refresh current I CC6 — 48 — 48 — 48 mA VIH ≥ VCC – 0.2 V VIL ≤ 0.2 V 8 Self refresh current (L-version) I CC6 — 32 — 32 — 32 mA Input leakage current I LI –10 10 –10 10 –10 10 µA 0 ≤ Vin ≤ VCC Output leakage current I LO –10 10 –10 10 –10 10 µA 0 ≤ Vout ≤ VCC DQ = disable Output high voltage VOH 2.4 — 2.4 — 2.4 — V I OH = –4 mA Output low voltage VOL — 0.4 — 0.4 — 0.4 V I OL = 4 mA Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK0/CK1 operating current. 7. After power down mode, no CK0/CK1 operating current. 8. After self refresh mode set, self refresh current. Data Sheet E0083H40 12 HB52RF648DC-B, HB52RD648DC-B Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V) Parameter Symbol Max Unit Notes Input capacitance (Address) CIN 90 pF 1, 2, 4 Input capacitance (RE, CE, W) CIN 90 pF 1, 2, 4 Input capacitance (S0/S1, CK0/CK1, CKE0/CKE1) CIN 60 pF 1, 2, 4 Input capacitance (DQMB) CIN 30 pF 1, 2, 4 Input/Output capacitance (DQ) CI/O 27 pF 1, 2, 3, 4 Notes: 1. 2. 3. 4. Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested. Data Sheet E0083H40 13 HB52RF648DC-B, HB52RD648DC-B AC Characteristics (Ta = 0 to +65°C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V) HB52RF648DC/HB52RD648DC -75 -A6 -B6 Parameter PC100 Symbol Symbol Min Max Min Max Min Max Unit Notes System clock cycle time (CE latency = 2) t CK Tclk 10 — 10 — 15 — ns (CE latency = 3) t CK Tclk 7.5 — 10 — 10 — ns CK high pulse width t CKH Tch 2.5 — 3 — 3 — ns 1 CK low pulse width t CKL Tcl 2.5 — 3 — 3 — ns 1 Access time from CK (CE latency = 2) t AC Tac — 6 — 6 — 8 ns 1, 2 (CE latency = 3) t AC Tac — 5.4 — 6 — 6 ns Data-out hold time t OH Toh 2.7 — 3 — 3 — ns 1, 2 CK to Data-out low impedance t LZ 2 — 2 — 2 — ns 1, 2, 3 CK to Data-out high impedance t HZ — 5.4 — 6 — 6 ns 1, 4 Input setup time t AS , t CS, t DS, t CES Tsi 1.5 — 2 — 2 — ns 1, 5, 6 CKE setup time for power down exit t CESP Tpde 1.5 — 2 — 2 — ns 1 Input hold time t AH, t CH, t DH, t CEH Thi 0.8 — 1 — 1 — ns 1, 6 Ref/Active to Ref/Active command period t RC Trc 67.5 — 70 — 70 — ns 1 Active to Precharge command period t RAS Tras 45 120000 50 120000 50 120000 ns 1 Active command to column command (same bank) t RCD Trcd 20 — 20 — 20 — ns 1 Precharge to active command period t RP Trp 20 — 20 — 20 — ns 1 Write recovery or data-in to precharge lead time t DPL Tdpl 15 — 20 — 20 — ns 1 Active (a) to Active (b) command period t RRD Trrd 15 — 20 — 20 — ns 1 Transition time (rise and fall) t T 1 5 1 5 1 5 ns Refresh period — 64 — 64 — 64 ms t REF Data Sheet E0083H40 14 1 HB52RF648DC-B, HB52RD648DC-B Notes: 1. 2. 3. 4. 5. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is C L = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command. Test Conditions • Input and output timing reference levels: 1.5 V • Input waveform and output load: See following figures 2.4 V input 0.4 V DQ 2.0 V 0.8 V CL t T tT Data Sheet E0083H40 15 HB52RF648DC-B, HB52RD648DC-B Relationship Between Frequency and Minimum Latency HB52RF648DC/ HB52RD648DC Parameter -75 -A6/B6 Frequency (MHz) 133 100 tCK (ns) Symbol Active command to column command (same bank) lRCD Active command to active command (same bank) PC100 Symbol 7.5 10 Notes 3 2 1 lRC 9 7 = [lRAS+ lRP] 1 Active command to precharge command (same bank) lRAS 6 5 1 Precharge command to active command (same bank) lRP 3 2 1 Write recovery or data-in to precharge command (same bank) lDPL 2 2 1 Active command to active command (different bank) lRRD 2 2 1 Self refresh exit time lSREX Tsrx 1 1 2 Last data in to active command (Auto precharge, same bank) lAPW Tdal 5 4 = [lDPL + lRP] Self refresh exit to command input lSEC 9 7 = [lRC] 3 Precharge command to high impedance (CE latency = 2) lHZP Troh 2 2 lHZP Troh 3 3 lAPR 1 1 lEP –1 –1 lEP –2 –2 (CE latency = 3) Last data out to active command (Auto precharge, same bank) Last data out to precharge (early precharge) (CE latency = 2) (CE latency = 3) Tdpl Column command to column command lCCD Tccd 1 1 Write command to data in latency lWCD Tdwd 0 0 DQMB to data in lDID Tdqm 0 0 DQMB to data out lDOD Tdqz 2 2 CKE to CK disable lCLE Tcke 1 1 Register set to active command lRSA Tmrd 1 1 Data Sheet E0083H40 16 HB52RF648DC-B, HB52RD648DC-B HB52RF648DC/ HB52RD648DC Parameter -75 -A6/B6 Frequency (MHz) 133 100 PC100 Symbol 7.5 tCK (ns) Symbol 10 S to command disable lCDD 0 0 Power down exit to command input lPEC 1 1 Notes Notes: 1. lRCD to l RRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP] Data Sheet E0083H40 17 HB52RF648DC-B, HB52RD648DC-B Pin Functions CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0/S1 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM modules, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BA) is precharged. BA0/BA1 (input pin): BA0/BA1 is a bank select signal (BA). The memory array is divided into bank0, bank1, bank2 and bank3. If BA0 is Low and BA1 is Low, bank0 is selected. If BA0 is High and BA1 is Low, bank1 is selected. If BA0 is Low and BA1 is High, bank2 is selected. If BA0 is High and BA1 is High, bank3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for powerdown mode, clock suspend mode and self refresh mode. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks). Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written (The latency of DQMB during writing is 0 clock). DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected. Detailed Operation Part Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet (E0082H). Data Sheet E0083H40 18 HB52RF648DC-B, HB52RD648DC-B Physical Outline Unit:mm 67.60 3.80 Max (Datum -A-) B 23.20 3.30 4.00 Min 20.00 1 143 31.75 Component area (front) 3.20 Min 2R3.00 Min A 32.80 1.00 ± 0.10 4.60 2.50 2.10 4.60 Component area (back) 4.00 ± 0.10 32.80 144 23.20 2 3.70 2-R2.00 2.00 Min (Datum -A-) Detail B Detail A (DATUM -A-) 2.5 0.80 R0.75 4.00 ± 0.10 2.55 Min 0.25 Max 0.60 ± 0.05 1.50 ± 0.10 ECA-TS2-0044-01 Data Sheet E0083H40 19 HB52RF648DC-B, HB52RD648DC-B Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. © Hitachi, Ltd., 2000 Data Sheet E0083H40 20