EXAR XR16L2552

XR16L2552
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2.25V TO 5.5V DUART WITH 16-BYTE FIFO
MAY 2005
REV. 1.1.1
GENERAL DESCRIPTION
The XR16L2552 (L2552) is a dual universal
asynchronous receiver and transmitter (UART) with 5
volt tolerant inputs. The XR16L2552 is an improved
version of the ST16C2552 UART with lower operating
voltages and 5 volt tolerant inputs. The L2552
provides enhanced UART functions with 16 byte TX
and RX FIFOs, automatic hardware (RTS/CTS) and
software (Xon/Xoff) flow control, and a complete
modem control interface. Onboard status registers
provide the user with error indications and
operational status. Indepedendent programmable
baud rate generators are provided to select transmit
and receive clock rates up to 3.125Mbps. An internal
loop-back capability allows onboard diagnostics. The
L2552 provides block mode data transfers (DMA)
through FIFO controls. DMA transfer monitoring is
provided through the signals TXRDY# and RXRDY#.
An Alternate Function Register provides the user with
the ability to write the control registers for both UARTs
concurrently and selection of the Multi-Function
output (Baudout#, OP2#, or RXRDY#).
NOTE:
FEATURES
• 2.25 to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin and functionally compatible to National
PC16552
• Pin-to-pin Compatible to Exar’s ST16C2552,
XR16L2752 and XR16C2852 in the 44-PLCC
• 2 Independent UART Channels
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1 Covered by U.S. Patent #5,649,122.
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APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
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Up to 3.125Mbps with external clock of 50 MHz
Register Set Compatible to 16C550
16 byte Transmit FIFO to reduce the bandwidth
requirement of the external CPU
16 byte Receive FIFO with error tags to reduce
the bandwidth requirement of the external CPU
4 selectable RX FIFO Trigger Levels
Automatic RTS/CTS hardware flow control
Automatic XonXoff software flow control
Wireless infrared encoder/decoder
Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
Programmable character lengths (5, 6, 7, 8)
with even, odd, or no parity
Multi-Function output allows more package
functions with fewer I/O pins
• Concurrent write to Channels A and B
• Crystal oscillator or external clock input
• 48-TQFP (7x7x1.0 mm) and 44-PLCC packages
FIGURE 1. XR16L2552 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDY# A/B
RXRDY# A/B
(48-TQFP Only)
* 5 Volt Tolerant Inputs
UART Channel A
UART
Regs
BRG
8-bit Data
Bus
Interface
16 Byte TX FIFO
16 Byte RX FIFO
UART Channel B
(same as Channel A)
Reset
RXA
TXB
RXB
Crystal Osc/Buffer
XTAL1
XTAL2
Modem Control Logic
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
TXA
TX & RX
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
2.25 to 5.5 Volt VCC
GND
DTR#A/B, RTS#A/B
2552BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
FIGURE 2. PIN OUT ASSIGNMENTS
36
RXA
2
35
TXA
D7
3
34
DTRA#
A0
4
33
RTSA#
XTAL1
5
32
MFA#
GND
6
31
RXRDYA#
XTAL2
7
30
INTA
RXRDYB#
8
29
VCC
A1
9
28
TXRDYB#
A2
10
27
RIB#
CHSEL
11
26
CDB#
INTB
12
25
DSRB#
D1
D0
TXRDYA#
VCC
RIA#
CDA#
DSRA#
CTSA#
2
1
44
43
42
41
40
CTSB#
D2
23
24
DTRB#
3
22
TXB
D3
21
RXB
44-PLCC PACKAGE
4
19
20
NC
18
RTSB#
IOR#
16
17
GND
15
IOW#
RESET
13
14
CS#
MFB#
XR16L2552
48-pin TQFP
D4
NC
37
1
D6
5
CTSA#
38
D5
6
CDA#
DSRA#
RIA#
41
39
VCC
42
40
D0
TXRDYA#
43
D1
45
44
D3
D2
46
D4
48
47
48-TQFP PACKAGE
D5
7
39
RXA
D6
8
38
TXA
D7
9
37
DTRA#
A0
10
36
RTSA#
XTAL1
11
35 MFA#
XR16L2552
44-pin PLCC
GND 12
34
INTA
XTAL2
13
33
VCC
A1
14
32
TXRDYB#
A2 15
31
RIB#
CHSEL 16
17
DSRB#
CTSB# 28
DTRB# 27
TXB 26
RXB 25
IOR# 24
RTSB# 23
GND 22
RESET 21
IOW# 20
MFB# 19
29
CS# 18
INTB
30 CDB#
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE
RANGE
DEVICE STATUS
XR16L2552IM
48-Lead TQFP
-40°C to +85°C
Active
XR16L2552IJ
44-Lead PLCC
-40°C to +85°C
Active
2
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
PIN DESCRIPTIONS
Pin Description
NAME
48-TQFP 44-PLCC
TYPE
PIN#
PIN #
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
10
9
4
15
14
10
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
3
2
1
48
47
46
45
44
9
8
7
6
5
4
3
2
I/O
IOR#
20
24
I
Input/Output Read Strobe (active low). The falling edge instigates an internal
read cycle and retrieves the data byte from an internal register pointed to by
the address lines [A2:A0]. The data byte is placed on the data bus to allow the
host processor to read it on the rising edge.
IOW#
15
20
I
Input/Output Write Strobe (active low). The falling edge instigates an internal
write cycle and the rising edge transfers the data byte on the data bus to an
internal register pointed by the address lines.
CS#
13
18
I
UART chip select (active low). This function selects channel A or B in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the L2552.
CHSEL
11
16
I
Channel Select - UART channel A or B is selected by the logical state of this
pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART
channel B while a logic 1 selects UART channel A. Normally, CHSEL could
just be an address line from the user CPU such as A3. Bit-0 of the Alternate
Function Register (AFR) can temporarily override CHSEL function, allowing
the user to write to both channel register simultaneously with one write cycle
when CS# is low. It is especially useful during the initialization routine.
INTA
30
34
O
UART channel A Interrupt output (active high). A logic high indicates channel
A is requesting for service.
INTB
12
17
O
UART channel B Interrupt output (active high). A logic high indicates channel
B is requesting for service.
TXRDYA#
43
1
O
UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A. If it is not used, leave it unconnected.
RXRDYA#
31
-
O
UART channel A Receiver Ready (active low). This output provides the RX
FIFO/RHR status for receive channel A. This pin is only available on the 48pin TQFP package. If it is not used, leave it unconnected.
TXRDYB#
28
32
O
UART channel B Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel B. If it is not used, leave it unconnected.
Data bus lines [7:0] (bidirectional).
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
Pin Description
NAME
RXRDYB#
48-TQFP 44-PLCC
TYPE
PIN#
PIN #
8
-
O
DESCRIPTION
UART channel B Receiver Ready (active low). This output provides the RX
FIFO/RHR status for receive channel B. This pin is only available on the 48pin TQFP package. If it is not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
35
38
O
UART channel A Transmit Data. If it is not used, leave it unconnected.
RXA
36
39
I
UART channel A Receive Data. Normal receive data input must idle at logic 1
condition. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor.
RTSA#
33
36
O
UART channel A Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control, see EFR[6],
MCR[1] and IER[6]. If it is not used, leave it unconnected.
CTSA#
38
40
I
UART channel A Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7] and IER[7]. This input should
be connected to VCC when not used.
DTRA#
34
37
O
UART channel A Data-Terminal-Ready (active low) or general purpose output.
If it is not used, leave it unconnected.
DSRA#
39
41
I
UART channel A Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
CDA#
40
42
I
UART channel A Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
RIA#
41
43
I
UART channel A Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
TXB
22
26
O
UART channel B Transmit Data. If it is not used, leave it unconnected.
RXB
21
25
I
UART channel B Receive Data. Normal receive data input must idle at logic 1
condition. If it is not used, tie it to VCC or pull it high via a 100k ohm resistor.
RTSB#
18
23
O
UART channel B Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control, see EFR[6],
MCR[1] and IER[6]. If it is not used, leave it unconnected.
CTSB#
24
28
I
UART channel B Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7] and IER[7]. This input should
be connected to VCC when not used.
DTRB#
23
27
O
UART channel B Data-Terminal-Ready (active low) or general purpose output.
If it is not used, leave it unconnected.
DSRB#
25
29
I
UART channel B Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
CDB#
26
30
I
UART channel B Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
Pin Description
NAME
48-TQFP 44-PLCC
TYPE
PIN#
PIN #
DESCRIPTION
RIB#
27
31
I
UART channel B Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect on
the UART.
MFA#
32
35
O
Multi-Function Output Channel A. This output pin can function as the OP2A#,
BAUDOUTA#, or RXRDYA# pin. One of these output signal functions can be
selected by the user programmable bits 1-2 of the Alternate Function Register
(AFR). These signal functions are described as follows:
1) OP2A# - When OP2A# (active low) is selected, the MF# pin is a logic 0
when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a
logic 1 condition after a reset or power-up.
2) BAUDOUTA# - When BAUDOUTA# function is selected, the 16X Baud rate
clock output is available at this pin.
3) RXRDYA# - RXRDYA# (active low) is intended for monitoring DMA data
transfers. If using the 48-TQFP package, this output is already available at pin
31.
If it is not used, leave it unconnected.
MFB#
14
19
O
Multi-Function Output ChannelB. This output pin can function as the OP2B#,
BAUDOUTB#, or RXRDYB# pin. One of these output signal functions can be
selected by the user programmable bits 1-2 of the Alternate Function Register
(AFR). These signal functions are described as follows:
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is a logic 0
when MCR bit-3 is set to a logic 1 (see MCR bit-3). MCR bit-3 defaults to a
logic 1 condition after a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud rate
clock output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data
transfers. If using the 48-TQFP package, this output is already available at pin
8.
If it is not used, leave it unconnected.
ANCILLARY SIGNALS
XTAL1
5
11
I
Crystal or external clock input.
XTAL2
7
13
O
Crystal or buffered clock output.
RESET
16
21
I
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will reset the
internal registers and all outputs. The UART transmitter output will be held at
logic 1, the receiver input will be ignored and outputs are reset during reset
period (see External Reset Conditions).
VCC
29, 42
44, 33
Pwr 2.25V to 5.5V power supply. All input pins are 5V tolerant.
GND
6, 17
22, 12
Pwr Power supply common, ground.
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
Pin Description
NAME
NC
48-TQFP 44-PLCC
TYPE
PIN#
PIN #
19, 37
-
-
DESCRIPTION
Not Connected Internally.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
1.0 PRODUCT DESCRIPTION
The XR16L2552 (L2552) provides serial asynchronous receive data synchronization, parallel-to-serial and
serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are
necessary for converting the serial data stream into parallel data that is required with digital data systems.
Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to
form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry
to provide all these functions is fairly complex especially when manufactured on a single integrated silicon
chip. The L2552 represents such an integration with greatly enhanced features. The L2552 is fabricated with
an advanced CMOS process.
Transmit and Receive FIFOs (16 Bytes each)
The L2552 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C2450. The L2552 is designed to work with low voltage supplies and
high performance data communication systems, that require fast data processing time. Increased performance
is realized in the L2552 by the transmit and receive FIFO’s. This allows the external processor to handle more
networking tasks within a given time. For example, the ST16C2450 without a receive FIFO, will require
unloading of the RHR in 93 microseconds (This example uses a character length of 11 bits, including start/stop
bits at 115.2 Kbps). This means the external CPU will have to service the receive FIFO less than every 100
microseconds. However with the 16 byte FIFO in the L2552, the data buffer will not require unloading/loading
for 1.53 ms. This increases the service interval giving the external CPU additional time for other applications
and reducing the overall UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger
interrupt levels is uniquely provided for maximum data throughput performance especially when operating in a
multi-channel environment. The FIFO memory greatly reduces the bandwidth requirement of the external
controlling CPU, increases performance, and reduces power consumption.
Enhanced Features
The XR16L2552 integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has automatic RTS/CTS hardware flow control, automatic Xon/Xoff and
special character software flow control, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate
generator with a prescaler of divide by 1 or 4, and data rate up to 4 Mbps at 5V.
Data Rate
The L2552 is capable of operation up to 3.125 Mbps with a 50 MHz external clock. With a crystal or external
clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
The rich feature set of the L2552 is available through internal registers. Selectable receive FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power
on reset or an external reset, the L2552 is software compatible with the 16L2752 and 16C2852.
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L2552 data interface supports the Intel compatible types of CPUs and it is compatible
to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data
bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels
share the same data bus for host operations. The data bus interconnections are shown in Figure 3.
FIGURE 3.
XR16L2552 DATA BUS INTERCONNECTIONS
VCC
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A0
A1
DSRA#
CDA#
A2
RIA#
(OP2A#)
(BAUDOUTA#)
IOR#
IOW#
IOR#
IOW#
UART
Channel A
UART_INTA
INTA
UART_INTB
INTB
TXRDYA#
TXRDYA#
(RXRDYA#)
TXRDYB#
(RXRDYA#)
TXRDYB#
(RXRDYB#)
(RXRDYB#)
UART_RESET
RESET
DTRA#
RTSA#
CTSA#
RS-232 Serial Interface
TXB
CS#
CHSEL
UART_CS#
UART_CHSEL
VCC
TXA
RXA
RXB
UART
Channel B
DTRB#
RTSB#
CTSB#
DSRB#
RS-232 Serial Interface
CDB#
RIB#
(OP2B#)
(BAUDOUTB#)
GND
Pins in parentheses become available through the MF# pin. MF# A/B becomes RXRDY# A/B when AFR[2:1] = '10'. MF# A/B becomes OP2# A/B
when AFR[2:1] = '00'. MF# A/B becomes BAUDOUT# A/B when AFR[1:0] = '01'. RXRDY# pins available on 48-TQFP package.
.
2.2
5-Volt Tolerant Inputs
The L2552 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2552 is
operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial
transceiver that is operating at 5V.
2.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see the Table 13). An active high pulse of longer than 40 ns duration will be required to activate the
reset function in the device.
2.4
Device Identification and Revision
The L2552 provides a Device Identification code and a Device Revision code to distinguish the part from other
devices and revisions. To read the identification code from the part, it is required to set the baud rate generator
registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2552
and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means
revision A.
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
2.5
REV. 1.1.1
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select
the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,
send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown
in Table 1.
TABLE 1: CHANNEL A AND B SELECT
2.6
CS#
CHSEL
FUNCTION
1
X
UART de-selected
0
1
Channel A selected
0
0
Channel B selected
Channel A and B Internal Registers
Each UART channel in the L2552 has a set of enhanced registers for controlling, monitoring and data loading
and unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabilities, the L2552 offers enhanced feature registers (AFR,
EFR, Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, automatic Xon/Xoff
software flow control, and simultaneous writes to both channels. All the register functions are discussed in full
detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 21.
2.7
Simultaneous Write to Channel A and B
During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the
CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability
allow the registers in both UART channels to be modified concurrently, saving individual channel initialization
time. Caution should be exercised, however, when using this capability. Any in-process serial data transfer
may be disrupted by changing an active channel’s mode.
2.8
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output
pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode
operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for
more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1).
When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the L2552 is
placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block
sequence determined by the programmed trigger level. The following table show their behavior. Also see
Figure 18 through Figure 23.
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B 0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B 0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
2.9
INTA and INTB Ouputs
The INTA and INTB interrupt outputs change according to the operating mode and enahnced features setup.
Table 3 and Table 4 summarize the operating behavior for the transmitter and receiver. Also see Figure 18
through Figure 23.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)
INTA/B Pin
0 = a byte in THR
1 = THR empty
FCR BIT-0 = 1
(FIFO ENABLED)
0 = at least 1 byte in FIFO
1 = FIFO empty
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
INTA/B Pin
2.10
0 = no data
1 = 1 byte
FCR BIT-0 = 1
(FIFO ENABLED)
0 = FIFO below trigger level
1 = FIFO above trigger level
Crystal Oscillator or External Clock Input
The L2552 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R2
500 KΩ − 1 MΩ
1.8432 MHz
to
24 MHz
Y1
C1
22-47 pF
R1
0-120 Ω
(Optional)
C2
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 2), with an external 500kΩ to
1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
2.11
Programmable Baud Rate Generator
A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel
control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up to 24
MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as
shown in Figure 5) it can extend its operation up to 64 MHz (4Mbps serial data rate) at room temperature and
5.0V.
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
vcc
External Clock
XTAL1
gnd
VCC
R1
2K
XTAL2
10
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock
operating frequency over power supply voltage chart in Figure 6.
XTAL1 External Clock Frequency in MHz.
FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESISTOR ON XTAL2 PIN TO INCREASE OPERATING SPEED
Operating frequency for XR16L2552
with external clock and a 2K ohms
pull-up resistor on XTAL2 pin.
80
-40oC
25oC
85oC
70
60
50
40
30
3.0 3.5 4.0 4.5 5.0 5.5
Suppy Voltage
The L2552 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides this 16X clock by
any divisor from 1 to 216 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 or External clock frequency ) / (serial data rate x 16)
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
400
2304
900
09
00
0
2400
384
180
01
80
0
4800
192
C0
00
C0
0
9600
96
60
00
60
0
19.2k
48
30
00
30
0
38.4k
24
18
00
18
0
76.8k
12
0C
00
0C
0
11
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
153.6k
6
06
00
06
0
230.4k
4
04
00
04
0
460.8k
2
02
00
02
0
921.6k
1
01
00
01
0
2.12
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.12.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.12.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Data
Byte
16X
Clock
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
Transmit Shift Register (TSR)
M
S
B
L
S
B
TXNOFIFO1
2.12.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when the FIFO and the TSR
become empty.
12
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Data Byte
Transm it
FIFO
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
16X Clock
Transm it Data Shift Register
(TSR)
T XF IF O 1
2.13
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit
on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an
internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer
is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt
when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.74.6 character times. The RHR interrupt is enabled by IER bit-0.
2.13.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4
13
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X Clock
Receive Data Shift
Register (RSR)
Error
Tags in
LSR bits
4:2
Receive
Data Byte
and Errors
Receive Data
Holding Register
(RHR)
Data Bit
Validation
Receive Data Characters
RHR Interrupt (ISR bit-2)
RXFIFO1
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
16 bytes by 11-bit
wide
FIFO
Error Tags
(16-sets)
Data falls to 4
Receive
Data FIFO
FIFO Trigger=8
Error Tags in
LSR bits 4:2
Data fills to 14
Receive Data
Byte and Errors
Receive Data Characters
Example
:
- RX FIFO trigger level selected at 8 bytes
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
Receive
Data
RXFIFO1
14
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
2.14
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 11):
• Enable auto RTS flow control using EFR bit-6.
• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.15
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 11):
• Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the CTS#
pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as the stop
bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-asserted
(LOW), indicating more data may be sent.
15
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART
UARTA
Remote UART
UARTB
RXA
Receiver FIFO
Trigger Reached
RTSA#
Auto RTS
Trigger Level
Receiver FIFO
Trigger Reached
RTSB#
Assert RTS# to Begin
Transmission
1
ON
Auto RTS
Trigger Level
10
OFF
ON
7
2
CTSB#
Auto CTS
Monitor
RXB
CTSA#
Auto CTS
Monitor
Transmitter
CTSB#
TXA
Transmitter
RTSA#
TXB
ON
3
8
OFF
6
Suspend
11
ON
TXB
Data Starts
4
Restart
9
RXA FIFO
INTA
(RXA FIFO
Interrupt)
Receive
RX FIFO
Data
Trigger Level
5
RTS High
Threshold
RTS Low
Threshold
12
RX FIFO
Trigger Level
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
16
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
2.16
Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 12), the L2552 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the L2552 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the L2552 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the L2552 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 12) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are
selected, the L2552 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the L2552 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L2552 sends the
Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)
after the receive FIFO crosses the programmed trigger level. To clear this condition, the L2552 will transmit the
programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed
trigger level. See Table 6 below.
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
RX TRIGGER LEVEL
INT PIN ACTIVATION
XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
1
1
1*
0
4
4
4*
1
8
8
8*
4
14
14
14*
8
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2
characters); for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting.
2.17
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The L2552 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.
17
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
2.18
REV. 1.1.1
Infrared Mode
The L2552 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data
Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit
wide HIGH-pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the
infrared LED, hence reduces the power consumption. See Figure 12 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 12.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
TX Data
0
1
0
1
0
Stop
Start
Data Bits
1
0
1
1
0
Transmit
IR Pulse
(TX Pin)
1/2 Bit Time
Bit Time
3/16 Bit Time
IrEncoder-1
Receive
IR Pulse
(RX pin)
Bit Time
1/16 Clock Delay
1
0
1
0
0
Data Bits
1 1
0
1
Stop
0
Start
RX Data
Character
IRdecoder-
18
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
2.19
Sleep Mode with Auto Wake-Up
The L2552 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used.
All of these conditions must be satisfied for the L2552 to enter sleep mode:
■
■
■
■
■
no interrupts pending for both channels of the L2552 (ISR bit-0 = 1)
divisor is a non-zero value (ie. DLL = 0x1)
sleep mode of both channels are enabled (IER bit-4 = 1)
modem inputs are not toggling (MSR bits 0-3 = 0)
RX input pins are idling at a logic 1
The L2552 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The L2552 resumes normal operation by any of the following:
■
■
■
a receive data start bit transition (logic 1 to 0)
a data byte is loaded to the transmitter, THR or FIFO
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the L2552 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the L2552 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
an interrupt is pending from channel A or B. The L2552 will stay in the sleep mode of operation until it is
disabled by setting IER bit-4 to a logic 0.
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the
L2552 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 36. If the input lines are floating or are toggling while the L2552 is in sleep mode, the
current can be up to 100 times more. If any of those signals are toggling or floating, then an external buffer
would be required to keep the address, data and control lines steady to achieve the low current. As an
alternative, please refer to the XR16L2551 with the PowerSave feature that eliminates any unnecessary
external buffer.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. The number of characters lost during the restart also depends on your
operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep
RX A/B inputs idling at logic 1 or “marking” condition during sleep mode to avoid receiving a “break” condition
upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)
are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a
47k-100k ohm pull-up resistor on the RXA and RXB pins.
19
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
2.20
REV. 1.1.1
Internal Loopback
The L2552 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto RTS/
CTS is not supported during internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
VCC
TXA/TXB
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
RXA/RXB
VCC
RTSA#/RTSB#
RTS#
Modem / General Purpose Control Logic
Internal Data Bus Lines and Control Signals
MCR bit-4=1
CTS#
CTSA#/CTSB#
VCC
DTRA#/DTRB#
DTR#
DSR#
DSRA#/DSRB#
OP1#
RI#
VCC
RIA#/RIB#
(OP2A#/OP2B#)
OP2#
CD#
CDA#/CDB#
20
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the L2552 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CS# and CHSEL selecting the channel. The registers are 16C550 compatible. The complete
register set is shown in Table 7 and Table 8.
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0
0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
0
0 0
DLL - Div Latch Low Byte
Read/Write
0
0 1
DLM - Div Latch High Byte
Read/Write
0
1 0
AFR - Alternate Function Register
Read/Write
0
0 0
DREV - Device Revision
Read/Write
0
0 1
DVID - Device ID
Read/Write
0
0 1
IER - Interrupt Enable Register
Read/Write
0
1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0
1 1
LCR - Line Control Register
Read/Write
1
0 0
MCR - Modem Control Register
Read/Write
1
0 1
LSR - Line Status Register
Reserved
Read-only
Write-only
1
1 0
MSR - Modem Status Register
Reserved
Read-only
Write-only
1
1 1
SPR - Scratch Pad Register
Read/Write
LCR[7] = 0
LCR[7] = 1, LCR ≠ 0xBF
LCR[7] = 1, LCR ≠ 0xBF,
DLL = 0x00, DLM = 0x00
LCR[7] = 0
LCR ≠ 0xBF
ENHANCED REGISTERS
0
1 0
EFR - Enhanced Function Register
Read/Write
1
0 0
Xon-1 - Xon Character 1
Read/Write
1
0 1
Xon-2 - Xon Character 2
Read/Write
1
1 0
Xoff-1 - Xoff Character 1
Read/Write
1
1 1
Xoff-2 - Xoff Character 2
Read/Write
21
LCR = 0xBF
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
.
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
000
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
000
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
IER
RD/WR
0/
0/
0/
0/
CTS Int. RTS Int.
Enable Enable
Xoff Int.
Enable
Sleep
Mode
Enable
FIFOs
FIFOs
Enabled Enabled
0/
0/
INT
Source
Bit-5
INT
Source
Bit-4
0
0
DMA
Mode
Enable
TX
FIFO
Reset
Even
Parity
Parity
Enable
Stop
Bits
010
ISR
RD
RX FIFO RX FIFO
Trigger Trigger
Modem RX Line
TX
RX
Stat.
Stat.
Empty
Data
Int.
Int.
Int
Int.
Enable Enable Enable Enable
INT
INT
INT
INT
Source Source Source Source
Bit-3
Bit-2
Bit-1
Bit-0
010
FCR
WR
011
LCR
RD/WR
Divisor
Enable
Set TX
Break
Set Parity
100
MCR
RD/WR
0/
0/
0/
RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX
Break
RX
Framing
Error
RX
Parity
Error
RX
Overrun
Error
RX
Data
Ready
BRG
Prescaler
101
LSR
RD
RX
FIFO
Reset
LCR[7] = 0
FIFOs
Enable
Word
Word
Length Length
Bit-1
Bit-0
Internal OP2#
Rsvd
RTS# DTR#
Lopback Output (OP1#) Output Output
IR Mode XonAny Enable Control
Control Control
ENable
110
MSR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
111
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR ≠ 0xBF
Baud Rate Generator Divisor
000
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
010
AFR
RD/WR
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
000
DREV
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
001
DVID
RD
0
0
0
0
0
0
1
0
22
RXRDY# Baudout# Concurrent Write
Select
Select
LCR[7] = 1
LCR ≠ 0xBF
LCR[7]=1
LCR ≠ 0xBF
DLL=0x00
DLM=0x00
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2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
MCR[7:5]
Software
Flow
Cntl
Bit-3
Software
Flow
Cntl
Bit-2
Software
Flow
Cntl
Bit-1
Software
Flow
Cntl
Bit-0
COMMENT
Enhanced Registers
010
EFR
RD/WR
Auto
CTS
Enable
Auto
RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
100
XON1 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
101
XON2 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
110
XOFF1 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
111
XOFF2 RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR=0XBF
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
Receive Holding Register (RHR) - Read- Only
See “Receiver” on page 13.
4.2
Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 12.
4.3
Baud Rate Generator Divisors (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’. See
“Programmable Baud Rate Generator” on page 10. for more details.
4.4
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.4.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
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4.4.2
REV. 1.1.1
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L2552 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates transmit FIFO is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the TX FIFO becomes empty.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the RTS# interrupt (default).
• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
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IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the CTS# interrupt (default).
• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.5
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.5.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• Receive Xoff/Special character is by detection of a Xoff or Special character.
• CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control enabled by
EFR bit-7.
• RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control enabled by
EFR bit-6.
4.5.2
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that
generated the interrupt(s) has been emptied or cleared from FIFO).
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
• Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
• Special character interrupt is cleared by a read to ISR or after the next character is received.
• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
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REV. 1.1.1
]
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
1
1
0
0
RXRDY (Receive Data Time-out)
3
0
0
0
1
0
0
RXRDY (Received Data Ready)
4
0
0
0
0
1
0
TXRDY (Transmit Ready)
5
0
0
0
0
0
0
MSR (Modem Status Register)
6
0
1
0
0
0
0
RXRDY (Received Xoff or Special character)
7
1
0
0
0
0
0
CTS#, RTS# change of state
-
0
0
0
0
0
1
None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).
ISR[4]: Xoff or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff interrupt, it can be cleared by a read to the ISR or when an Xon
character is received. If it is a special character interrupt, it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed
state from low to high.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.6
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
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FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
• Logic 0 = Normal Operation (default).
• Logic 1 = DMA Mode.
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections.
TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
0
0
1
1
4.7
FCR
RECEIVE
BIT-6 TRIGGER LEVEL
0
1
0
1
1 (default)
4
8
14
COMPATIBILITY
Table-A. 16C550,
16C2550, 16C2552,
16C554, 16C580 compatible.
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
BIT-2
WORD
27
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REV. 1.1.1
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR[5] = logic 0, parity is not forced (default).
• LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
• LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark,
“1”
1
1
1
Forced parity to
space, “0”
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.8
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
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MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force DTR# output to a logic 1 (default).
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: OP1# Output
OP1# is not available as an output pin on the L2552. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output
OP2# is available as an output pin on the L2552 when AFR[2:1] = ‘00’. In the Loopback Mode, MCR[3] is used
to write the state of the modem CD# interface signal. Also see pin descriptions for MF# pins.
• Logic 0 = Forces OP2# output to a logic 1 (default).
• Logic 1 = Forces OP2# output to a logic 0.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable
• Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the L2552 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
• Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)
• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.9
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
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LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Tag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from
the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is
empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.
4.10
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits
are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general
purpose inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
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MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
Normally this bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to
the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem
interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.11
Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12
Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
• Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.13
Alternate Function Register (AFR) - Read/Write
This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
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AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
• Logic 0 = No concurrent write (default).
• Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
BIT-2
BIT-1
MF# FUNCTION
0
0
OP2# (default)
0
1
BAUDOUT#
1
0
RXRDY#
1
1
Reserved
AFR[7:3]: Reserved
All are initialized to logic 0.
4.14
Device Identification Register (DVID) - Read Only
This register contains the device ID (0x02 for XR16L2552). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.15
Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.16
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 12). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
32
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
TABLE 12: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1, Xoff1
0
1
X
X
Transmit Xon2, Xoff2
1
1
X
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1, Xoff1
X
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 to be modified.
After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature
prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 are
saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, and MCR bits 5-7are set to a
logic 0 to be compatible with ST16C550 mode (default).
• Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled (default).
• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5. Special character interrupts are cleared automatically after the next
received character.
33
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at the next upper trigger level. RTS# will return to a logic 0 when FIFO data falls
below the next lower trigger level. The RTS# output must be asserted (logic 0) before the auto RTS can take
effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.
• Logic 0 = Automatic RTS flow control is disabled (default).
• Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
• Logic 0 = Automatic CTS flow control is disabled (default).
• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.17
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters XOFF1, XOFF2, XON1, and
XON2. For more details, see Table 6.
34
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
TABLE 13: UART RESET CONDITIONS FOR CHANNELS A AND B
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
AFR
Bits 7-0 = 0x00
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX
Logic 1
MF#
Logic 1
RTS#
Logic 1
DTR#
Logic 1
TXRDY#
Logic 0
INT
Logic 0
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (48-TQFP)
theta-ja =59oC/W, theta-jc = 16oC/W
Thermal Resistance (44-PLCC)
theta-ja = 50oC/W, theta-jc = 21oC/W
35
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
7 Volts
Voltage at Any Pin
GND-0.3 V to VCC+0.3 V
Operating Temperature
-40o to +85oC
Storage Temperature
-65o to +150oC
Package Dissipation
500 mW
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: 40o to +85oC for industrial grade package, Vcc is 2.25 to 5.5V
SYMBOL
PARAMETER
LIMITS
2.5V
MIN
MAX
LIMITS
3.3V
MIN
MAX
LIMITS
5.0V
MIN
MAX
UNITS
CONDITIONS
VILCK
Clock Input Low Level
-0.3
0.2
-0.3
0.6
-0.5
0.6
V
VIHCK
Clock Input High Level
2.0
5.5
2.4
5.5
3.0
5.5
V
VIL
Input Low Voltage
-0.3
0.6
-0.3
0.8
-0.5
0.8
V
VIH
Input High Voltage
2.0
5.5
2.0
5.5
2.2
5.5
V
VOL
Output Low Voltage
0.4
V
V
V
IOL = 6 mA
V
V
V
IOH = -6 mA
0.4
0.4
VOH
Output High Voltage
2.4
2.0
1.8
IIL
Input Low Leakage Current
±10
±10
±10
uA
IIH
Input High Leakage Current
±10
±10
±10
uA
CIN
Input Pin Capacitance
5
5
5
pF
ICC
Power Supply Current
1
1.3
3
mA
Sleep Current
6
15
30
uA
ISLEEP
IOL = 4 mA
IOL = 2 mA
IOH = -1 mA
IOH = -400 uA
See Test 1
Test 1: The following inputs must remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0D7, IOR#, IOW#, CS#, CHSEL, and all modem inputs. Also, RXA and RXB inputs must idle at logic 1 state
while asleep. Floating inputs will result in sleep currents in the mA range. For PowerSave feature that isolates
address, data and control signals, please see the XR16L2551 datasheet.
36
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
AC ELECTRICAL CHARACTERISTICS
Unless Otherwise Noted: TA=-40o to +85oC, Vcc is 2.25V to 5.5V,
70 pF load where applicable
SYMBOL
LIMITS
2.5
PARAMETER
MIN
-
Crystal Frequency
LIMITS
3.3
MAX
MIN
16
31
LIMITS
5.0
MAX
MIN
20
17
UNIT
MAX
24
CLK
External Clock Low/High Time
OSC
External Clock Frequency
TAS
Address Setup Time
10
10
10
ns
TAH
Address Hold Time
10
10
10
ns
TCS
Chip Select Width
150
75
50
ns
TRD
IOR# Strobe Width
150
75
50
ns
TDY
Read Cycle Delay
150
75
50
ns
TRDV
Data Access Time
TDD
Data Disable Time
0
TWR
IOW# Strobe Width
150
75
50
ns
TDY
Write Cycle Delay
150
75
50
ns
TDS
Data Setup Time
25
20
15
ns
TDH
Data Hold Time
15
10
10
ns
16
30
125
45
10
MHz
50
70
0
30
ns
0
MHz
45
ns
30
ns
TWDO
Delay From IOW# To Output
150
75
50
ns
TMOD
Delay To Set Interrupt From MODEM Input
150
75
50
ns
TRSI
Delay To Reset Interrupt From IOR#
150
75
50
ns
TSSI
Delay From Stop To Set Interrupt
1
1
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
150
75
50
ns
TSI
Delay From Stop To Interrupt
150
75
50
ns
TINT
Delay From Initial INT Reset To Transmit
Start
24
Bclk
TWRI
Delay From IOW# To Reset Interrupt
TSSR
Delay From Stop To Set RXRDY#
TRR
8
24
8
24
8
150
75
50
ns
1
1
1
Bclk
Delay From IOR# To Reset RXRDY#
150
75
50
ns
TWT
Delay From IOW# To Set TXRDY#
150
75
50
ns
TSRT
Delay From Center of Start To Reset TXRDY#
8
8
8
Bclk
37
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
AC ELECTRICAL CHARACTERISTICS
Unless Otherwise Noted: TA=-40o to +85oC, Vcc is 2.25V to 5.5V,
70 pF load where applicable
SYMBOL
LIMITS
2.5
PARAMETER
MIN
TRST
Reset Pulse Width
40
N
Baud Rate Divisor
1
Bclk
LIMITS
3.3
MAX
MIN
LIMITS
5.0
MAX
40
216-1
Baud Clock
1
MIN
UNIT
MAX
40
216-1
1
ns
216-1
16X of data rate
Hz
FIGURE 14. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
IOW #
Active
T W DO
RTS#
DTR#
Change of state
Change of state
CD#
CTS#
DSR#
Change of state
Change of state
T MO D
T M OD
INT
Active
Active
Active
T RSI
IOR#
Active
Active
Active
T M OD
Change of state
RI#
38
-
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
FIGURE 16. DATA BUS READ TIMING
A0-A2
Valid Address
TAS
TCS
Valid Address
TAS
TAH
TAH
TCS
CSA#/
CSB#
TDY
TRD
TRD
IOR#
TDD
TRDV
D0-D7
TDD
TRDV
Valid Data
Valid Data
RDTm
FIGURE 17. DATA BUS WRITE TIMING
A0-A2
Valid Address
TAS
TCS
Valid Address
TAS
TAH
TCS
TAH
CSA#/
CSB#
TDY
TWR
TWR
IOW#
TDS
D0-D7
TDH
Valid Data
TDS
TDH
Valid Data
16Write
39
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
RX
Start
Bit
Stop
Bit
D0:D7
INT
D0:D7
D0:D7
TSSR
TSSR
TSSR
1 Byte
in RHR
1 Byte
in RHR
1 Byte
in RHR
TSSR
TSSR
Active
Data
Ready
Active
Data
Ready
RXRDY#
TRR
TSSR
Active
Data
Ready
TRR
TRR
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
TX
(Unloading)
Start
Bit
IER[1]
enabled
Stop
Bit
D0:D7
D0:D7
ISR is read
D0:D7
ISR is read
ISR is read
INT*
TWRI
TWRI
TWRI
TSRT
TSRT
TSRT
TXRDY#
TWT
TWT
TWT
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
40
TXNonFIFO
xr
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
Start
Bit
RX
S D0:D7
S D0:D7 T
D0:D7
Stop
Bit
S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
RX FIFO drops
below RX
Trigger Level
TSSI
INT
FIFO
Empties
TSSR
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RXRDY#
First Byte is
Received in
RX FIFO
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXINTDMA#
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
Start
Bit
RX
Stop
Bit
S D0:D7
S D0:D7 T
D0:D7
S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
RX FIFO drops
below RX
Trigger Level
TSSI
INT
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
FIFO
Empties
TSSR
RXRDY#
TRRI
TRR
IOR#
(Reading data out
of RX FIFO)
RXFIFODMA
41
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
Stop
Bit
Start
Bit
S D0:D7 T
(Unloading)
IER[1]
enabled
Last Data Byte
Transmitted
T S D0:D7 T S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
TSRT
ISR is read
TX FIFO no
longer empty
INT*
TSI
TWRI
TX FIFO
Empty
Data in
TX FIFO
TXRDY#
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA#
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
Stop
Bit
Start
Bit
S D0:D7 T
(Unloading)
IER[1]
enabled
Last Data Byte
Transmitted
ISR is read
S D0:D7 T
TSRT
TX FIFO no
longer empty
INT*
T S D0:D7 T S D0:D7 T
S D0:D7 T S D0:D7 T
TSI
TWRI
TXRDY#
TX FIFO
Empty
At least 1
empty location
in FIFO
TX FIFO
Full
TWT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
42
TXDMA
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D
D1
36
25
24
37
D1
13
48
1
2
1
B
e
A2
C
A
Seating
Plane
α
A1
L
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.039
0.047
1.00
1.20
A1
0.002
0.006
0.05
0.15
A2
0.037
0.041
0.95
1.05
B
0.007
0.011
0.17
0.27
C
0.004
0.008
0.09
0.20
D
0.346
0.362
8.80
9.20
D1
0.272
0.280
6.90
7.10
e
0.020 BSC
0.50 BSC
L
0.018
0.030
0.45
0.75
α
0°
7°
0°
7°
43
D
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
PACKAGE DIMENSIONS (44 PIN PLCC)
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
C
D
D1
2 1
45° x H2
Seating Plane
45° x H1
A2
44
B1
D
D1
B
D3
e
R
D3
A1
A
Note: The control dimension is the millimeter column
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.165
0.180
4.19
4.57
A1
0.090
0.120
2.29
3.05
A2
0.020
---
0.51
---
B
0.013
0.021
0.33
0.53
B1
0.026
0.032
0.66
0.81
C
0.008
0.013
0.19
0.32
D
0.685
0.695
17.40
17.65
D1
0.650
0.656
16.51
16.66
D2
0.590
0.630
14.99
16.00
D3
0.500 typ.
12.70 typ.
e
0.050 BSC
1.27 BSC
H1
0.042
0.056
1.07
1.42
H2
0.042
0.048
1.07
1.22
R
0.025
0.045
0.64
1.14
44
D2
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
REVISION HISTORY
DATE
REVISION
DESCRIPTION
November 2002 P1.0.0
Preliminary Datasheet.
March 2003
P1.0.1
Updated AC Electrical Characteristics. Updated register set with enhanced features.
May 2003
P1.0.2
Added patent number to first page.
June 2003
P1.0.3
Added Device Status to Ordering Information.
July 2003
P1.0.4
Updated AC Electrical Characteristics.
September 2003 1.0.0
Final Production Release. Updated 5V tolerance information.
September 2004
1.1.0
Corrected A2 and A0 pin numbers for PLCC-44 package in Pin Descriptions. Added
Device Revision and Device ID registers and descriptions.
May 2005
1.1.1
Updated the Data Access Time (TRDV) in AC Electrical Characteristics.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet May 2005.
Send your UART technical inquiry with technical details to hotline: [email protected]
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
45
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XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ................................................................................................................................................1
FEATURES .....................................................................................................................................................1
FIGURE 1. XR16L2552 BLOCK DIAGRAM ......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENTS ................................................................................................................................................... 2
ORDERING INFORMATION.................................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 PRODUCT DESCRIPTION .....................................................................................................................6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................7
2.1 CPU INTERFACE .............................................................................................................................................. 7
FIGURE 3.
2.2
2.3
2.4
2.5
XR16L2552 DATA BUS INTERCONNECTIONS .................................................................................................................. 7
5-VOLT TOLERANT INPUTS ...........................................................................................................................
DEVICE RESET ................................................................................................................................................
DEVICE IDENTIFICATION AND REVISION .....................................................................................................
CHANNEL A AND B SELECTION ....................................................................................................................
7
7
7
8
TABLE 1: CHANNEL A AND B SELECT ............................................................................................................................................... 8
2.6 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 8
2.7 SIMULTANEOUS WRITE TO CHANNEL A AND B ......................................................................................... 8
2.8 DMA MODE ....................................................................................................................................................... 8
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE ............................................................................................. 9
2.9 INTA AND INTB OUPUTS ................................................................................................................................ 9
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER ........................................................................................................ 9
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................... 9
2.10 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 9
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS ............................................................................................................................... 10
2.11 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 10
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 10
FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESISTOR ON XTAL2 PIN TO INCREASE OPERATING SPEED
11
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 11
2.12 TRANSMITTER ............................................................................................................................................. 12
2.12.1
2.12.2
FIGURE 7.
2.12.3
FIGURE 8.
TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ....................................................................................... 12
TRANSMITTER OPERATION IN NON-FIFO MODE ................................................................................................ 12
TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 12
TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 12
TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 13
2.13 RECEIVER .................................................................................................................................................... 13
2.13.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 13
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 14
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 14
2.14 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................. 15
2.15 AUTO CTS FLOW CONTROL ..................................................................................................................... 15
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION ....................................................................................................... 16
2.16 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 17
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 17
2.17 SPECIAL CHARACTER DETECT ............................................................................................................... 17
2.18 INFRARED MODE ........................................................................................................................................ 18
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 18
2.19
2.20
SLEEP MODE WITH AUTO WAKE-UP ....................................................................................................... 19
INTERNAL LOOPBACK .............................................................................................................................. 20
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 20
3.0 UART INTERNAL REGISTERS ...........................................................................................................21
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS...................................................................................... 21
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1......................................... 22
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................23
4.1
4.2
4.3
4.4
RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ...............................................................................
TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................
BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE ...................................................
INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ..............................................................................
I
23
23
23
23
xr
XR16L2552
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.1
4.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 23
4.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 24
4.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 25
4.5.1 INTERRUPT GENERATION: ...................................................................................................................................... 25
4.5.2 INTERRUPT CLEARING: ........................................................................................................................................... 25
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 26
4.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 26
TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION ................................................................................................................... 27
4.7 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 27
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 28
4.8 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE
4.9 LINE STATUS REGISTER (LSR) - READ ONLY ...........................................................................................
4.10 MODEM STATUS REGISTER (MSR) - READ ONLY ..................................................................................
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................
4.12 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE ..............................................
4.13 ALTERNATE FUNCTION REGISTER (AFR) - READ/WRITE .....................................................................
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY ....................................................................
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY ..............................................................................
4.16 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................
28
29
30
31
31
31
32
32
32
TABLE 12: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 33
4.17 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 34
TABLE 13: UART RESET CONDITIONS FOR CHANNELS A AND B ......................................................................................... 35
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) ................................................ 35
ABSOLUTE MAXIMUM RATINGS ..................................................................................................................... 36
ELECTRICAL CHARACTERISTICS................................................................................ 36
DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 36
AC ELECTRICAL CHARACTERISTICS .............................................................................................................. 37
FIGURE 14.
FIGURE 15.
FIGURE 17.
FIGURE 16.
FIGURE 18.
FIGURE 19.
FIGURE 20.
FIGURE 21.
FIGURE 22.
FIGURE 23.
CLOCK TIMING............................................................................................................................................................. 38
MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 38
DATA BUS WRITE TIMING ............................................................................................................................................ 39
DATA BUS READ TIMING .............................................................................................................................................. 39
RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 40
TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 40
RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 41
RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 41
TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 42
TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 42
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM) .............................................. 43
PACKAGE DIMENSIONS (44 PIN PLCC) ....................................................................... 44
REVISION HISTORY ...................................................................................................................................... 45
TABLE OF CONTENTS ............................................................................................................ I
II