EXAR XR20V2172

XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
JULY 2008
REV. 1.0.1
GENERAL DESCRIPTION
FEATURES
The XR20V21721 (V2172) is a high performance two
channel universal asynchronous receiver and
transmitter (UART) with 64 byte TX and RX FIFOs, a
selectable I2C/SPI slave interface and RS232
transceiver. The V2172 operates from 3.3 to 5.5 volts.
The enhanced features in the V2172 include a
programmable fractional baud rate generator, an 8X
and 4X sampling rate that allows for a maximum baud
rate of 1 Mbps at 3.3V. The standard features include
16 selectable TX and RX FIFO trigger levels,
automatic hardware (RTS/CTS) and software (Xon/
Xoff) flow control, and a complete modem interface.
Onboard registers provide the user with operational
status and data error flags. An internal loopback
capability allows system diagnostics. The V2172 is
available in the 64-pin QFN.
• Selectable I2C/SPI Interface
• Meets true EIA/TIA-232-F Standards from +3.3V to
+5.5V operation
• Data rate up to 1 Mbps
• 45us sleep mode exit (charge pump to full power)
• ESD protection for RS-232 I/O pins at
+/-15kV - Human Body Model
■
+/-15kV - IEC 61000-4-2, Air-Gap Discharge
■
+/- 8kV - IEC 61000-4-2, Contact Discharge
• Full-featured UART
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
• Portable Appliances
• Battery-Operated Devices
• Cellular Data Devices
• Factory Automation and Process Controls
■
■
Fractional Baud Rate Generator
■
Transmit and Receive FIFOs of 64 bytes
■
16 Selectable TX and RX FIFO Trigger Levels
■
Automatic Hardware (RTS/CTS) Flow Control
■
Automatic Software (Xon/Xoff) Flow Control
■
Halt and Resume Transmission Control
■
Automatic sleep mode
■
General Purpose I/Os
■
Full modem interface
• 64-QFN packages
C1-
C1+
C2-
C2+
FAST
ACP
R_EN
VCC
GND
XTAL2
XTAL1
FIGURE 1. XR20V2172 BLOCK DIAGRAM
VR EF+
C rys ta l
O sc /B u ffe r
IR Q #
SDA
SCK
A 0 /C S A #
A 1 /S I
I2C/SPI Interface
I2 C /S P I#
UART Registers
RESET#
BRG
6 4 B yte
TX & RX
F IF O
C h a rg e P u m p
VR EFTXDA
RXDA
TXA
RXA
5K
RTSA#
M odem
I/O s
RTSA
DTRA#
CTSA#
5K
DSRA#
5K
R IA #
5K
CDA#
C hannel A
C hannel B
SO
5K
DSRA
R IA
CDA
C h A T ra n sc e iv e r
CDB#
R IB #
DSRB#
CTSB#
D TR B#
RTSB#
TXB
RXB
C hannel B
T ra n sc e ive r
RXB_SEL
UART
DTRA
CTSA
CDB
R IB
DSRB
CTSB
DTRB
RTSB
TXDB
RXDB
TXB
RXB
R S -2 3 2 T ra n s ce iv e r
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
VREF+
RESET#
C1+
C1-
N.C.
52
51
50
49
54
53
N.C.
VCC
55
A0/CS#
RIA
58
C3
A1/SI
60
59
56
CDA
61
57
CDB
I2C/SPI#
62
SO
CTSA
64
63
FIGURE 2. PIN OUT ASSIGNMENT
GND
1
48
N.C.
SDA
2
47
N.C.
N.C.
3
46
N.C.
CTSB
4
45
VCC
RTSB
5
44
C2+
RXB_SEL
6
43
C2-
RXB
7
42
TXDA
TXB
8
N.C.
XR20V2172
64-pin QFN
30
31
32
N.C.
N.C.
N.C.
SCK
N.C.
33
29
16
28
GND
RTSA
N.C.
RXDB
34
26
15
27
GND
XTAL1
N.C.
35
TXDB
14
25
N.C.
DSRB
VREF-
36
24
13
ACP
N.C.
RIB
23
37
N.C.
12
21
IRQ#
DTRB
22
RXDA
38
N.C.
39
11
GND
10
N.C.
20
N.C.
FAST 19
DSRA
R_EN
40
18
DTRA
9
XTAL2 17
41
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
DEVICE STATUS
XR20V2172IL64
64-pin QFN
-40°C to +85°C
Active
2
XR20V2172
REV. 1.0.1
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
PIN DESCRIPTIONS
Pin Description
64-QFN
PIN #
TYPE
DESCRIPTION
I2C/SPI#
61
I/O
I2C-bus or SPI interface select. I2C-bus interface is selected if this pin is
HIGH. SPI interface is selected if this pin is LOW. This pin is not 5V tolerant.
SDA
2
I/O
I2C-bus data input/output (open-drain). If SPI configuration is selected,
then this pin is undefined and must be connected to VCC. This pin is not
5V tolerant.
SCK
33
I
I2C-bus or SPI serial input clock.
When the I2C-bus interface is selected, the serial clock idles HIGH. When
the SPI interface is selected, the serial clock idles LOW. This pin is not 5V
tolerant.
A0/
CS#
57
I
I2C-bus device address select A0 or SPI chip select. If I2C-bus configuration is selected, this pin along with the A1 pin allows user to change the
device’s base address. If SPI configuration is selected, this pin is the SPI
chip select pin (Schmitt-trigger, active LOW). This pin is not 5V tolerant.
A1/
SI
59
I
I2C-bus device address select A1 or SPI data input pin. If I2C-bus onfiguration is selected, this pin along with A0 pin allows user to change the
device’s base address. If SPI configuration is selected, this pin is the SPI
data input pin. This pin is not 5V tolerant.
SO
64
O
SPI data output pin. If SPI configuration is selected then this pin is a
three-stateable output pin. If I2C-bus configuration is selected, this pin is
undefined and must be left unconnected.
IRQ#
38
OD
RESET#
52
I
NAME
I2C (SPI) INTERFACE
Interrupt output (open-drain, active LOW).
Reset (active LOW) - A longer than 40 ns LOW pulse on this pin will reset
the internal registers and all outputs. The UART transmitter output will be
idle and the receiver input will be ignored. This pin is not 5V tolerant.
SERIAL I/O INTERFACE (CMOS/TTL Voltage Levels)
RXB
7
I
UART Channel B Receive Data. This pin can be used to communicate
with external IR or RS-232 transceiver. This pin is not 5V tolerant.
TXB
8
O
UART Channel B Transmit Data. This pin can be used to communicate
with external IR or RS-232 transceiver.
MODEM OR SERIAL I/O INTERFACE (EIA-232/RS-232 Voltage Levels)
RXDA
RXDB
39
29
I
UART Receive Data. UART receive data input must idle LOW (< 1.5V).
This input has an internal pull-down resistor and can be left unconnected
when not used.
TXDA
TXDB
42
27
O
UART Transmit Data. The TX signal will be LOW (< 1.5V) during reset or
idle (no data).
RTSA
RTSB
28
5
O
UART Request-to-Send. This output must be asserted prior to using auto
RTS flow control, see EFR[6], MCR[1] and IER[6].
CTSA
CTSB
63
4
I
UART Clear-to-Send. It can be used for auto CTS flow control, see
EFR[7], MSR[4] and IER[7]. This input has an internal pull-down resistor
and can be left unconnected when not used.
3
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
Pin Description
NAME
64-QFN
PIN #
DTRA
DTRB
41
12
O
UART Data-Terminal-Ready. See MCR[0].
DSRA
DSRB
40
14
I
UART Data-Set-Ready. This input has an internal pull-down resistor and
can be left unconnected when not used. See MSR[5].
CDA
CDB
60
62
I
UART Carrier-Detect. This input has an internal pull-down resistor and
can be left unconnected when not used. See MSR[7].
RIA
RIB
58
13
I
UART Ring-Indicator. This input has an internal pull-down resistor and
can be left unconnected when not used. See MSR[6].
TYPE
DESCRIPTION
Ancillary signals (CMOS/TTL Voltage Levels)
XTAL1
15
I
Crystal or external clock input. This pin is not 5V tolerant.
XTAL2
17
O
Crystal or buffered clock output.
ACP
24
I
Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the
charge pump is shut off if the V2172 is already in partial sleep mode, i.e.
the crystal oscillator is stopped. This pin is 5V tolerant.
FAST
19
I
When FAST is HIGH, the maximum serial data rate is 1 Mbps.
When FAST is LOW, the maximum serial data rate is 250 Kbps. This pin
is 5V tolerant.
R_EN
20
I
When the supply voltage is < 3.6V, connect R_EN to VCC.
When the supply voltage is > 3.6V, connect R_EN to GND. This pin is 5V
tolerant.
RXB_SEL
6
I
When RXB_SEL is HIGH, RXB is the receive data input.
When RXB_SEL is LOW, RXDB is the receive data input. This pin is 5V
tolerant.
C2+
C2-
44
43
-
Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor
should be placed between these 2 pins.
C1+
C1-
51
50
-
Charge pump capacitors. As shown in Figure 1, a 0.1 uF capacitor
should be placed between these 2 pins.
C3
56
-
When the supply voltage is 3.3 V, C3 should be connected to VCC.
When the supply voltage is 5 V, C3 should be connected to a 1 uF capacitor to GND.
VREF-
25
Pwr
-5.0V generated by the charge pump.
VREF+
53
Pwr
+5.0V generated by the charge pump.
GND
1, 16, 21, 35
Pwr
Power supply common, ground.
VCC
45, 54
Pwr
3.3 to 5.5V power supply.
4
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
Pin Description
NAME
64-QFN
PIN #
TYPE
DESCRIPTION
-
PAD
Pwr
The center pad on the backside of the QFN packages is metallic and is
not electrically connected to anything inside the device. It must be soldered on to the PCB and may be optionally connected to GND on the
PCB. The thermal pad size on the PCB should be the approximate size of
this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB
thermal pad.
NC
3, 9, 10, 11, 18,
22, 23, 26, 30,
31, 32, 34, 36,
37, 46, 47, 48,
49, 55
-
No Connection.
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. For CMOS/TTL Voltage levels, ’LOW’
indicates a voltage in the range 0V to VIL and ’HIGH" indicates a voltage in the range VIH to VCC. For RS-232
input voltage levels, ’LOW’ is any voltage < -3V and ’HIGH’ is any voltage > 3V. For RS-232 output voltage levels,
’LOW’ is any voltage < -5V and ’HIGH’ is any voltage > 5V.
5
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
1.0 PRODUCT DESCRIPTION
The XR20V2172 (V2172) integrates a selectable I2C/SPI bus interface with an enhanced two channel
Universal Asynchronous Receiver and Transmitter (UART) and an RS-232 Transceiver. The configuration
register set is 16550 UART compatible for control, status and data transfer. Additionally, each channel of the
V2172 has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/
Xoff and special character software flow control, programmable transmit and receive FIFO trigger levels,
programmable fractional baud rate generator with a prescaler of divide by 1 or 4, data rate up to 1 Mbps, while
meeting all EIA RS-232F specifications. Additionally, the V2172 includes the ACP pin with which the user can
shut down the charge pump for the RS-232 drivers when the V2172 is already in sleep mode. The XR20V2172
is a 3.3 to 5.5V device. The V2172 is fabricated with an advanced CMOS process.
Enhanced Features
The V2172 UART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the industry standard 16C550. The V2172 is designed to work with low supply voltage and high
performance data communication systems, that require fast data processing time. Increased performance is
realized in the V2172 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow
control mechanism. This allows the external processor to handle more networking tasks within a given time.
For example, the 16C550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses
a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to
service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the V2172, the data buffer will
not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional
time for other applications and reducing the overall UART interrupt servicing time. In addition, the
programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided
for maximum data throughput performance especially when operating in a multi-channel system. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption. Finally, since the V2172 includes an RS-232 transceiver and a full-modem
interface, it can be connected to an RS-232 serial cable directly.
Data Rate
The V2172 is capable of operation up to 1 Mbps data rate using the 16X, 8X or 4X internal sampling clock rate.
The UART section can operate at much higher speeds, but the speed of the RS-232 transceiver is limited to
1Mbps beyond which the V2172 cannot comply with the EIA/TIA-232 electrical characteristics. The device can
operate either with a crystal on pins XTAL1 and XTAL2, or external clock source on XTAL1 pin.
RS-232 Interface
The V2172 includes RS-232 drivers/receivers for the modem interface. This feature eliminates the need for an
external RS-232 transceiver. The charge pump provides output voltages of +5V and -5V for its drivers over the
3.3V to 3.63V power supply voltage range. The serial outputs TXD swing between -5V (inactive) and +5V
(active) RS-232 voltage levels. The serial inputs RXD are RS-232 receivers and can take any voltage swing
from -15V to +15V. The receivers are always active, even in Sleep mode. The RS-232 drivers guarantee a data
rate of 1 Mbps even when fully loaded with 3Kohm in parallel with 1000pF load.
All RS-232 drivers and receivers are protected to ±15kV using the Human Body Model ground combination,
±8kV using IEC 61000-4-2 Contact Discharge, and ±15kV using IEC 61000-4-2 Air-Gap Discharge. For more
information, send an e-mail to [email protected]
6
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The V2172 can operate with either an I2C-bus interface or an SPI interface. The CPU interface is selected via
the I2C/SPI# input pin.
2.1.1
I2C-bus Interface
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2Cbus interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial
clock and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to
400 kbps. The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW
when SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the subaddress that contains the address of the register to access. The V2172 responds to each write with an
acknowledge (SDA driven LOW by V2172 for one clock cycle when SCL is HIGH). If the TX FIFO is full, the
V2172 will respond with a negative acknowledge (SDA driven HIGH by V2172 for one clock cycle when SCL is
HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I2C-bus master contains a stop bit
(SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below. For complete details, see
the I2C-bus specifications.
FIGURE 3. I2C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE (V2172)
SLAVE
ADDRESS
S
W
A
REGISTER
ADDRESS
A
SLAVE
ADDRESS
R
nDATA
A
P
White block: host to UART
Grey block: UART to host
FIGURE 5. MASTER READS FROM SLAVE (V2172)
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A
S
White block: host to UART
Grey block: UART to host
7
A
nDATA
A
LAST DATA
NA
P
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
2.2
REV. 1.0.1
I2C-bus Addressing
There could be many devices on the I2C-bus. To distinguish itself from the other devices on the I2C-bus, there
are eight possible slave addresses that can be selected for the V2172 using the A1 and A0 address lines.
Table 1 below shows the different addresses that can be selected. Note that there are two different ways to
select each I2C address.
TABLE 1: XR20V2172 I2C ADDRESS MAP
A1
A0
I2C ADDRESS
VCC
VCC
0x60 (0110 000X)
VCC
GND
0x62 (0110 001X)
VCC
SCL
0x64 (0110 010X)
VCC
SDA
0x66 (0110 011X)
GND
VCC
0x68 (0110 100X)
GND
GND
0x6A (0110 101X)
GND
SCL
0x6C (0110 110X)
GND
SDA
0x6E (0110 111X)
SCL
VCC
0x60 (0110 000X)
SCL
GND
0x62 (0110 001X)
SCL
SCL
0x64 (0110 010X)
SCL
SDA
0x66 (0110 011X)
SDA
VCC
0x68 (0110 100X)
SDA
GND
0x6A (0110 101X)
SDA
SCL
0x6C (0110 110X)
SDA
SDA
0x6E (0110 111X)
An I2C sub-address is sent by the I2C master following the slave address. The sub-address contains the
UART register address being accessed. A read or write transaction is determined by bit-0 of the slave
address. If bit-0 is’0’, then it is a write transaction. If bit-0 is ’1’, then it is a read transaction. Table 2 below
lists the functions of the bits in the I2C sub-address.
TABLE 2: I2C SUB-ADDRESS
BIT
7
FUNCTION
Reserved
6:3
UART Internal Register Address A3:A0
2:1
UART Channel Select
’00’ = UART Channel A
’01’ = UART Channel B
0
Reserved
After the last read or write transaction, the I2C-bus master will set the SCL signal back to its idle state (HIGH).
8
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
2.2.1
SPI Bus Interface
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 5 Mbps. To access the device in the SPI
mode, the CS# signal for the V2172 is asserted by the SPI master, then the SPI master starts toggling the SCL
signal with the appropriate transaction information. The first byte sent by the SPI master includes whether it is
a read or write transaction and the UART register being accessed. See Table 3 below.
TABLE 3: SPI FIRST BYTE FORMAT
BIT
7
FUNCTION
Read/Write#
Logic 1 = Read
Logic 0 = Write
6:3
UART Internal Register Address A3:A0
2:1
UART Channel Select
’00’ = UART Channel A
’01’ = UART Channel B
0
Reserved
After the last read or write transaction, the SPI master will set the SCL signal back to its idle state (LOW).
2.3
Device Reset
The RESET# input resets the internal registers and the serial interface outputs in the UART to its default state
(see Table 16). An active low pulse of longer than 40 ns duration will be required to activate the reset function
in the device.
2.4
Internal Registers
The V2172 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to the industry standard ST16C550. These registers function as data
holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR),
receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR),
programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible Scratchpad Register
(SPR).
Beyond the general 16C550 features and capabilities, the V2172 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, TCR, TLR, TXLVL, RXLVL, IODir, IOState, IOIntEna, IOControl, EFCR and DLD) that
provide automatic RTS and CTS hardware flow control, Xon/Xoff software flow control, TX and RX FIFO level
counters, and programmable FIFO trigger level control. All the register functions are discussed in full detail
later in “Section 3.0, UART Internal Registers” on page 21.
2.5
IRQ# Output
The IRQ# interrupt output changes according to the operating mode and enhanced features setup. Table 4
and 5 summarize the operating behavior for the transmitter and receiver.
TABLE 4: IRQ# PIN OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
IRQ# Pin
NO
HIGH = a byte in THR
LOW = THR empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or FIFO empty
IRQ# Pin
YES
HIGH = a byte in THR
LOW = transmitter empty
HIGH = FIFO above trigger level
LOW = FIFO below trigger level or transmitter empty
9
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
TABLE 5: IRQ# PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
IRQ# Pin
2.6
HIGH = no data
LOW = 1 byte
FCR BIT-0 = 1
(FIFO ENABLED)
HIGH = FIFO below trigger level
LOW = FIFO above trigger level
Crystal Oscillator or External Clock Input
The V2172 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in
each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the
output. Please note that the input XTAL1 is not 5V tolerant and so the maximum at the pin should be VCC. For
programming details, see ““Section 2.7, Programmable Baud Rate Generator with Fractional Divisor” on
page 10.”
FIGURE 6. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R2
500 ΚΩ − 1 ΜΩ
Y1
C1
22-47 pF
R1
0-120 Ω
(Optional)
1.8432 MHz
to
24 MHz
C2
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 6). The programmable Baud
Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. Although the V2172
can accept an external clock of up to 64MHz, the maximum data rate supported by the RS-232 drivers is
250Kbps. For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR
web site at http://www.exar.com.
2.7
Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for
data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the
10
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon power-up. Therefore, the BRG must be
programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part
of the divisor and the DLD register provides the fractional part of the dvisior. The four lower bits of the DLD are
used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud
Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data rate.
Table 6 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the
pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X
sampling rate, these data rates would double and at 4X sampling rate, these data rates would quadruple. Also,
when using 8X sampling mode, the bit time will have a jitter of ± 1/16 whenever the DLD is non-zero and is an
odd number. When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero,
odd and not a multiple of 4. When using a non-standard data rate crystal or external clock, the divisor value
can be calculated with the following equation(s):
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
The closest divisor that is obtainable in the V2172 can be calculated using the following formula:
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
FIGURE 7. BAUD RATE GENERATOR
DLL, DLM and DLD
Registers
Prescaler
Divide by 1
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
Fractional Baud
Rate Generator
Logic
Prescaler
Divide by 4
11
MCR Bit-7=1
16X or 8X or 4X
Sampling
Rate Clock
to Transmitter
and Receiver
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
DIVISOR FOR
16x Clock
(Decimal)
DIVISOR
OBTAINABLE IN
V2172
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DLD PROGRAM
VALUE (HEX)
DATA ERROR
RATE (%)
400
3750
3750
E
A6
0
0
2400
625
625
2
71
0
0
4800
312.5
312 8/16
1
38
8
0
9600
156.25
156 4/16
0
9C
4
0
10000
150
150
0
96
0
0
19200
78.125
78 2/16
0
4E
2
0
25000
60
60
0
3C
0
0
28800
52.0833
52 1/16
0
34
1
0.04
38400
39.0625
39 1/16
0
27
1
0
50000
30
30
0
1E
0
0
57600
26.0417
26 1/16
0
1A
1
0.08
75000
20
20
0
14
0
0
100000
15
15
0
F
0
0
115200
13.0208
13
0
D
0
0.16
153600
9.7656
9 12/16
0
9
C
0.16
200000
7.5
7 8/16
0
7
8
0
225000
6.6667
6 11/16
0
6
B
0.31
230400
6.5104
6 8/16
0
6
8
0.16
250000
6
6
0
6
0
0
2.8
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X
internal clock. A bit time is 16 (8 if 8X or 4 if 4X) clock periods (see DLD[5:4]). The transmitter sends the startbit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The
status of the FIFO and TSR are reported in the Line Status Register (LSR[6:5]).
2.8.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
12
XR20V2172
REV. 1.0.1
2.8.2
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 8. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Data
Byte
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X or 8X or 4X
Clock
( DLD[5:4] )
Transmit Shift Register (TSR)
M
S
B
L
S
B
TXNOFIFO1
2.8.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
FIGURE 9. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Data Byte
Transmit
FIFO
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.)
Auto Software Flow Control
16X or 8X or 4X Clock
( DLD[5:4] )
Transm it Data Shift Register
(TSR)
TXFIFO 1
13
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
2.9
REV. 1.0.1
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0.
2.9.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X or 4X C lock
( D LD[5:4] )
R eceive
D ata B yte
and E rrors
R eceive D ata S hift
R egister (R S R )
E rror
Tags in
LS R bits
4:2
R eceive D ata
H olding R egister
(R H R)
D ata Bit
V alidation
R eceive D ata C haracters
R H R Interrupt (ISR bit-2)
R XFIFO 1
14
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Shift
Register (RSR)
Data Bit
Validation
64 bytes by 11-bit wide
FIFO
Error Tags
(64-sets)
Data falls to
Resume Level
Receive
Data FIFO
FIFO
Trigger=16
Error Tags in
LSR bits 4:2
Data fills to
Halt Level
Receive Data
Byte and Errors
Receive Data Characters
Example
: - RX FIFO trigger level selected at 16 bytes
(See Note Below)
RTS# re-asserts when data falls to the Resume
Level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills to the Halt Level
to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Receive
Data
RXFIFO1
2.10
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 12):
• Enable auto RTS flow control using EFR bit-6.
• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.11
Auto RTS Halt and Resume
The RTS# pin will not be forced HIGH (RTS off) until the receive FIFO reaches the Halt Level (TCR[3:0]). The
RTS# pin will return LOW after the RX FIFO is unloaded to the Resume Level (TCR[7:4]). Under these
conditions, the V2172 will continue to accept data if the remote UART continues to transmit data. It is the
responsibility of the user to ensure that the Halt Level is greater than the Resume Level. If interrupts are used,
it is recommended that Halt Level > RX Trigger Level > Resume Level. The Auto RTS function is initiated
when the RTS# output pin is asserted LOW (RTS On).
2.12
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 12):
• Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
• Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
15
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is reasserted (LOW), indicating more data may be sent.
FIGURE 12. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART
UARTA
Remote UART
UARTB
RXA
Receiver FIFO
Trigger Reached
RTSA#
Auto RTS
Trigger Level
Receiver FIFO
Trigger Reached
RTSB#
Assert RTS# to Begin
Transmission
1
ON
Auto RTS
Trigger Level
10
OFF
ON
7
2
CTSB#
Auto CTS
Monitor
RXB
CTSA#
Auto CTS
Monitor
Transmitter
CTSB#
TXA
Transmitter
RTSA#
TXB
ON
3
8
OFF
6
Suspend
11
ON
TXB
Data Starts
4
Restart
9
RXA FIFO
INTA
(RXA FIFO
Interrupt)
Receive
RX FIFO
Data
Trigger Level
5
RTS High
Threshold
RTS Low
Threshold
12
RX FIFO
Trigger Level
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
16
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
2.13
Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 15), the V2172 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the V2172 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the V2172 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the V2172 will resume operation
and clear the flags (ISR bit-4).
Upon power-up, the contents of the Xon/Xoff 8-bit flow control registers to 0x00. The user can write any Xon/
Xoff value desired for software flow control. These registers are not reset by a hardware or software reset.
Different conditions can be set to detect Xon/Xoff characters (See Table 15) and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the V2172 compares two consecutive
receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX
transmissions accordingly. Under the above described flow control mechanisms, flow control characters are
not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the V2172 automatically
sends the Xoff-1,2 via the serial TX output to the remote modem when the RX FIFO reaches the Halt Level
(TCR[3:0]). To clear this condition, the V2172 will transmit the programmed Xon-1,2 characters as soon as RX
FIFO falls down to the Resume Level.
2.14
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The V2172 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison.
2.15
Sleep Mode with Auto Wake-Up
The V2172 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used. In the Partial Sleep mode, the internal oscillator of the UART
or charge pump of the RS-232 transceiver is turned off to reduce the power consumption. In the Full Sleep
mode, both the oscillator and the charge pump are turned off.
2.15.1
Partial Sleep Mode
There are two different partial sleep modes. In the first mode, the UART is in sleep mode and the charge pump
is active. In the other mode, the UART is still active but the charge pump is turned off.
2.15.1.1
UART in sleep mode, RS-232 transceiver active
If the ACP pin is LOW, then the charge pump for the RS-232 transceiver will always be active. But the UART
portion in the V2172 can still enter sleep mode if all of these conditions are satisfied for both channels:
■
■
■
■
■
no interrupts pending (ISR bit-0 = 1)
the 16-bit divisor programmed in DLM and DLL registers is a non-zero value
sleep mode is enabled (IER bit-4 = 1)
modem inputs are not toggling (MSR bits 0-3 = 0)
RXD input pin is idling LOW
17
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
The V2172 UART portion stops its crystal oscillator to conserve power in this mode. The user can check the
XTAL2 pin for no clock output as an indication that the device has entered the partial sleep mode.
The UART portion in the V2172 resumes normal operation or active mode by any of the following:
■
■
■
a receive data start bit transition on the RXD input (LOW to HIGH)
a data byte is loaded to the transmitter, THR or FIFO
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the UART portion of V2172 is awakened by any one of the above conditions, it will return to the sleep mode
automatically after all interrupting conditions have been serviced and cleared. If the UART portion of V2172 is
awakened by the modem inputs, a read to the MSR is required to reset the modem inputs. In any case, the
sleep mode will not be entered while an interrupt is pending. The UART portion of V2172 will stay in the sleep
mode of operation until it is disabled by setting IER bit-4 to a logic 0.
2.15.1.2
UART active, charge pump of RS-232 transceiver shut down
If the ACP pin is HIGH and the UART portion of the V2172 is not in sleep mode, then the charge pump will
automatically shut down to conserve power if the following conditions are true:
■
■
■
no activity on the TXD output signal
modem input signals (RX) are LOW
modem inputs have been idle for approximately 30 seconds
When these conditions are satisfied, the V2172 shuts down the charge pump and tri-states the RS-232 drivers
to conserve power. In this mode, the RS-232 receivers are fully active and the internal registers of the V2172
can be accessed. The time for the charge pump to resume normal operation after exiting the sleep mode is
typically 45µs. It will wake up by any of the following:
■
■
■
a receive data start bit transition on the RXD input (LOW to HIGH)
a data byte is loaded to the transmitter, THR or FIFO
a LOW to HIGH transition on any of the modem or general purpose serial inputs
Because the receivers are fully active when the charge pump is turned off, any data received will be transferred
to/from the UART without any issues.
2.15.2
Full Sleep Mode
In full sleep mode, the V2172 shuts down the charge pump and the internal oscillator. The V2172 enters the full
sleep mode if the following conditions are satisfied:
■
■
the UART portion of the V2172 is already in sleep mode (no output on XTAL2)
the ACP (Autosleep for Charge Pump) pin is HIGH
When these conditions are satisfied, both the UART and the charge pump will be in the sleep mode. In this
mode, the RS-232 receivers are fully active and the internal registers of the V2172 can be accessed. The
V2172 exits the full sleep mode if either the ACP pin becomes LOW or the internal oscillator starts up. The time
for the charge pump to resume normal operation after exiting the full sleep mode is typically 45µs.
If the serial clock, serial data, and modem input lines remain steady when the V2172 is in sleep mode, the
maximum current will be in the microamp range as specified in the DC Electrical Characteristics on page 39.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. The number of characters lost during the restart also depends on your
operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep
RX input idling HIGH or “marking” condition during sleep mode to avoid receiving a “break” condition upon the
restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type) are also put
to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a 47k-100k
ohm pull-up resistor on the RX input pin.
18
XR20V2172
REV. 1.0.1
2.16
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
Infrared Mode (UART Channel B Only)
The L402 includes an infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version
1.0 and 1.1. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGHpulse for each “0” bit in the transmit data stream with a data rate up to 115.2 Kbps. For the IrDA 1.1 standard,
the infrared encoder sends out a 1/4 of a bit time wide HIGH-pulse for each "0" bit in the transmit data stream
with a data rate up to 1.152 Mbps. This signal encoding reduces the on-time of the infrared LED, hence
reduces the power consumption. See Figure 13 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. With this bit enabled, the
infrared encoder and decoder is compatible to the IrDA 1.0 standard. For the infrared encoder and decoder to
be compatible to the IrDA 1.1 standard, EFCR bit-7 will also need to be set to a ’1’. When the infrared feature
is enabled, the transmit data output, TX, idles LOW. Likewise, the RX input also idles LOW, see Figure 13.
The wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each
time it senses a light pulse, it returns a logic 1 to the data bit stream.
The Infrared Mode can only be used with channel B of the L402 using the TXB output and the RXB input pins.
FIGURE 13. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
TX Data
0
Stop
Start
Character
Data Bits
1
0
1
0
1
0
1
1
0
Transmit
IR Pulse
(TX Pin)
Receive
IR Pulse
(RX pin)
1/2 Bit Time
3/16 or 1/4
Bit Time
Bit Time
IrEncoder-1
Bit Time
1/16 Clock Delay
1
0
1
0
0
Data Bits
1
1
0
1
Stop
0
Start
RX Data
Character
IRdecoder-1
19
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
2.17
REV. 1.0.1
Internal Loopback
The V2172 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 14 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, auto RTS/CTS flow control is not supported during
internal loopback.
FIGURE 14. INTERNAL LOOP BACK
VCC
TX
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
RX
VCC
RTS#
RTS#
Modem / General Purpose Control Logic
Internal Data Bus Lines and Control Signals
MCR bit-4=1
CTS#
CTS#
VCC
DTR#
DTR#
DSR#
DSR#
OP1#
RI#
RI#
OP2#
CD#
CD#
20
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
3.0 UART INTERNAL REGISTERS
The complete register set is shown below in Table 7 and Table 8.
TABLE 7: UART INTERNAL REGISTER ADDRESSES
ADDRESS
REGISTER
READ/WRITE
COMMENTS
LCR[7] = 0
16C550 COMPATIBLE REGISTERS
0X00
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
0X00
DLL - Divisor LSB
Read/Write
0X01
DLM - Divisor MSB
Read/Write
0X02
DLD - Divisor Fractional
Read/Write
0X01
IER - Interrupt Enable Register
Read/Write
0X02
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0X03
LCR - Line Control Register
Read/Write
0X04
MCR - Modem Control Register
Read/Write
0X05
LSR - Line Status Register
Read-only
0X06
MSR - Modem Status Register
Read-only
See Table 12
0X07
SPR - Scratch Pad Register
Read/Write
See Table 13
0X06
TCR - Transmission Control Register
Read/Write
See Table 12
0X07
TLR - Trigger Level Register
Read/Write
See Table 13
0X08
TXLVL - Transmit FIFO Level
Read-only
0x09
RXLVL - Receive FIFO Level
Read-only
0x0A
IODir - GPIO Direction Control Register
Read/Write
0x0B
IOState - GPIO State Register
Read/Write
0x0C
IOIntEna - GPIO Interrupt Enable Register
Read/Write
0x0D
Reserved
0x0E
IOControl - GPIO Control Register
Read/Write
0x0F
EFCR - Extra Features Control Register
Read/Write
0x02
EFR - Enhanced Function Register
Read/Write
0x04
Xon-1 - Xon Character 1
Read/Write
0x05
Xon-2 - Xon Character 2
Read/Write
0x06
Xoff-1 - Xoff Character 1
Read/Write
0x07
Xoff-2 - Xoff Character 2
Read/Write
LCR[7] = 1, LCR ≠ 0xBF
LCR[7] = 1, LCR ≠ 0xBF,
EFR[4] = 1
LCR[7] = 0
LCR ≠ 0xBF
LCR[7] = 0
-
21
LCR = 0xBF
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
.
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDR
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
0x00
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x00
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x01
IER
RD/WR
0/
0/
0/
0/
CTS Int. RTS Int.
Enable Enable
Xoff Int.
Enable
Sleep
Mode
Enable
FIFOs
FIFOs
Enabled Enabled
0/
0/
INT
Source
Bit-5
INT
Source
Bit-4
0/
0/
TX FIFO
Trigger
TX FIFO
Trigger
0x02
0x02
ISR
FCR
RD
WR
RX FIFO RX FIFO
Trigger Trigger
0x03
LCR
RD/WR Divisor
Enable
0x04
MCR
RD/WR
0/
Clock
Prescaler
Select
Set TX
Break
0/
Modem RX Line
Stat. Int. Stat. Int.
Enable Enable
TX
RX Data
Empty
Int.
Int
Enable
Enable
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
DMA TX FIFO
Mode
Reset
Enable
RX
FIFO
Reset
FIFOs
Enable
Stop
Bits
Word
Length
Bit-1
Word
Length
Bit-0
0/
RTS#
Output
Control
DTR#
Output
Control
Set Par- Even Par- Parity
Enable
ity
ity
0/
Enable XonAny
IR Mode
(Ch B
Only)
Internal
Lopback
Enable
OP2#
Enable
TCR
and TLR
LCR[7]=0
LCR≠0xBF
0x05
LSR
RD
RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX Break
RX
Framing
Error
RX
Parity
Error
RX
Overrun
Error
RX Data
Ready
0x06
MSR
RD
CD#
Input
RI# Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
See Table 12
0x07
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
See Table 13
0x06
TCR
RD/WR Resume Resume Resume
Bit-3
Bit-2
Bit-1
Resume
Bit-0
Halt
Bit-3
Halt
Bit-2
Halt
Bit-1
Halt
Bit-0
See Table 12
0x07
TLR
RD/WR RX Trig
Bit-3
0x08
TXLVL
RD/WR
0x09
RXLVL
RD/WR
RX Trig
Bit-2
RX Trig
Bit-1
RX Trig
Bit-0
TX Trig
Bit-3
TX Trig
Bit-2
TX Trig
Bit-1
0
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
22
TX Trig
See Table 13
Bit-0
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDR
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
0x0A
IODir
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x0B
IOState
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x0C IOIntEna RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0
0
0
0
0
0
0
0
0
0
0
0
UART
SW
Reset
0
0
0
0
0x0D reserved
-
0x0E IOControl RD/WR
0x0F
EFCR
RD/WR Fast IR
Mode
(Ch B
Only)
COMMENT
GPIO or GPIO or IOLatch
Modem Modem
IO Ch B IO Ch A
TX
RX
Disable Disable
0
Baud Rate Generator Divisor
0x00
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x01
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x02
DLD
RD/WR
Bit-7
Bit-6
4X
Mode
8X Mode
Fractional
Divisor
Bit-3
Fractional
Divisor
Bit-2
Fractional
Divisor
Bit-1
Fractional
Divisor
Bit-0
LCR[7]=1
LCR≠0xBF
LCR[7]=1
LCR≠0xBF
EFR[4]=1
Enhanced Registers
0x02
EFR
RD/WR
Auto Auto RTS Special
CTS
Enable
Char
Enable
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5],
DLD
Software
Flow
Cntl
Bit-3
Software
Flow
Cntl
Bit-2
Software
Flow
Cntl
Bit-1
Software
Flow
Cntl
Bit-0
0x04
XON1
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x05
XON2
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x06
XOFF1
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x07
XOFF2
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR=0XBF
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 14.
4.2
Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 12.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
23
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
4.3.1
REV. 1.0.1
IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR20V2172 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the nonFIFO mode or when spaces in the FIFO is above the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3, 4 or 7 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bit-7 is set if any character in the RX FIFO has a parity or framing error, or is
a break character. LSR[4:2] always show the error status for the received character available for reading from
the RX FIFO. If IER[2] = 1, an LSR interrupt will be generated as long as LSR[7] = 1, ie. the RX FIFO contains
at lease one character with an error.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
24
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
• Logic 0 = Disable Sleep Mode (default).
• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
• Logic 1 = Enable the receive Xoff interrupt. See Software Flow Control section for details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the RTS# interrupt (default).
• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
• Logic 0 = Disable the CTS# interrupt (default).
• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3, 4 and 7.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX trigger level or TX FIFO empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• GPIO is when any of the GPIO inputs toggle.
• Receive Xoff/Special character is by detection of a Xoff or Special character.
• CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.
• RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
4.4.2
Interrupt Clearing:
• LSR interrupt is cleared by reading all characters with errors out of the RX FIFO.
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
• GPIO interrupt is cleared by reading the IOState register.
• Xoff interrupt is cleared when Xon character(s) is received.
25
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
• Special character interrupt is cleared by a read to ISR.
• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
]
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
0
0
1
1
0
LSR (Receiver Line Status Register)
2
0
0
1
1
0
0
RXRDY (Receive Data Time-out)
3
0
0
0
1
0
0
RXRDY (Received Data Ready)
4
0
0
0
0
1
0
TXRDY (Transmit Ready)
5
0
0
0
0
0
0
MSR (Modem Status Register)
6
1
1
0
0
0
0
GPIO (General Purpose Inputs)
7
0
1
0
0
0
0
RXRDY (Received Xoff or Special character)
8
1
0
0
0
0
0
CTS#, RTS# change of state
-
0
0
0
0
0
1
None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is set when EFR[4] = 1 and IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of
the Xoff character(s). If this is an Xoff interrupt, it is cleared when XON is received. If it is a special character
interrupt, it is cleared by reading ISR.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR[4] = 1. ISR bit-5 indicates that the CTS# or RTS# has been de-asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
• Logic 0 = Disable the transmit and receive FIFO (default).
• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
26
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’ and requires at least 3 XTAL clocks to reset.
• Logic 0 = No receive FIFO reset (default)
• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’ and requires at least 3 XTAL clocks to reset.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
This is a legacy register bit that does not have any functionality in the XR20V2172.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of spaces in the FIFO is above the selected trigger level, or when it gets empty in case that the FIFO
did not get filled over the trigger level on last re-load. Table 10 shows the selections. The UART will issue a
transmit interrupt when the number of available spaces in the FIFO is less than the transmit trigger level.
Table 10 shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO is greater than the receive trigger level or when a receive data
timeout occurs (see “Section 2.9, Receiver” on page 14).
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
0
0
1
1
FCR
BIT-6
FCR
BIT-5
FCR
BIT-4
0
0
1
1
0
1
0
1
RECEIVE
TRIGGER LEVEL
(CHARACTERS)
TRANSMIT
TRIGGER LEVEL
(SPACES)
8
16
32
56
0
1
0
1
8
16
56
60
27
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
4.6
REV. 1.0.1
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
5
0
1
6 (default)
1
0
7
1
1
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1
1
5
1-1/2
1
6,7,8
2 (default)
BIT-2
WORD
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received (default).
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
28
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR BIT-5 = logic 0, parity is not forced (default).
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
X
0
No parity
0
0
1
Odd parity
0
1
1
Even parity
1
0
1
Force parity to mark, “1”
1
1
1
Forced parity to space, “0”
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM and DLD) enable.
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force DTR# output HIGH (default).
• Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. The RTS# pin can also be used for Auto RS485 Half-Duplex direction control enabled by FCTR bit3. If the modem interface is not used, this output may be used as a general purpose output.
• Logic 0 = Force RTS# HIGH (default).
• Logic 1 = Force RTS# LOW.
29
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
MCR[2]: OP1# / TCR and TLR Enable
OP1# is not available as an output pin on the V2172. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the MSR and TCR registers at address offset 0x6 and the SPR and TLR
registers at address offset 0x7. Table 12 and Table 13 below shows how these registers are accessed.
TABLE 12: REGISTER AT ADDRESS OFFSET 0X6
EFR[4] MCR[2] Register at Address Offset 0x6
0
X
Modem Status Register (MSR)
1
0
Modem Status Register (MSR)
1
1
Trigger Control Register (TCR)
TABLE 13: REGISTER AT ADDRESS OFFSET 0X7
EFR[4]
MCR[2] Register at Address Offset 0x7
0
X
Scratchpad Register (SPR)
1
0
Scratchpad Register (SPR)
1
1
Trigger Level Register (TLR)
MCR[3]: OP2# Output
OP2# is not available as an output on the V2172 but can be controlled in internal loopback mode.
• Logic 0 = OP2# output set HIGH(default).
• Logic 1 = OP2# output set LOW.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 14.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
• Logic 0 = Disable Xon-Any function (default).
• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the V2172 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
• Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface requirement.
While in this mode, the infrared TX output will be idling LOW. SEE”INFRARED MODE (UART CHANNEL B
ONLY)” ON PAGE 19.
30
XR20V2172
REV. 1.0.1
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
MCR[7]: Clock Prescaler Select (requires EFR bit-4=1 to write to this bit)
• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
LSR[1]: Receiver Overrun Error Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Error Tag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
31
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.9
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a LOW to HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The
CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.10
Scratch Pad Register (SPR) - Read/Write
32
XR20V2172
REV. 1.0.1
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a power off-on cycle. There are also two other
registers (TLR and FIFO Rdy) that share the same address location as the Scratch Pad Register. See
Table 13.
4.11
Transmission Control Register (TCR) - Read/Write (requires EFR bit-4 = 1)
This register replaces MSR and is accessible only when MCR[2] = 1. This 8-bit register is used to store the RX
FIFO threshold levels to halt/resume transmission during hardware or software flow control.
TCR[3:0]: RX FIFO Halt Level
A value of 0-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the Halt Level. When the RX
FIFO is greater than or equal to this value, the RTS# output will be de-asserted if Auto RTS flow control is used
or the XOFF character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that
this value is greater than the RX Trigger Level.
TCR[7:4]: RX FIFO Resume Level
A value of 0-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the Resume Level. When the
RX FIFO is less than or equal to this value, the RTS# output will be re-asserted if Auto RTS flow control is used
or the XON character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that this
value is less than the RX Trigger Level.
4.12
Trigger Level Register (TLR) - Read/Write (requires EFR bit-4 = 1)
This register replaces SPR and is accessible under the conditions listed in Table 13. This 8-bit register is used
to store the RX and TX FIFO trigger levels used for interrupts.
TLR[3:0]: TX FIFO Trigger Level
A value of 4-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the TX FIFO Trigger Level.
When the number of available spaces in the TX FIFO is greater than or equal to this value, a Transmit Ready
interrupt is generated. For any non-zero value, TCR[3:0] will be used as the TX FIFO Trigger Level. If
TCR[3:0] = 0x0, then the TX FIFO Trigger Level is the value selected by FCR[5:4]. See Table 10.
TLR[7:4]: RX FIFO Trigger Level
A value of 4-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the RX FIFO Trigger Level.
When the number of characters received in the RX FIFO is greater than or equal to this value, a Receive Data
Ready interrupt is generated (a Receive Data Timeout interrupt is independent of the RX FIFO Trigger Level
and can be generated any time there is at least 1 byte in the RX FIFO and the RX input has been idle for the
timeout period described in “Section 2.9, Receiver” on page 14). For any non-zero value, TCR[7:4] will be
used as the RX FIFO Trigger Level. If TCR[7:4] = 0x0, then the RX FIFO Trigger Level is the value selected by
FCR[7:6]. See Table 10.
4.13
Transmit FIFO Level Register (TXLVL) - Read-only
This register reports the number of spaces available in the TX FIFO. If the TX FIFO is empty, the TXLVL
register will report that there are 64 spaces available. If the TX FIFO is full, the TXLVL register will report that
there are 0 spaces available.
4.14
Receive FIFO Level Register (RXLVL) - Read-only
This register reports the number of characters available in the RX FIFO. If the RX FIFO is empty, the RXLVL
register will report that there are 0 characters available. If the RX FIFO is full, the RXLVL register will report
that there are 64 characcters available.
4.15
GPIO Direction Register (IODir) - Read/Write
This register is used to program the direction of the GPIO pins. Bit-7 to bit-0 controls GPIO7 to GPIO0.
• Logic 0 = set GPIO pin as input
• Logic 1 = set GPIO pin as output
33
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
4.16
REV. 1.0.1
GPIO State Register (IOState) = Read/Write
This register reports the state of all GPIO pins during a read and writes to any GPIO that is an output.
• Logic 0 = set output pin LOW
• Logic 1 = set output pin HIGH
4.17
GPIO Interrupt Enable Register (IOIntEna) - Read/Write
This register enables the interrupt for the GPIO pins. The interrupts for GPIO[7:4] are only enabled if
IOControl[1] = 0. If IOControl[0] = 1 (GPIO pins are selected as modem IOs) , then IOIntEna[7:4] will have no
effect on GPIO[7:4].
• Logic 0 = a change in the input pin will not generate an interrupt
• Logic 1 = a change in the input will generate an interrupt
4.18
GPIO Control Register (IOControl) - Read/Write
IOControl bits 2-1 should be set to a logic 1 to behave like modem IOs that can be controlled and monitored via
the MCR and MSR registers. If not, by default, they are GPIOs controlled by IODir, IOState and IOIntEna.
IOControl[7:4]: Reserved
IOControl[3]: UART Software Reset
Writing a logic 1 to this bit will reset the device. Once the device is reset, this bit will automatically be set to a
logic 0.
IOControl[2]: GPIO[3:0] or Modem IO Select (CH B)
This bit controls whether GPIO[3:0] behave as GPIO pins or as modem IO pins (RIB#, CDB#, DTRB#, DSRB#)
• Logic 0 = GPIO[3:0] behave as GPIO pins
• Logic 1 = GPIO[3:0] behave as RIB#, CDB#, DTRB#, DSRB#. Note: DTRB# will also need to be set as an
output via IODir bit-1.
IOControl[1]: GPIO[7:4] or Modem IO Select (CH A)
This bit controls whether GPIO[7:4] behave as GPIO pins or as modem IO pins (RIA#, CDA#, DTRA#, DSRA#)
• Logic 0 = GPIO[7:4] behave as GPIO pins
• Logic 1 = GPIO[7:4] behave as RIA#, CDA#, DTRA#, DSRA#. Note: DTRA# will also need to be set as an
output via IODir bit-5.
IOControl[0]: IO Latch
This bit enable/disable GPIO inputs latching.
• Logic 0 = GPIO input values are not latched. A change in any GPIO input generates an interrupt. A read of
the IOState register clears the interrupt. If the input goes back to its initial logic state before the input register
is read, then the interrupt is cleared.
• Logic 1 = GPIO input values are latched. A change in the GPIO input generates an interrupt and the input
logic value is loaded in the bit of the corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial logic state before the interrupt register is
read, then the interrupt is not cleared and the corresponding bit of the IOState register keeps the logic value
that generated the interrupt.
34
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
4.19
Extra Features Control Register (EFCR) - Read/Write
EFCR[7]: IrDA mode
This bit selects between the slow and fast IrDA modes. See “Section 2.16, Infrared Mode (UART Channel B
Only)” on page 19 for complete details.
• Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps
• Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps
EFCR[6:3]: Reserved
These bits are reserved and should be left at "0000".
EFCR[2]: Transmitter Disable
UART does not send serial data out on the TX output pin, but the TX FIFO will continue to receive data from
CPU until full. Any data in the TSR will be sent out before the trasnmitter goes into disable state.
• Logic 0 = Transmitter is enabled
• Logic 1 = Transmitter is disabled
EFCR[1] = Receiver Disable
UART will stop receiving data immediately once this bit is set to a Logic 1. Any data that is being received in
the TSR will be received correctly and sent to the RX FIFO.
• Logic 0 = Receiver is enabled
• Logic 1 = Receiver is disabled
EFCR[0]: Reserved
This bit is reserved and should remain at a logic 0.
4.20
Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. SEE”PROGRAMMABLE BAUD RATE GENERATOR WITH
FRACTIONAL DIVISOR” ON PAGE 10.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 14 below.
TABLE 14: SAMPLING RATE SELECT
DLD[5]
DLD[4]
SAMPLING RATE
0
0
16X
0
1
8X
1
X
4X
DLD[7:6]: Reserved
35
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
4.21
REV. 1.0.1
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1, Xoff1
0
1
X
X
Transmit Xon2, Xoff2
1
1
X
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1, Xoff1
X
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2 and 5-7,
TCR, TLR and DLD to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch
the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2
and 5-7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits
4-5, MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
• Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
• Logic 0 = Special Character Detect Disabled (default).
36
XR20V2172
REV. 1.0.1
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the programmed HALT level. RTS# will return LOW when FIFO data falls below the
programmed RESUME level. The RTS# output must be asserted (LOW) before the auto RTS can take effect.
RTS# pin will function as a general purpose output when hardware flow control is disabled.
• Logic 0 = Automatic RTS flow control is disabled (default).
• Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
• Logic 0 = Automatic CTS flow control is disabled (default).
• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW.
4.21.1
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 8.
37
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
TABLE 16: UART RESET STATES
REGISTERS
DLM, DLL
RESET STATE
DLM = 0x00 and DLL = 0x01[1]
DLD
Bits 7-0 = 0x00
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x1D
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF[1]
TCR
Bits 7-0 = 0x0F
TLR
Bits 7-0 = 0x00
TXLVL
Bits 7-0 = 0x40
RXLVL
Bits 7-0 = 0x00
IODir
Bits 7-0 = 0x00
IOState
Bits 7-0 = 0x00
IOIntEna
Bits 7-0 = 0x00
IOCont
Bits 7-0 = 0x00
EFCR
Bits 7-0 = 0x00
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00[1]
XON2
Bits 7-0 = 0x00[1]
XOFF1
Bits 7-0 = 0x00[1]
XOFF2
Bits 7-0 = 0x00[1]
I/O SIGNALS
RESET STATE
TX
HIGH
RTS#
HIGH
DTR#
HIGH
IRQ#
HIGH
NOTE: [1] Only resets to these values during a power up. They do not reset when the RESET# pin is asserted or during
software reset IOCont[3] = 1.
38
XR20V2172
REV. 1.0.1
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
5.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
6 Volts
Operating Temperature
-40o to +85oC
Storage Temperature
-65o to +150oC
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (64-QFN)
theta-ja = 54oC/W, theta-jc = 13oC/W
39
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA= -40O TO +85OC (INDUSTRIAL GRADE), VCC= 3.3 - 5.5V
PARAMETER
SYMBOL
CONDITIONS
3.3V LIMITS
MIN MAX
5.0V LIMITS
MIN MAX
40
45
mA
40
50
uA
UNITS
DC CHARACTERISTICS
ICC
ISLP/IPWS
Supply Current, Normal Mode
VCC=3.3V to 5.5V, TA=+25C, no
load
Supply Current, Sleep Mode/PowerSave Mode
OSCILLATOR INPUT (X1)
VILCK
Clock Input Low Level
-0.3
0.6
-0.5
0.6
V
VIHCK
Clock Input High Level
2.4
VCC
3.0
VCC
V
LOGIC INPUTS/OUTPUTS (SDA, SCK, A1/SI, A0/CS#, SO, IRQ#, RESET#, ACP, TXB, RXB, RXBSEL, FAST, R_EN)
VIL
VIH
Input Low Voltage
-0.3
0.7
-0.3
0.7
V
Input High Voltage (not 5V tolerant)
2.0
3.63
2.0
3.63
V
Input High Voltage (5V tolerant)
2.0
5.5
2.0
5.5
V
0.4
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.4
2.0
2.0
V
IIL
Input Low Leakage Current
+/-10
+/-10
uA
IHL
Input High Leakage Current
+/-10
+/-10
uA
+/-15
+/-15
V
RS-232 INPUTS (RXD, CTS, DSR, RI, DCD)
Input Voltage Range
VIHR
Input Threshold Low
TA=+25C
VILR
Input Threshold High
TA=+25C
VHYS
Input Hysteresis
RTR
Input Transmition Resistance
0.6
TA=+25C
3
0.8
V
2.0
2.4
V
0.5
0.5
V
7
Kohm
7
3
RS-232 OUTPUTS (TXD, RTS, DTR)
Output Voltage Range
3Kohm load on all transmitter outputs
+/-5.0
+/-5.0
V
ROR
Output Resistance
Vcc=0V, transmitter output=+/-2V
300
300
ohm
IOS
Output Short-Circuit Current
ILKGR
Output Leakage Current
Vcc=0, transmitters disabled
+/-60
+/-60
mA
+/-25
+/-25
uA
RS-232 AC TIMING (TXD)
Maximum Data Rate (FAST = GND)
RL=3Kohm, CL=1000pF
250
250
Kbps
Transmitter Slew Rate (FAST = GND)
CL = 50pF to 2500pF, RL=3-7Kohm
30
30
V/us
Maximum Data Rate (FAST = VCC)
RL=3Kohm, CL=1000pF
1
1
Mbps
Transmitter Slew Rate (FAST = VCC)
CL = 50pF to 2500pF, RL=3-7Kohm
100
100
V/us
40
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
AC ELECTRICAL CHARACTERISTICS - UART CLOCK
Unless otherwise noted: TA=-40o to +85oC, Vcc=3.3 - 5.5V
SYMBOL
LIMITS
MIN
MAX
PARAMETER
UNIT
XTAL1
UART Crystal Oscillator
24
MHz
ECLK
UART External Clock
64
MHz
TECLK
External Clock Time Period
7
FIGURE 15. CLOCK TIMING
TECLK
TECL
TECH
VIHCK
External
Clock
VILCK
41
ns
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
AC ELECTRICAL CHARACTERISTICS - I2C-BUS TIMING SPECIFICATIONS
Unless otherwise noted: TA=-40o to +85oC, Vcc=3.3 - 5.5V
SYMBOL
STANDARD MODE
I2C-BUS
MIN
MAX
PARAMETER
0
0
400
UNIT
fSCL
Operating frequency
TBUF
Bus free time between STOP and START
4.7
1.3
µs
THD;STA
START condition hold time
4.0
0.6
µs
TSU;STA
START condition setup time
4.7
0.6
µs
THD;DAT
Data hold time
0
0
ns
TVD;ACK
Data valid acknowledge
0.6
0.6
µs
TVD;DAT
SCL LOW to data out valid
0.6
0.6
ns
TSU;DAT
Data setup time
250
150
ns
TLOW
Clock LOW period
4.7
1.3
µs
THIGH
Clock HIGH period
4.0
0.6
µs
TF
Clock/data fall time
300
300
ns
TR
Clock/data rise time
1000
300
ns
TSP
Pulse width of spikes tolerance
0.5
0.5
µs
TD1
I2C-bus GPIO output valid
0.2
0.2
µs
TD2
I2C-bus modem input interrupt valid
0.2
0.2
µs
TD3
I2C-bus modem input interrupt clear
0.2
0.2
µs
TD4
I2C input pin interrupt valid
0.2
0.2
µs
TD5
I2C input pin interrupt clear
0.2
0.2
µs
TD6
I2C-bus receive interrupt valid
0.2
0.2
µs
TD7
I2C-bus receive interrupt clear
0.2
0.2
µs
TD8
I2C-bus transmit interrupt clear
1.0
0.5
µs
TD15
SCL delay after reset
3
3
µs
42
100
FAST MODE
I2C-BUS
MIN
MAX
kHz
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
FIGURE 16. SCL DELAY AFTER RESET
RESET#
T D15
SCL
FIGURE 17. I2C-BUS TIMING DIAGRAM
START
condition
(S)
Protocol
T SU;STA
Bit 7
MSB
(A7)
T LOW
Bit 0
LSB
(R/W)
Bit 6
(A6)
Acknowledge
(A)
STOP
condition
(P)
T HIGH
1/F SCL
SCL
TF
TR
T SP
T BUF
SDA
T HD;STA
T SU;DAT
T HD;DAT
T VD;DAT
T VD;ACK
FIGURE 18. WRITE TO OUTPUT
SDA
SLAVE
ADDRESS
W
A
IOSTATE REG.
A
DATA
A
T D1
GPIOn
43
T SU;STO
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
FIGURE 19. MODEM INPUT PIN INTERRUPT
SDA
SLAVE
ADDRESS
W
A
MSR REGISTER
A
S
SLAVE
ADDRESS
R
A
DATA
A
IRQ#
T D2
T D3
MODEM pin
FIGURE 20. GPIO PIN INTERRUPT
ACK from slave
SDA
SLAVE
ADDRESS
W
A
IOSTATE REG.
ACK from slave
S
A
SLAVE
ADDRESS
R
A
ACK from master
DATA
IRQ#
T D4
T D5
GPIOn
44
A
P
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
FIGURE 21. RECEIVE INTERRUPT
Start bit
Stop bit
Next
start
bit
RX
D0
D1
D2
D3
D4
D5
D6
D7
T D6
IRQ#
FIGURE 22. RECEIVE INTERRUPT CLEAR
SLAVE
ADDRESS
SDA
W
A
RHR
A
S
SLAVE
ADDRESS
R
A
DATA
IRQ#
T D7
FIGURE 23. TRANSMIT INTERRUPT CLEAR
SDA
SLAVE
ADDRESS
W
A
THR REGISTER
A
DATA
A
DATA
A
IRQ#
TD8
45
A
P
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS
Unless otherwise noted: TA=-40o to +85oC, Vcc=1.62 - 3.63V
SYMBOL
PARAMETER
MIN
MAX
UNIT
CONDITIONS
100
ns
CL = 100 pF
TTR
CS# HIGH to SO three-state time
TCSS
CS# to SCL setup time
100
ns
TCSH
CS# to SCL hold time
20
ns
TDO
SCL fall to SO valid time
TDS
SI to SCL setup time
100
ns
TDH
SI to SCL hold time
20
ns
TCP
SCL period
250
ns
TCH
SCL HIGH time
100
ns
TCL
SCL LOW time
100
ns
CS# HIGH pulse width
200
ns
TD9
SPI output data valid
200
ns
TD10
SPI modem output data valid
200
ns
TD11
SPI transmit interrupt clear
200
ns
TD12
SPI modem input interrupt clear
200
ns
TD13
SPI input pin interrupt clear
200
ns
TD14
SPI receive interrupt clear
200
ns
TCSW
100
ns
CL = 100 pF
TCH + TCL
FIGURE 24. SPI-BUS TIMING
CS#
...
T CSH
T CSS
T CL
T CH
T CSH
T CSW
...
SCLK
T DH
T DS
SI
...
T DO
SO
...
46
T TR
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
FIGURE 25. SPI WRITE MCR TO DTR OUTPUT SWITCH
CS#
SCLK
SI
R/W
A3
A2
A1
A0
CH1
CH0
X
D7
D6
D5
D4
D3
D2
D1
D0
T D9
GPIOx
FIGURE 26. SPI WRITE MCR TO DTR OUTPUT SWITCH
CS#
SCLK
SI
R/W
A3
A2
A1
A0
CH1
CH0
X
D7
D6
D5
D4
D3
D2
D1
D0
T D10
DTR#
(GPIO5)
47
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
FIGURE 27. SPI WRITE THR TO CLEAR TX INT
CS#
SCLK
SI
R/W
A3
A2
A1
A0
CH1
CH0
X
D7
D6
D5
D4
D3
D2
D1
D0
GPIOx
td11
IRQ#
FIGURE 28. READ MSR TO CLEAR MODEM INT
CS#
SCLK
SI
R/W
A3
A2
A1
A0
CH1
CH0
X
D7
SO
T D12
IRQ#
48
D6
D5
D4
D3
D2
D1
D0
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
FIGURE 29. READ IOSTATE TO CLEAR GPIO INT
CS#
SCLK
SI
R/W
A3
A2
A1
A0
CH1
CH0
X
D7
SO
D6
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
T D13
IRQ#
FIGURE 30. READ RHR TO CLEAR RX INT
CS#
SCLK
SI
R/W
A3
A2
A1
A0
CH1
CH0
X
SO
D7
T D14
IRQ#
49
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
PACKAGE DIMENSIONS (64 PIN QFN - 9 X 9 X 0.9 mm)
Note: the actual center pad is
metallic and the size (D2) is
device-dependent with a
typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.031
0.039
0.80
1.00
A1
0.000
0.002
0.00
0.05
A3
0.006
0.010
0.15
0.25
D
0.350
0.358
8.90
9.10
D2
0.295
0.307
7.50
7.80
b
0.007
0.012
0.18
0.30
e
0.0197 BSC
0.50 BSC
L
0.012
0.020
0.30
0.50
k
0.008
-
0.20
-
50
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
REVISION HISTORY
DATE
REVISION
DESCRIPTION
February 2007
P1.0.0
Preliminary Datasheet.
February 2007
P1.0.1
VCC range updated to +3.3 to +5.5V.
July 2007
1.0.0
Final Datasheet. Corrected R_EN pin description and pinout. Corrected IEC spec #
on page 1.
July 2008
1.0.1
Added "not 5V tolerant" and "5V tolerant" in Pin description.
Deleted "Voltage at any pin" on page 39.
Corrected VIH in Electrical Characteristics Table on page 40.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2008 EXAR Corporation
Datasheet July 2008.
Send your UART technical inquiry with technical details to hotline: [email protected]
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
51
XR20V2172
REV. 1.0.1
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
APPLICATIONS .............................................................................................................................................. 1
FEATURES .................................................................................................................................................... 1
FIGURE 1. XR20V2172 BLOCK DIAGRAM ......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION ............................................................................................................................... 2
PIN DESCRIPTIONS ....................................................................................................... 3
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 7
2.1 CPU INTERFACE ................................................................................................................................................ 7
2.1.1 I2C-BUS INTERFACE .....................................................................................................................................................
FIGURE 3. I2C START AND STOP CONDITIONS .................................................................................................................................
FIGURE 4. MASTER WRITES TO SLAVE (V2172) ...............................................................................................................................
FIGURE 5. MASTER READS FROM SLAVE (V2172) ............................................................................................................................
7
7
7
7
2.2 I2C-BUS ADDRESSING ...................................................................................................................................... 8
TABLE 1: XR20V2172 I2C ADDRESS MAP ....................................................................................................................................... 8
TABLE 2: I2C SUB-ADDRESS ............................................................................................................................................................ 8
2.2.1 SPI BUS INTERFACE ..................................................................................................................................................... 9
TABLE 3: SPI FIRST BYTE FORMAT .................................................................................................................................................. 9
2.3 DEVICE RESET ................................................................................................................................................... 9
2.4 INTERNAL REGISTERS...................................................................................................................................... 9
2.5 IRQ# OUTPUT ..................................................................................................................................................... 9
TABLE 4: IRQ# PIN OPERATION FOR TRANSMITTER .......................................................................................................................... 9
TABLE 5: IRQ# PIN OPERATION FOR RECEIVER ............................................................................................................................. 10
2.6 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 10
FIGURE 6. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 10
2.7 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 10
FIGURE 7. BAUD RATE GENERATOR ............................................................................................................................................... 11
TABLE 6: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 12
2.8 TRANSMITTER.................................................................................................................................................. 12
2.8.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY...........................................................................................
2.8.2 TRANSMITTER OPERATION IN NON-FIFO MODE ....................................................................................................
FIGURE 8. TRANSMITTER OPERATION IN NON-FIFO MODE ..............................................................................................................
2.8.3 TRANSMITTER OPERATION IN FIFO MODE .............................................................................................................
FIGURE 9. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE .....................................................................................
12
13
13
13
13
2.9 RECEIVER ......................................................................................................................................................... 14
2.9.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .............................................................................................. 14
FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................. 14
FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 15
2.10 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 15
2.11 AUTO RTS HALT AND RESUME .................................................................................................................. 15
2.12 AUTO CTS FLOW CONTROL........................................................................................................................ 15
FIGURE 12. AUTO RTS AND CTS FLOW CONTROL OPERATION ....................................................................................................... 16
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 17
2.14 SPECIAL CHARACTER DETECT.................................................................................................................. 17
2.15 SLEEP MODE WITH AUTO WAKE-UP ......................................................................................................... 17
2.15.1 PARTIAL SLEEP MODE.............................................................................................................................................
2.15.1.1 UART IN SLEEP MODE, RS-232 TRANSCEIVER ACTIVE.........................................................................................
2.15.1.2 UART ACTIVE, CHARGE PUMP OF RS-232 TRANSCEIVER SHUT DOWN ..................................................................
2.15.2 FULL SLEEP MODE ...................................................................................................................................................
17
17
18
18
2.16 INFRARED MODE (UART CHANNEL B ONLY)............................................................................................. 19
FIGURE 13. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 19
2.17 INTERNAL LOOPBACK................................................................................................................................. 20
FIGURE 14. INTERNAL LOOP BACK ................................................................................................................................................. 20
3.0 UART INTERNAL REGISTERS............................................................................................................. 21
TABLE 7: UART INTERNAL REGISTER ADDRESSES .............................................................................................................. 21
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 22
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 23
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 23
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 23
I
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.1
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 23
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 24
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 24
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 25
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 26
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 26
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 27
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 28
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 29
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 29
TABLE 12: REGISTER AT ADDRESS OFFSET 0X6 ............................................................................................................................. 30
TABLE 13: REGISTER AT ADDRESS OFFSET 0X7 ............................................................................................................................. 30
4.8 LINE STATUS REGISTER (LSR) - READ ONLY..............................................................................................
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .......................................................................................
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .......................................................................................
4.11 TRANSMISSION CONTROL REGISTER (TCR) - READ/WRITE (REQUIRES EFR BIT-4 = 1).....................
4.12 TRIGGER LEVEL REGISTER (TLR) - READ/WRITE (REQUIRES EFR BIT-4 = 1) ......................................
4.13 TRANSMIT FIFO LEVEL REGISTER (TXLVL) - READ-ONLY.......................................................................
4.14 RECEIVE FIFO LEVEL REGISTER (RXLVL) - READ-ONLY .........................................................................
4.15 GPIO DIRECTION REGISTER (IODIR) - READ/WRITE .................................................................................
4.16 GPIO STATE REGISTER (IOSTATE) = READ/WRITE...................................................................................
4.17 GPIO INTERRUPT ENABLE REGISTER (IOINTENA) - READ/WRITE .........................................................
4.18 GPIO CONTROL REGISTER (IOCONTROL) - READ/WRITE........................................................................
4.19 EXTRA FEATURES CONTROL REGISTER (EFCR) - READ/WRITE............................................................
4.20 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD[3:0]) - READ/WRITE................................
31
32
33
33
33
33
33
33
34
34
34
35
35
TABLE 14: SAMPLING RATE SELECT ............................................................................................................................................... 35
4.21 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 36
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 36
4.21.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 37
TABLE 16: UART RESET STATES ............................................................................................................................................... 38
5.0 ELECTRICAL CHARACTERISTICS ...................................................................................................... 39
ABSOLUTE MAXIMUM RATINGS..................................................................................................................... 39
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) .............................................. 39
AC ELECTRICAL CHARACTERISTICS - UART CLOCK ..................................................................................... 41
FIGURE 15. CLOCK TIMING ............................................................................................................................................................. 41
AC ELECTRICAL CHARACTERISTICS - I2C-BUS TIMING SPECIFICATIONS ........................................................ 42
FIGURE 16. SCL DELAY AFTER RESET........................................................................................................................................... 43
FIGURE 17. I2C-BUS TIMING DIAGRAM .......................................................................................................................................... 43
FIGURE 18. WRITE TO OUTPUT ...................................................................................................................................................... 43
FIGURE 19. MODEM INPUT PIN INTERRUPT ..................................................................................................................................... 44
FIGURE 20. GPIO PIN INTERRUPT .................................................................................................................................................. 44
FIGURE 21. RECEIVE INTERRUPT .................................................................................................................................................... 45
FIGURE 22. RECEIVE INTERRUPT CLEAR ......................................................................................................................................... 45
FIGURE 23. TRANSMIT INTERRUPT CLEAR ....................................................................................................................................... 45
AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS ........................................................ 46
FIGURE 24. SPI-BUS TIMING .......................................................................................................................................................... 46
FIGURE 25. SPI WRITE MCR TO DTR OUTPUT SWITCH ................................................................................................................. 47
FIGURE 26. SPI WRITE MCR TO DTR OUTPUT SWITCH ................................................................................................................. 47
FIGURE 27. SPI WRITE THR TO CLEAR TX INT ............................................................................................................................. 48
FIGURE 28. READ MSR TO CLEAR MODEM INT.............................................................................................................................. 48
FIGURE 29. READ IOSTATE TO CLEAR GPIO INT........................................................................................................................... 49
FIGURE 30. READ RHR TO CLEAR RX INT .................................................................................................................................... 49
PACKAGE DIMENSIONS (64 PIN QFN - 9 X 9 X 0.9 mm) .............................................. 50
REVISION HISTORY...................................................................................................................................... 51
II