TI TPS5103IDBR

TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
D
D
D
D
D
D
D
D
D
D
Step-Down DC-DC Converter
Three Operation-Mode
– Heavy Load:
– Fixed Frequency PWM
– Hysteretic (User Selctable)
– Light Load:
– Skip Mode
4.5 V to 25 V Input Voltage Range
Adjustable Output Voltage Down to 1.2 V
95% Efficiency
Stand-By Control
Over Current Protection
UVLO for Internal 5 V Regulation
Low Standby Current . . . 0.5 mA Typical
TA = –40°C to 85°C
DB PACKAGE
(TOP VIEW)
SOFTSTART
INV
FB
CT
RT
GND
REF
COMP
PWMSKIP
STBY
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
LH
OUT_u
LL
OUT_d
OUTGND
TRIP
VCC_SENSE
VCC
VREF5
VREG5V_IN
description
The TPS5103 is a synchronous buck dc/dc controller, designed for notebook PC system power. The controller
has three user-selectable operation modes available; hysteretic mode, fixed frequency PWM control, or SKIP
control.
In high current applications, where fast transient response is advantageous for reducing bulk capacitance, the
hysteretic mode is selected by connecting the Rt pin to Vref5. Selecting the PWM/SKIP modes for less
demanding transient applications is ideal for conserving notebook battery life under light load conditions. The
device includes high-side and low-side MOSFET drivers capable of driving low Rds (on) N–channel MOSFETs.
The user-selectable overcurrent protection (OCP) threshold is set by an external TRIP pin resister in order to
protect the system. The TPS5103 is configured so that a current sense resistor is not required, improving the
operating efficiency.
C4
5V
R1
C1
R2
C2
U1
TPS5103
1
2
3
4
5
6
7
8
9
10
SOFTSTART
LH
INV
OUTU
FB
LL
CT
OUTD
RT
OUTGND
GND
TRIP
REF
VCCSENSE
COMP
VCC
PWM/SKIP
VREF5
STBY
VREG5V_IN
D1
20
19
18
17
16
15
14
13
12
11
Q1
C3
OUTPUT
L1
R3
C5
+
Q2
R4
Figure 1. Typical Design
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
functional block diagram
SOFT START
Soft Start
_
+
FB
PWM Comp.
_
_
INV
+
LH
OUT_u
+
Error Amp
LL
1.185 V
OUT_d
OUTGND
One Shot ON
PWMSKIP
_
TRIP
+
CT
RT
OSC
Disable
_
VCC_SENSE
+
_
1.185 V
UVLO
+
VREF5
Comp
GND
VCC
VREF
_
STBY
REF
+
1.185 V
VREG5V_IN
AVAILABLE OPTIONS
TA
–40
40 °C to 85 °C
2
PACKAGE
SSOP(DB)
EVM
TPS5103IDB
TPS5103EVM–136
TPS5103IDBR
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
COMP
8
I
Comparator input for voltage monitor
CT
4
I/O
External capacitor from CT to GND for adjusting the triangle oscillator and decreasing the current limiting
voltage
FB
3
O
Feedback output of error amp
GND
6
INV
2
I
Inverting input of both error amp and hysteretic comparator
LH
20
I/O
Bootstrap. Connect 1 µF low-ESR capacitor from LH to LL.
LL
18
I/O
Bootstrap low. High side gate driving return and output current protection. Connect to the junction of the high
side and low side FETs for floating drive configuration.
OUT_d
17
I/O
Gate-drive output for low-side power switching FETs
OUTGND
16
OUT_u
19
O
Gate-drive output for high-side power switching FETs
PWMSKIP
9
I
PWM/SKIP mode select
L:PWM mode
H:SKIP mode
REF
7
O
1.185-V reference voltage output
RT
SOFTSTART
5
I/O
External resistor connection for adjusting the triangle oscillator.
1
I
External capacitor from SOFTSTART to GND for soft start control
STBY
10
I
Standby control
TRIP
15
I
External resistor connection for output current control
VCC
VCC_SENSE
13
I
Supply voltage input
14
I
Supply voltage sense for current protection
VREF5
12
O
5-V-internal regulator output
VREG5V_IN
11
I
External 5-V input (input voltage range = 4.5 V to 25 V)
Control GND
Ground for FET drivers
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
detailed description
REF
The reference voltage is used for the output voltage setting and the voltage protection(COMP). The tolerance
is 1.5% typically.
VREF5
An internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage
range is from 4.5 V to 25 V, this voltage offers a fixed voltage for the bootstrap voltage so that the design for
the bootstrap is much easier. The tolerance is 6%.
hysteretic comparator
The hysteretic comparator is used to regulate the output voltage of the synchronous-buck converter. The
hysteresis is set internally and is typically 9.7 mV. The total delay time from the comparator input to the driver
output is typically 400 ns for going both high and low.
error amplifier
The error amplifier is used to sense the output voltage of the synchronous buck converter. The negative input
of the error amplifier is connected to the Vref voltage(1.185 V) with a resistive divider network. The output of
the error amplifier is brought out to the FB terminal to be used for loop gain compensation.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V
from VREF5. The current rating of driver is typically 1.2 A at sink current, –1.5 A at source current.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
1.2 A at sink current, –1.7 A at source current. When configured as a floating driver, the bias voltage to the driver
is developed from the VREF5, limiting the maximum drive voltage between OUT_u and LL to 5 V. The maximum
voltage that can be applied between LH and OUTGND is 30 V.
driver deadtime control
The deadtime control prevents shoot-through current from flowing through the main power FETs. During
switching transitions the deadtime control actively controls the turnon time of the MOSFET drivers. The typical
deadtime from the low-side-driver-off to the high-side-driver-on is 90 ns, and 110 ns from high-side-driver-off
to low-side-driver-on.
COMP
COMP is designed for use with a regulation output monitor. COMP also functions as an internal comparator
used for any voltage protection such as the input under voltage protection. If the input voltage is lower than the
setpoint, the comparator turns off and prevents external parts from damage. The investing terminal of the
comparator is internally connected to REF(1.185 V).
current protection
Current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during
on-time through VCC_SENSE and LL terminals. An external resistor between Vin and TRIP terminal with the
internal current source connected to the current comparator negative input adjusts the current limit. The typical
internal current source value is 15 µA in PWM mode, 5 µA in SKIP mode. When the voltage on the positive
terminal is lower than the negative terminal, the current comparator turns on the trigger, and then activates the
oscillator. This oscillator repeatedly reset the trigger until the over current condition is removed. The capacitor
on the CT terminal can be open or added to adjust the reset frequency.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
detailed description (continued)
softstart
SOFTSTART sets the sequencing of the output for any possibility. The capacitor value for a start-up time can
be calculated by the following equation: C = 2xT (uF) where C is the external capacitor value, T is the required
start-up time in (ms).
standby
This controller can be switched into standby mode by grounding the STBY terminal. When it is in standby mode,
the quiescent current is less than 1.0 uA.
UVLO
The under-voltage-lock-out (ULVO) threshold is approximately 3.8 V. The typical hysteresis is 55 mV.
5-V Switch
5-V Switch if the internal 5-V switch senses a 5-V input from REG5V terminal, the internal 5-V linear regulator
will be disconnected from the MOSFET drivers. The external 5 V will be used for both the low-side driver and
the high-side bootstrap, thus increasing the efficiency.
PWM/SKIP switch
The PWM/SKIP switch selects the output operating mode. This controller has three operational modes, PWM,
SKIP, and Hysteretic. The PWM and SKIP mode control should be used for slower transient applications.
oscillator
The oscillator gives a triangle wave by connecting an external resistor to the RT terminal and an external
capacitor to the CT terminal. The voltage amplitude is 0.43 V ~ 1.17 V. This wave is connected to the noninverting input of the PWM comparator.
Comparison Table Between PWM Mode and Hysteretic Mode
MODE
PWM
HYSTERETIC
Frequency
Fixed
Not Fixed
Transient Response
Normal
Very fast
Feed back compensation
Need
Needless
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V
Input voltage, VI, INV, CT, RT, PWM/SKIP, SOFTSTART, COMP . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Input voltage, VREG5V_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Input voltage, STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Input voltage, TRIP, VCC_SENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Low level output voltage, VOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 27 V
High level output voltage, VOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 32 V
Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. See Dissipation Rating Table for free-air temperature range above 25°C.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
DB
801 mW
6.408mW/°C
416 mW
recommended operating conditions
MIN
VCC
Supply voltage
NOM
4.5
25
INV, CT, RT, COMP, PWM_SKIP, SOFTSTART
VI
Input voltage
5.5
STBY
12
f
Timing capacitor
Frequency
– 40
POST OFFICE BOX 655303
V
82
kΩ
100
pF
200
TA
Operating temperature range
‡ Not a JEDEC symbol.
6
V
25
Timing register
Oscillator frequency
UNIT
6
VREG5V_IN
TRIP, VCC_SENCE
RT‡
CT‡
MAX
• DALLAS, TEXAS 75265
kHz
85
°C
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V
(unless otherwise noted)
reference voltage
PARAMETER
TEST CONDITIONS
Vreff
Reference voltage
TA = 25°C,
Ivref = 50 µA‡
Ivref = 50 µA
Regin
Line regulation†
Load regulation†
VCC = 4.5 V to 25 V,
I = 1 µA to 1 mA
I = 50 µA
Regl
† Not a JEDEC symbol.
MIN
TYP
MAX
1.167
1.185
1.203
1.155
1.215
UNIT
V
0.2
12
mV
0.5
10
mV
TYP
MAX
UNIT
500
kHz
oscillator
PARAMETER
f
Frequency
RT
fdv
Timing resistor
fdt
TEST CONDITIONS
MIN
PWM mode
47
Frequency change†
VHL‡
High level output voltage
High-level
VLL‡
Low level output voltage
Low-level
VCC = 4.5 V to 25 V
TA = – 40°C to 85°C
kΩ
0.1%
2%
DC includes internal comparator error
1
f = 200 kHz, includes internal comparator error
DC includes internal comparator error
1.1
1.2
1.17
0.4
f = 200 kHz, includes internal comparator error
0.5
0.6
0.43
V
V
† Not a JEDEC symbol.
‡ The output voltages of oscillator (f = 200 kHz) are ensured by design.
error amp
PARAMETER
V
Input offset voltage
Av
Open-loop voltage gain†
Unity-gain bandwidth†
GB
IO
IS
TEST CONDITIONS
MIN
TA = 25°C
TYP
MAX
2
10
50
Output sink current
VO = 0.4 V
Output source current
VO = 1 V
30
UNIT
mV
dB
0.8
MHz
45
µA
300
µA
† Not a JEDEC symbol.
hysteresis comparator§
PARAMETER
TEST CONDITIONS
Vhsy
Vp-VS
Hysteresis window
Hysteretic mode
I
Bias current
tPHL
tPLH
Propagation delay from INV to OUT_U
MIN
TYP
MAX
6
9.7
13
Offset voltage
UNIT
mV
2
mV
10
pA
TTL input signal
230
ns
10 mV overdrive on hysteresis band signal
400
ns
§ The numbers in the table include the driver delay. All numbers are ensured by design.
control
PARAMETER
VIHA
High level input voltage
High-level
VILA
Low level input voltage
Low-level
TEST CONDITIONS
STBY
PWM_SKIP
POST OFFICE BOX 655303
MIN
TYP
MAX
2.5
V
2
STBY
0.5
PWM_SKIP
0.5
• DALLAS, TEXAS 75265
UNIT
V
7
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V
(unless otherwise noted) (continued)
5-V regulator
PARAMETER
VO
Regin
Regl
TEST CONDITIONS
Output voltage
I = 10 mA
Line regulation†
Load regulation†
VCC = 5.5 V to 25 V,
I = 1 mA to 10 mA,
IOS
Short-circuit output current
† Not a JEDEC symbol.
MIN
TYP
4.7
MAX
UNIT
5.3
V
I = 10 mA
20
mV
VCC = 5.5 V
40
mV
Vref = 0 V
70
mA
5-V switch
PARAMETER
VIT(high)
VIT(low)
TEST CONDITIONS
Threshold voltage†
Vhsy
Hysteresis)
† Not a JEDEC symbol.
MIN
TYP
MAX
4.2
4.9
4.1
4.8
UNIT
V
50
150
250
mV
MIN
TYP
MAX
UNIT
UVLO
PARAMETER
VIT(high)
VIT(low)
TEST CONDITIONS
Threshold voltage†
Vhys
Hysteresis
† Not a JEDEC symbol.
3.6
4.2
3.5
4.1
10
150
mV
MAX
UNIT
V
output
PARAMETER
IO
IS
OUT_u sink curent
IO
IS
OUT_d sink current
I
OUT_u source current
OUT_d source current
TRIP terminal current
MIN
TYP
VO = 3 V
VO = 2 V
TEST CONDITIONS
0.5
1.2
A
–1
–1.7
A
VO = 3 V
VO = 2 V
0.5
1.2
A
–1
–1.5
PWM mode,
VTRIP = 7 V
10
15
20
A
SKIP mode,
VTRIP = 7 V
3
5
7
µA
High side driver is GND referenced.
Input: INV = 0 – 3V
tr
Rise time
tr/tf = 10 ns,
CL = 2200 pF
ns
Frequency = 200 kHz
28
CL = 3300 pF
39
High side driver is GND referenced.
Input: INV = 0 – 3 V
tf
Fall time
tr/tf = 10 ns,
CL = 2200 pF
CL = 3300 pF
8
POST OFFICE BOX 655303
ns
Frequency = 200 kHz
• DALLAS, TEXAS 75265
30
38
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V
(unless otherwise noted) (continued)
softstart
PARAMETER
I(CTRL)
VIT(high)
VIT(low)
TEST CONDITIONS
Softstart current
MIN
TYP
MAX
1.9
2.5
3
3.9
Threshold voltage (SKIP mode)†
UNIT
µA
V
2.6
† Not a JEDEC symbol.
output voltage monitor
PARAMETER
VIT
TEST CONDITIONS
Threshold voltage
MIN
TYP
MAX
UNIT
1.08
1.18
1.28
V
MIN
TYP
MAX
UNIT
driver deadtime section
PARAMETER
TDRVLH
TDRVHL
TEST CONDITIONS
Low-side to high-side
90
ns
High-side to low-side
110
ns
whole device
PARAMETER
ICC
I
TEST CONDITIONS
MIN
Supply current
Shutdown current
STBY = 0 V
SOFTSTART
0.1 µF
OUT_u
FB
LL
CT
OUT_d
RT
OUTGND
GND
TRIP
REF
VCC_SENSE
PWM SKIP
STBY
MAX
0.5
1.2
UNIT
mA
0.01
10
µA
LH
INV
COMP
TYP
VCC
VREF5
0.1 µF
7V
5V_IN
5V
Figure 2. Test Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
QUIESCENT CURRENT
vs
JUNCTION TEMPERATURE
700
50
45
600
VCC = 25 V
550
VCC = 7 V
500
VCC = 4.5 V
450
400
I CCS – Quiescent Current – µ A
I CC – Quiescent Current – µ A
650
VCC = 25 V
40
35
VCC = 7 V
30
25
VCC = 4.5 V
20
15
10
350
5
300
–40
–20
25
85
TJ – Junction Temperature – °C
0
125
–40
–20
Figure 3
125
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT
5.5
3
VCC = 7 V,
TJ = 25°C
VCC = 7 V,
TJ = 25°C
V(OUT_u)– Drive Output Voltage – V
V(OUT_u)– Drive Output Voltage – V
85
Figure 4
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT
5
4.5
4
3.5
3
1
0.7
I(OUT_source) – Drive Source Current – A
0.1
2.5
2
1.5
1
0.5
0
1
0.1
0.7
I(OUT_sink) – Drive Source Current – A
Figure 5
10
25
TJ – Junction Temperature – °C
Figure 6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT
4.5
6
TJ = 25°C
TJ = 25°C
V(OUT_d)– Drive Output Voltage – V
V(OUT_d)– Drive Output Voltage – V
4
5
4
3
2
1
3.5
3
2.5
2
1.5
1
0.5
0
0
1
0.1
0.7
I(OUT_sink) – Drive Source Current – A
1
0.7
I(OUT_source) – Drive Source Current – A
0.1
Figure 7
Figure 8
OSCILLATOR OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
OSCILLATOR OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
500
V(oscl)– Oscillator Output Voltage – V
V(osch)– Oscillator Output Voltage – V
1.125
1.115
1.105
1.095
VCC = 4.5 V,
VCC = 7 V,
VCC = 25 V
1.085
495
490
VCC = 4.5 V,
VCC = 7 V,
VCC = 25 V
485
480
1.075
–40
–20
25
85
125
TJ – Junction Temperature – °C
–40
Figure 9
85
125
–20
25
TJ – Junction Temperature – °C
Figure 10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER INPUT OFFSET VOLTAGE
vs
JUNCTION TEMPERATURE
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
Vom+– Error Amplifier Output Voltage – mV
Vio– Error Amplifier Input Offset Voltage – mV
2.5
2
1.5
VCC = 4.5 V,
VCC = 7 V,
VCC = 25 V
1
0.5
2
1.5
1
0.5
0
–40
VCC = 4.5 V,
VCC = 7 V,
VCC = 25 V
0
85
125
–20
25
TJ – Junction Temperature – °C
–40
85
125
–20
25
TJ – Junction Temperature – °C
Figure 12
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
Vom–– Error Amplifier Output Voltage – mV
6.2
6
5.8
VCC = 4.5 V,
VCC = 7 V,
VCC = 25 V
5.6
5.4
5.2
5
4.8
4.6
4.4
–40
–20
25
85
125
TJ – Junction Temperature – °C
Vhys– Hysteresis Comparator Hysteresis Voltage – mV
Figure 11
HYSTERESIS COMPARATOR HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
10.5
VCC = 7 V
10.25
10
9.75
9.5
9.25
9
–40
Figure 13
12
–20
25
85
125
TJ – Junction Temperature – °C
Figure 14
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
VREF5 OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
2.5
5.2
VCC = 4.5 V,
VCC = 7 V
2
VCC = 25 V
1.5
VCC = 25 V
1
VCC = 4.5 V
VCC = 7 V
0.5
TJ = –40°C
5.1
VO – VREF5 Output Voltage – V
VIH,VIL – Standby Switch Threshold Voltage – V
STANDBY SWITCH THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
5
TJ = 125°C
4.9
TJ = 25°C
4.8
4.7
4.6
4.5
4.4
4.3
0
95
–25
25
TJ – Junction Temperature – °C
–45
4.2
135
20
10
VCC – Supply Voltage – V
0
Figure 15
Figure 16
VREF5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VREF5 SHORT CURRENT
vs
JUNCTION TEMPERATURE
6
–100
TJ = 125°C
VCC = 25 V
I OS– VREF5 Short Current – mA
VO – VREF5 Output Voltage – V
5
TJ = 25°C
4
3
TJ = –40°C
2
1
0
0
–10
–20 –30
–40 –50
IO – Output Current – mA
–60
–70
–80
–60
VCC = 4.5 V
VCC = 7 V
–40
–20
0
–40
Figure 17
–20
25
85
TJ – Junction Temperature – °C
125
Figure 18
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
UVLO HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
80
Vhys– UVLO Hysteresis Voltage – mV
VTHL,VTLH – UVOL Threshold Voltage – V
4
3.95
VTLH
3.90
3.85
VTHL
3.80
3.75
70
60
50
40
30
20
10
0
3.70
–40
85
–20
25
TJ – Junction Temperature – °C
–40
125
Figure 19
5 VSW HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
200
4.75
180
Vhys– 5V SW Hysteresis Voltage – mV
VTHL,VTLH – 5 VSW Threshold Voltage – V
4.80
VTLH
4.65
4.60
VTHL
4.55
4.50
4.45
4.40
160
140
120
100
80
60
40
20
0
4.35
–45
95
–25
25
TJ – Junction Temperature – °C
135
–45
Figure 21
14
125
Figure 20
5 VSW THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
4.70
85
–20
25
TJ – Junction Temperature – °C
–25
25
95
TJ – Junction Temperature – °C
Figure 22
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SOFTSTART THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
SOFTSTART CURRENT
vs
JUNCTION TEMPERATURE
4.5
VTLH – Softstart Threshold Voltage – V
I CTRL – Softstart Current – µ A
–2.45
–2.40
–2.35
VCC = 4.5 V
VCC = 7 V
–2.30
VCC = 25 V
–2.25
4
3.5
3
2.5
VCC = 7 V,
VCC = 25 V
2
1.5
1
0.5
0
–2.20
–40
85
–20
25
TJ – Junction Temperature – °C
–40
125
Figure 23
85
125
–20
25
TJ – Junction Temperature – °C
Figure 24
OUTPUT VOLTAGE MONITOR COMPARATOR
THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
SOFTSTART THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
3.5
1.195
VTH– Output Voltage Monitor Comparator
Threshold Voltage – V
VTHL – Softstart Threshold Voltage – V
VCC = 4.5 V
3
VCC = 7 V,
VCC = 25 V
2.5
2
VCC = 4.5 V
1.5
1
–40
–20
25
85
TJ – Junction Temperature – °C
125
1.193
1.190
1.188
VCC = 4.5 V,
VCC = 7 V,
VCC = 25 V
1.185
1.183
1.180
–40
85
–20
25
TJ – Junction Temperature – °C
125
Figure 26
Figure 25
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
OSCILLATOR OUTPUT VOLTAGE
vs
FREQUENCY
600
VOSCH,VOSCL– Oscillator Output Voltahe – V
1.6
Fosc– Oscillator Frequency – kHz
F = 500 kHz
500
VCC = 4.5 V,
VCC = 7 V,
VCC = 25 V
400
VCC = 4.5 V,
VCC = 7 V,
VCC = 25 V
300
200
F = 200 kHz
100
0
–40
85
–20
25
TJ – Junction Temperature – °C
125
1.4
VOSCH
1.2
1
0.8
0.6
VOSCL
0.4
0.2
0
10
Figure 27
100
FOSC – Frequency – kHz
Figure 28
ERROR AMPLIFIER GAIN AND PHASE SHIFT
180
60
Rs = 100 Ω,
Rf = 10 kΩ
50
Phase
40
100
30
Gain
20
60
10
20
0
–20
–10
–20
1.E+03
1.E+04
1.E+05
1.E+06
f – Frequency – Hz
Figure 29
16
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–60
1.E+07
Phase Shift – Deg
Error Amplifier Gain – dB
140
1000
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
MAXIMUM DUTY CYCLE
vs
JUNCTION TEMPERATURE
SOFTSTART CAPACITANCE
vs
SOFTSTART TIME
100
104
f = 200 kHz
C SS – Softstart Capacitance – pF
99.5
Maximum Duty Cycle – %
99
98.5
98
97.5
97
96.5
96
103
102
95.5
95
100
0.01
85
125
–20
25
TJ – Junction Temperature – °C
–40
0.1
1
10
TSS – Soft Start Time – ms
Figure 30
Figure 31
DRIVER DEAD TIME
vs
JUNCTION TEMPERATURE
CURRENT PROTECTION SOURCE CURRENT
vs
INPUT VOLTAGE PWM MODE
14.5
TDRVHL
VCC = 4.5 V
120
100
TDRVLH
80
VCC = 7 V,
VCC = 25 V
VCC = 4.5 V
VCC = 7 V,
VCC = 25 V
40
20
0
–45
95
–25
25
TJ – Junction Temperature – °C
135
I TRIP– Corrent Protection Source Current –µ A
T DRVLH,TDRVHL– Driver Dead Time – ns
140
60
100
14.25
TA = 125°C
14
13.75
TA = 25°C
13.5
13.25
TA = –40°C
13
12.75
12.5
4.5
Figure 32
7
VTRIP – Input Voltage – V
25
Figure 33
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
TYPICAL CHARACTERISTICS
CURRENT PROTECTION SOURCE CURRENT
vs
INPUT VOLTAGE SKIP MODE
I TRIP– Corrent Protection Source Current –µ A
4.6
TA = 125°C
4.5
4.4
TA = 25°C
4.3
4.2
TA = –40°C
4.1
4
4.5
7
VTRIP – Input Voltage – V
25
Figure 34
OSCILLATOR FREQUENCY
vs
RESISTOR
700
Fosc– Oscillator Frequency – kHz
CT = 10 pF
600
CT = 15 pF
500
CT = 22 pF
400
CT = 33 pF
300
200
CT = 470 pF
CT = 680 pF
100
0
10
100
RT – Resistor – kΩ
Figure 35
18
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
overshoot of output rectangle wave
The drivers in the TPS5103 controller are fast and can produce high transients on VCC or the junction of Q1 and
Q2(shown below). Care must be taken to insure that these transients do not exceed the absolute maximum
rating for the device or associated external component. A low-ESR capacitor connected directly from Q1 drain
to Q2 source can greatly reduce transient pulses on VCC. Also, Q1 turn-on-speed can be reduced by adding
a resistor (5 – 15 Ω) in series with OUT_u. Poor layout of the switching node (V1 in figure) can result in the
requirement for additional snubber circuitry require from V1 to ground.
C1
VCC
Q1
OUT_u
V1
Q2
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
application for general power
The design shown in this data sheet is a reference design for a general power supply application. An evaluation
module (EVM), TPS5103EVM-136 (SLVP136), is available for customer testing and evaluation. The intent is
to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here. For subsequent
customer board revisions, the EVM design can be copied onto the users PCB to shorten design cycle time,
component count, and board cost.
To help the customers to design the power supply using TPS5103, some key design procedures are shown
below.
R2
C4
J1
C15
R3
TP18
J2
Q1
C5
C6
R6B
C8
J4
J5
R11
R5
C7
L1
D2
TP1
TP17
TP2
TP16
TP3
TP15
TP4
TP14
C2
TP6
J7
C10
D1
C12
TP8
TP12
TP9
TP11
C11
C13
R13
R10
R9
Figure 36. EVM Schematic
20
J9
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J11
J13
TP10
JP2
J8
J10
R12
TP13
TP7
JP1
+
C3
R6A
C9
J6
Q2
TP5
R7
J3
R1
R4
C14
+ C1
TP26
• DALLAS, TEXAS 75265
J14
J12
Vi
Vi
Input GND
Input GND
Input GND
SENSE
Vo
Vo
Vo
VoGND
VoGND
VoGND
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
output voltage setpoint calculation
The output voltage is set by the reference voltage and the voltage divider. In TPS5102, the reference voltage
is 1.185 V, and the divider is composed of two resistors in the EVM design that are R4 and R5, or R14 and R15.
The equation for the setpoint is:
R2
Vr
+ R1
Vo * Vr
Where R1 is the top resistor (kΩ) like R4 or R15; R2 is the bottom resistor (kΩ) such as R5 or R14; Vo is the
required output voltage (V); Vr is the reference voltage (1.185 V in TPS5103).
Example: R1 = 1 kΩ; Vr = 1.185 V; Vo = 1.8 V, then R2 = 1.9 kΩ.
For your convenience, some of the most popular output voltage setpoints are calculated in the table below:
Vo
1.3 V
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
R1 (top) (kΩ)
1
1
1
1
1
1
R2 (bottom) (kΩ)
10
3.7
1.9
0.9
0.56
0.31
If higher precision resistor is used, the output voltage setpoint can be more accurate.
In some applications, the output voltage is required to be lower than the reference voltage. With few extra
components, the lower voltage can be easily achieved. The drawing below shows the method.
VCC
VO
R(top)
Rz1
Rz2
INV
TPS5103
Zener
R(bottom)
In the schematic, the Rz1, Rz1, and the zener are the extra components. Rz1 is used to give zener enough
current to build up the zener voltage. The zener voltage is added to INV through Rz2. Therefore, the voltage
on INV is still equal to the IC internal voltage (1.185 V) even if the output voltage is regulated at lower setpoint.
The equation for setting up the output voltage is shown below:
Rz2
(Vz–Vr)
+ ǒVr–Vo
Ǔ ) Vr
Rtop
Rbtm
Where Rz2 is the adjusting resistor for low output voltage; Vz is the zener voltage; Vr is the internal reference
voltage; Rtop is the top resistor of voltage sensing network; Rbtm is the bottom resistor of the sensing network;
Vo is the required output voltage setpoint.
Example: Assuming the required output voltage setpoint is Vo = 0.8 V, Vz = 5 V; Rtop = 1 kΩ; Rbottom = 1 kΩ,
then the Rz2 = 2.43 kΩ.
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
switching frequency
With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the
hysteresis window, the delay of the hysteresis comparator and the driver, the output inductance, the resistance
in the output inductor, the output capacitance, the ESR and ESL in the output capacitor, the output current, and
the turnon resistance of high side and low side MOSFET. It is a very complex equation if everything is included.
To make it more useful to the designers, a simplified equation only considers the most influential factors. The
tolerance of this equation is about 30%:
ƒs
+V
V out
in
(V
in
(V in
ESR
* Vout)
(10
* (10 10* ) Td)ńCout)
10 * ) Td) ) 0.0097 L out * ESL
7
(ESR
7
V )
in
Where fs is the switching frequency (Hz); Vout is the output voltage (V); Vin is the input voltage (V); Cout is the
output capacitance; ESR is the equivalent series resistance in the output capacitor (Ω); ESL is the equivalent
series inductance in the output capacitor (H); Lout is the output inductance (H); Td is output feedback RC filter
time constant (S).
In the EVM module design, for the 1.8 V output, for example: Vin = 5 V, Vout = 1.8 V, Cout = 680 µF; ESR =
40 mΩ; ESL = 3 nH; Lout = 6 µH; Td = 0.5 µs.
Then, the frequency fs = 122 kHz.
output inductor ripple current
The output inductor current ripple can affect not only the efficiency and the inductor saturation, but also the
output voltage capacitor selection. The equation is exhibited as below:
Iripple
( Rdson ) RL )
+ Vin * Vout * Iout
Lout
D
Ts
Where Iripple is the peak-to-peak ripple current (A) through inductor; Vin is the input voltage (V); Vout is
the output voltage (V); Iout is the output current; Rdson is the on-time resistance of MOSFET (Ω); D is the duty
cycle; and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted
by changing the output inductor value.
Example: Vin = 5 V; Vout = 1.8 V; Iout = 5 A; Rdson = 10 mΩ; RL = 5 mΩ; D = 0.36; Ts = 10 µS; Lout = 6 µH
Then, the ripple Iripple = 2 A.
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to the ground, the RMS current
in the output capacitor can be calculated as:
I o(rms)
+ ǸD12I
Where I(orms) is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple
current (A).
Example: ∆I = 2 A, so Io(rms) = 0.58 A
22
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
input capacitor RMS current
Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in
the input capacitor can be calculated as:
I (rms)
i
+
Ǹ
I o2
D
(1
* D) ) 121
D
Iripple 2
Where Ii(rms) is the input RMS current in the input capacitor (A); Io is the output current (A); D is the duty cycle.
From the equation, it can be seen that the highest input RMS current usually occurs at the lowest input voltage,
so it is the worst case design for input capacitor ripple current.
Example: Io = 5 A; D = 0.36
Then, Ii(rms)= 3.36 A
softstart
The softstart timing can be adjusted by selecting the soft-start capacitor value. The equation is
C
soft
+2
T
soft
Where Csoft is the softstart capacitance (µF); Tsoft is the start-up time on softstart terminal (S).
Example: Tsoft = 5 mS, so Csoft = 0.01 µF.
current protection
The current protection in TPS5103 is set using an internal current source and an external resistor to set up the
current limit. The sensed high side MOSFET drain-to-source voltage drop is compared to the set point, if the
voltage drop exceeds the limit, the internal oscillator is activated, and it continuously resets the current limit until
the over-current condition is removed. The equation below should be used for calculating the external resistor
value for current protection:
)
ń
)
ń
PWM or HYS mode
Rcl
+ Rds(on)
(Itrip Iind(p-p) 2)
0.000015
SKIP mode
Rcl
+ Rds(on)
(Itrip Iind(p-p) 2)
0.000005
Where Rcl is the external current limit resistor (R10,R11); Rds(on) is the high side MOSFET on-time resistance.
Itrip is the required current limit; Iind(p-p) is the peak-to-peak output inductor current.
Example: PWM mode or HYS mode
Rds(on) = 10 mΩ, Itrip =5 A, Iind = 2 A, so Rcl = 4 kΩ
Example: SKIP mode
Rds(on) = 10 mΩ, Itrip = 2 A, Iind = 1 A, so Rcl = 5 kΩ
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
loop gain compensation
Voltage mode control is used in this controller for the output voltage regulation. To achieve fast, stabilized
control, two parts are discussed in this section: the power stage small signal modeling and the compensation
circuit design.
For the buck converter, the small signal modeling circuit is shown below:
a
ZL
∧
d
Vap
D
ia
VO
C
∧
Ic d
VI
L
ic
D
1
+
RL
c
+
–
R
ZRC
RC
p
From this equivalent circuit, several control transfer functions can be derived: input-to-output, output
impedance, and control-to-output. Typically the control-to-output transfer function is used for the feedback
control design.
Assuming Rc and RL are much smaller than R, the simplified small signal control-to-output transfer function is:
∧
Vod
∧
d
+
1
) sCRc)
Rc ) R ) L ) s 2LC
L
R
ƪ ǒ
)s C
(1
Ǔ ƫ
Where C is the output capacitance; Rc is the equivalent serial resistance (ESR) in the output capacitor; L is the
output inductor; RL is the equivalent serial resistance (ESR) in the output inductor; R is the load resistance.
To achieve the fast transient response and the better output voltage regulation, a compensation circuit is added
to improve the feedback control. The whole system is shown below:
Vref
Power
Stage
PWM
Compensation
24
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
The typical compensation circuit used as an option in the EVM design is a part of the output feedback circuit.
The circuitry is displayed below.
R1
R2
R4
C3
C1
_
R3
Vref
C2
To PWM
+
This circuit is composed of one integrator, two poles, and two zeros:
Assuming R1 << R2 and C2 << C3, the equation is:
Comp
(1 ) sC3R4) (1 ) sC2R2)
+ sC3R2(1
) sC2R4)(1 ) sC1R1)
Therefore,
1
+ 2pC1R1
1
Zero2 +
2pC3R4
1
Integrator +
2pƒC3R2
Pole1
1
+ 2pC2R4
1
Zero1 +
2pC2R2
Pole2
A simplified version used in the EVM design is exhibited below.
Vo
R2
R4
_
R3
Vref
C3
C2
+
Assuming C2 << C3, the equation is:
Comp
(1 ) sC3R4)
+ sC3R2(1
) sC2R4)
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
there is one pole, one zero and one integrator:
Zero
1
+ 2pC3R4
Pole
1
+ 2pC2R4
Integrator
1
+ 2pƒC3R2
The loop-gain concept is used to design a stable and fast feedback control. The loop-gain equation is derived
by that the control-to-output transfer function times the compensation:
Loop
* gain + Vod X
Comp
By using a bode plot, the amplitude and the phase of this equation can be drawn with software such as MathCad.
In turn, the stability can be easily designed by adjusting the compensation perimeters. The sample bode plot
is shown below to explain the phase margin, gain margin and the crossover frequency.
The gain is drawn as 20 log (loop-gain), and the phase is in degrees. To explain them clearer, 180 degrees is
added to the phase, so that the gain and phase share the same zero.
Where the gain curve touches the zero is the crossover frequency. The higher this frequency is, the faster the
transient response is, since the transient recovery time is 1/(crossover frequency). The phase to the zero is the
phase margin at the crossover frequency. The phase margin should be at least 60 degrees to cover all the
condition changes such as temperature. The gain margin is the gap between gain curve and the zero when the
phase curve touches the zero. This margin should be at least 20 dB to guarantee the stability over all conditions.
180
166
152
138
124
110
96
82
68
20 Log (Loop-Gain) 54
180 + Phase 40
26
12
–2
–16
–30
–44
–58
–72
–86
–100
10
Phase
Phase
Margin
Gain
Gain
Margin
Crossover
100
103
104
f – Frequency – Hz
26
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105
106
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
synchronization
Some applications require switching clock synchronization. Two methods are used for synchronization:
D
Triangle wave synchronization
740 mV
Ct
TPS5103
740 mV
Rt
D
Square wave synchronization
It can be seen that RT and CT are removed from the circuit. Therefore, two components are saved. This method
is good for the synchronization between two controllers. If the controller needs to be synchronized with digital
circuit such as DSP, usually the square-type clock signal is used. The configuration exhibited below is for this
type of application:
Ct
TPS5103
Rt
An external resistor is added into the circuit, but RT is still removed. CT is kept to be a part of RC circuit generating
triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the
capacitor can be adjusted to achieve the correct peak–to–peak value and the offset value.
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, place the low-level components. Below are several specific points to
consider before layout of a TPS5103 design begins.
D
D
All sensitive analog components should be referenced to ANAGND. These include components connected
to Vref5, Vref, INV, LH, and COMP .
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on VO, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
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TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
D
D
D
D
D
D
D
D
D
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
The bypass capacitor for VCC should be placed close to the TPS5103.
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS5103.
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.
The bulk storage capacitors across VIN should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
High-frequency bypass capacitors should be placed across the bulk storage capacitors on VO.
LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces. Ceramic decoupling capacitors should be placed close to where VCC connects to Vin, to reduce
high-frequency noise coupling on VCC.
The output voltage sensing trace should be isolated by either ground trace or VCC trace.
test results
The tests are conducted at TA = 25°C, the point voltage is 5 V.
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
95
95
1.8 V Output Efficiency
1.8 V Output Efficiency
90
90
PWM Mode
85
Efficiency – %
Efficiency – %
85
80
75
PWM Mode
80
75
SKIP Mode
SKIP Mode
70
70
65
65
60
60
0
0.5
3.5
1
1.5
2
2.5
3
IO – Output Current – A
0
4
0.1
Figure 37
0.4
0.2
0.3
IO – Output Current – A
0.5
Figure 38
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.790
1.790
1.8 V Line Regulation
1.8 V Output Load Regulation
1.785
VO – Output Voltage – V
VO – Output Voltage – V
1.790
1.780
1.780
1.780
1.770
1.775
1.770
1.770
1.760
0
5
10
15
VI – Input Voltage – V
20
25
0
0.5
Figure 39
1
1.5
2
2.5
3
IO – Output Current – A
3.5
4
Figure 40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT/VOLTAGE
OUTPUT
VOLTAGE
95
1.8 V Output Diode Type Efficiency
90
Efficiency – %
85
80
75
70
65
60
0
0.5
1
1.5
2
2.5
3
IO – Output Current – A
3.5
4
Figure 41
Figure 42
TRANSIENT RESPONSE (OVERSHOOT)
TRANSIENT RESPONSE (UNDERSHOOT)
Figure 43
30
Figure 44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
Table 1. Bill of Materials (see Note 3)
REF
C1opt
C1
C2
C3
C4†
C5
C6
C7
C8
C9
C10
C11†
MFG
Sanyo
ELNA
Taiyo Yuden
Sanyo
std
MBRS340T3
MBRS130LT3
SD103-AWDICT-ND
DO3316P-682
CA26DA-D36W-0FC
S1132-2-ND
DESCRIPTION
Capacitor, POSCAP, 220 µF, 10 V
Capacitor, electrolytic, 220 µF, 35 V
Capacitor, ceramic, 10 µF, 35 V
Capacitor, POSCAP, 470 µF, 4 V
Open, capacitor, Ceramic, 2.2 µF, 16 V
Capacitor, ceramic, 1 µF, 16 V
Capacitor, ceramic, 0.01 µF, 16 V
Capacitor, ceramic, 220 pF, 16 V
Capacitor, ceramic, 100 pF, 16 V
Capacitor, ceramic, 1 µF, 16 V
Capacitor, ceramic, 2.2 µF, 35 V
Open
Capacitor, Ceramic, 2.2 µF, 35 V
Capacitor, Ceramic, 10 µF, 35 V
Open
Open
Open, capacitor, ceramic, 1000 pF, 16 V
Diode, Schottky, 40 V, 3 A
Diode, Schottky, 30 V, 1 A
Diode, Schottky, 40 V, 200 mA, 400 mW
Inductor, 6.8 uH, 4.4 A
Edge connector, surface-mount, 0.040” board, 0.090” standoff
Header, straight, 2–pin, 0.1 ctrs, 0.3” pins
JP1 Shunt
929950-00-ND
Shunt, jumper, 0.1”
3M
DigiKey
#929950-00-ND
JP2
S1132-2-ND
Header, straight, 2–pin, 0.1 ctrs, 0.3” pins
Sullins
DigiKey
#S1132-2-ND
C12
C13
C14
C14†opt
C15†
D1
D1opt
D2
L1
J1–J14
JP1
PN
10TPB220M
RV-35V221MH10-R
GMK325F106ZH
4TPB470M
std
std
std
std
std
std
GMK316F225ZG
std
GMK316F225ZG
GMK325F106ZH
std
Resistor, 5.1 kΩ, 5 %
std
Open, resistor, 1 kΩ, 5%
std
Resistor, 910 Ω, 1%
std
Resistor, 1.74 kΩ, 1%
std
Resistor, 5.1 kΩ, 5%
std
Resistor, 82 kΩ, 5%
std
Open, 0 Ω, 5%
R7
std
Resistor, 1 kΩ, 5%
R9
std
Resistor, 1 kΩ, 5%
R10
std
Resistor, 1 kΩ, 5%
R11
std
Resistor, 10 Ω, 5%
R12
std
Resistor, 51 kΩ, 5%
R13†
std
Open
Q1
Si4410DY
Transistor, MOSFET, n-ch, 30-V, 10-A, 13–mΩ
Q2
Si4410DY
Transistor, MOSFET, n-ch, 30-V, 10-A, 13-mΩ
U1
TPS5103
IC, controller
† Components for optional mode test only.
NOTE 3: This operation mode is PWM mode only.
Taiyo Yuden
Taiyo Yuden
Taiyo Yuden
Motorola
Motorola
Digikey
Coilcraft
NAS Interplex
Sullins
R1
R2†
R3
R4
R5
R6A
R6B†
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Siliconix
Siliconix
TI
SIZE
7.3x4.3mm
10x10mm
1210
7.3x4.3mm
805
805
805
805
805
805
1206
805
1206
1210
10x10mm
805
SMC
SMB
3.5x1.5mm
0.5x0.37 in
0.040”
DigiKey #
S1132-2-ND
805
805
805
805
805
805
805
805
805
805
805
805
805
SO–8
SO–8
SSOP–20
31
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
Top Layer
.
Bottom Layer (Top View)
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
Top Assembly
–
Power Supply
Load
0–4A
+
5–V, 5–A Supply
–
NOTE: All wire pairs should be twisted.
+
Test Setup
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
Table 2. Test Specifications
PARAMETER
CONDITIONS
MIN
Input voltage range
TYP
5
Output voltage range
Vi = 5 – 25 V Io = 0 – 4 A
Output current range
Vi = 5 – 10 V
Output current limit
Vi = 5 V
Output ripple
Vi =5 V,
Operating frequency
Io = 4 A
Efficiency
Vi = 5 V,
1.7
1.8
MAX
25
V
1.9
V
4
A
0
4.3
A
Io = 4 A
150
Vo = 1.8 V,
Io = 4 A
UNITS
50
mVp–p
250
KHz
90
%
Table 3. EVM Operating Specifications
SKIP MODE
Remove JP1 shunt
HYS MODE
Remove R5, C6 and C7
Remove R6A
Add R6B
Add C15
If it needs the loop-compensation, add R2 and C4
This EVM is designed to cover as many applications as possible. For some more specific applications, the circuit
can be simpler. The table below gives some recommendations.
Table 4. EVM Application Recommendations
5-V INPUT VOLTAGE
Change C1 to low profile capacitor
Sanyo 10TPB220M (220 µF, 10 V)
Or 6TPB330M (330 µF, 6.3 V)
Remove R10
<3-A OUTPUT CURRENT
Change Q1 and Q2 to dual pack MOSFET,
IRF7311 to reduce the cost.
DIODE VERSION
Remove Q2 to reduce the cost.
Table 5. Vendor and Source Information
MATERIAL
MOSFETS (Q1–Q2)
(Q1 Q2)
INPUT CAPACITORS (C1)
MAIN DIODES (D1)
INDUCTORS (L1)
SOURCE
In EVM design
Second source
In EVM design
Second source
In EVM design
Second source
In EVM design
Second source
CERAMIC CAPACITORS
(C2, C14) (C12, C10)
PART NUMBER
Si4410
IRF7811 (International Rectifier)
RV–35V221MH10–R (ELNA)
35CV330AX/GX (Sanyo)
UUR1V221MNR1GS (Nichicon)
MBRS340T3 (Motorola)
U3FWJ44N (Toshiba)
DO3316P–682 (Coilcraft)
CTDO3316P–682
(Inductor Warehouse)
GMK325F106ZH
GMK316F225ZG
(Taiyo Yuden)
IN EVM design
Taiyo Yuden representative
34
POST OFFICE BOX 655303
DISTRIBUTORS
Local distributor
Bell Microproducts 972–783–4191
870–633–5030
Future Electronics (Local Office)
Local distributors
Local distributors
972–458–2645
800–533–8295
SMEC
512–331–1877
e–mail: [email protected]
• DALLAS, TEXAS 75265
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
APPLICATION INFORMATION
High current applications are described in Table 6. The values are recommendations based on actual test
circuits. Many variations are possible based on the requirements of the user. Performance of the circuit is
dependent upon the layout rather than on the specific components, if the device parameters are not exceeded.
The power stage, having the highest current levels and greatest dv/dt rates, should be given the most attention,
as both the supply and load can be severely affected by the power levels and edge rates.
Table 6. High Current Applications
REFERENCE
DESIGNATIONS
FUNCTION
8-A OUTPUT
2x ELNA
RV-35V221MH10-R
220 µF, 35 V
2x Taiyo Yuden
GMK325F106ZH
10 µF, 35 V
12-A OUTPUT
3x ELNA
RV-35V221MH10-R
220 µF, 35 V
3x Taiyo Yuden
GMK325F106ZH
10 µF, 35 V
Coiltronics UP4B-1R5
1.5 µΗ, 13.4 A
16-A OUTPUT
4x ELNA
RV-35V221MH10-R
220 µF, 35 V
4x Taiyo Yuden
GMK325F106ZH
10 µF, 35 V
MicorMetals T68-8/90
Core w/7T, #16
1.0 µΗ, 25 A
C1
Input bulk capacitor
C2
Input bypass capacitor
L1
Output filter indicator
Coiltronics UP3B-2R2
2.2 µΗ, 9.2 A
C3
Output filter capacitor
2x Sanyo 4TPB470M
470 µF, 4 V
Q1
Power switch
2x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
3x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
4x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
Q2
Power switch
2x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
3x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
4x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
7Ω
10 kΩ
200 kHz
5Ω
15 kΩ
150 kHz
4Ω
20 kΩ
100 kHz
R11
R12
Switching frequency
Gate drive resistor
Current limit resistor
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3x Sanyo 4TPB470M
470 µF, 4 V
• DALLAS, TEXAS 75265
4x Sanyo 4TPB470M
470 µF, 4 V
35
TPS5103
MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER
SLVS240 – SEPTEMBER 1999
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°– 8°
1,03
0,63
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
A MAX
3,30
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
2,70
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 / C 10/95
NOTES: A.
B.
C.
D.
36
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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