HT1608L 2×20 Channel LCD Driver Features • • • • • Operating voltage: 2.7V~5.2V LCD driving voltage: 3.0V~5.0V 40 internal LCD drivers available Bias voltage: static to 1/5 bias • LCD driver with serial/parallel conversion function Common or segment driver output by selection Applications • • • • Electronic dictionaries Portable computers Remote controllers Calculators General Description from an LCD controller into parallel data and send out LCD driving waveforms to the LCD panel. The HT1608L is designed for general purpose LCD drivers. It can drive both static and dynamic drive LCDs. The chip can be applied to a common driver or a segment driver. The HT1608L is an LCD driver LSI with 40 output channels using CMOS technology. It is equipped with two sets of 20-bit bidirectional shift registers, 20-bit data latches, 20-bit LCD drivers, and logic control circuits. The HT1608 can convert serial data received Block Diagram 1 27th Aug ’98 HT1608L Pin Assignment 2 27th Aug ’98 HT1608L Pad Assignment Chip size: 101 × 115 (mil)2 * The IC substrate should be connected to VDD in the PCB layout artwork. 3 27th Aug ’98 HT1608L Pad Coordinates Unit: mil Pad No. X Y Pad No. X Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –44.54 –36.55 –29.92 –23.29 –16.66 –10.03 –3.40 3.23 9.86 16.49 23.12 29.75 36.38 51.94 45.86 39.78 33.70 27.63 21.55 15.47 9.39 3.32 –2.76 –8.84 –14.92 –21.00 –27.07 –33.15 –39.23 –45.31 –51.38 –51.38 –51.38 –51.38 –51.38 –51.38 –51.38 –51.38 –51.38 –51.38 –51.38 –51.38 –51.38 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 44.12 44.12 44.12 42.33 44.12 44.12 44.12 44.12 44.12 44.12 44.12 44.12 44.12 44.12 44.12 44.12 44.12 44.12 31.28 24.74 18.19 11.65 5.10 –1.45 –7.99 –14.53 –21.08 –27.63 –34.17 –51.38 –42.97 –36.93 –29.62 –22.31 –16.28 –10.67 –4.63 0.98 7.01 12.62 18.66 24.31 29.83 35.36 40.88 46.41 51.94 51.94 51.94 51.94 51.94 51.94 51.94 51.94 51.94 51.94 51.94 51.94 Pad Description Pad No. Pad Name I/O 1~9 Y28~Y20 10~23 Y19~Y6 O LCD driver outputs for channel 1 24 VDD — Power supply ( positive ) 25~30 Y5~Y0 O LCD driver outputs for channel 1 31 VEE I LCD power supply 32 CLK1 I Latch signal for channel 1 on the falling edge CLK1 is used for channel 2 when MODE is set to VSS (Note 1 ) O Description LCD driver outputs for channel 2 4 27th Aug ’98 HT1608L Pad No. Pad Name I/O Description 33 CLK2 I Shift signal for channel 1 on the falling edge and used for channel 2 when MODE is set to VSS (Note 1) 34 VSS — Power supply (ground) 35 DL1 I/O Data input/output of channel 1 shift register 36 DR1 I/O Data input/output of channel 1 shift register 37 DL2 I/O Data input/output of channel 2 shift register 38 DR2 I/O Data input/output of channel 2 shift register 39 ALT I Alternate signal input for LCD driving waveform 40 SHF1 I Shift direction selection of channel 1 shift register (Note 2) 41 SHF2 I Shift direction selection of channel 2 shift register (Note 2) 42 MODE I Mode select signal of channel 2 (Note 3) 43, 44 V1, V2 I LCD bias supply voltage for channels 1 and 2 45, 46 V3, V4 I LCD bias supply voltage for channel 1 47, 48 V5, V6 I LCD bias supply voltage for channel 2 49~59 Y39~Y29 O LCD driver outputs for channel 2 Note 1: Data is processed on the clock falling or rising edge as shown in the following table. MODE= L (VSS) MODE= H (VDD) 5 27th Aug ’98 HT1608L Note 2 : Shift direction of channel 1 and 2 Shift Direction of Channel 1 (Channel 2) SHF1 (SHF2) DL1 (DL2) DR1 (DR2) H OUT IN L IN OUT Note 3 : The output levels of channel 1 and 2 are decided by the combination of MODE, ALT and latched data. Refer to the following table: MODE Latched Data H H (VDD) L H L (VSS) L ALT Channel 1 (Y0~Y19) Channel 2 (Y20~Y39) H V1 V2 L V2 V1 H V3 V6 L V4 V5 H V1 V1 L V2 V2 H V3 V5 L V4 V6 6 27th Aug ’98 HT1608L Absolute Maximum Ratings* Supply Voltage ..............................–0.3V to 5.5V Storage Temperature................. –50°C to 125°C Input Voltage................. VSS–0.3V to VDD+0.3V Operating Temperature............... –20°C to 70°C *Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Ta=25°C D.C. Characteristics Symbol Parameter Test Conditions VDD Conditions — Min. Typ. Max. Unit 2.7 — 5.2 V — 100 300 µA VDD Operating Voltage — IDD Operating Current 5V ISTB Standby Current 5V — — 1 5 µA fCLK2 Data Shift Frequency 5V — — — 400 kHz twCLK Clock Pulse Width 5V — 800 — — ns VIL “L” Input Voltage 5V — — — 1 V VIH “H” Input Voltage 5V — 4 — — V VOL “L” Output Voltage 5V IOL=+0.4mA — — 0.4 V VOH “H” Output Voltage 5V IOH=–0.4mA 4.6 — — V VLCD LCD Driving Voltage — VDD–VEE 3 — 5.0 V No load 7 27th Aug ’98 HT1608L Functional Description Both channel 1 and 2 used as segment drivers (MODE=L) When both channel 1 and 2 of the HT1608L are used as segment drivers, they will shift data on the falling edge of CLK2 and shift latch data on the falling edge of CLK1. V3 and V5 or V4 and V6 are shortened in the application circuit as shown in the following figure. Both channel 1 and 2 used as common drivers (MODE=L) When both channel 1 and 2 of the HT1608L are used as common drivers, the MODE is set low and the signals (CLK1, CLK2, FRAME) from the controller are connected as shown in the following figure. 8 27th Aug ’98 HT1608L Channel 1 used as a segment driver and channel 2 as a common driver (MODE=H) When channel 2 is used as a common driver, MODE is connected to VDD. Channel 2 will shift data on the rising edge of CLK1 and shift latch data on the rising edge of CLK2. Static driver When the HT1608L is used as a static driver, data is transferred on the falling edge of CLK2 and latched on the falling edge of CLK1. The frequency of CLK1 becomes the frame frequency of the LCD driver. The frequency of ALT has to be twice the frequency of CLK1. ALT has to be synchronized on the falling edge of CLK1. The power supply for the LCD driver is used by shortening V1, V4 and V6 or V2, V3 and V5. One of the LCD output terminals can be used as a common output. The application circuit connections are shown below: 9 27th Aug ’98 HT1608L Timing Diagrams Segment data waveform (1/8 duty) 10 27th Aug ’98 HT1608L Common data waveform (a typical waveform of channel 2 as a COMMON driver, 1/8 duty) 11 27th Aug ’98 HT1608L Application Circuits 12 27th Aug ’98