HOLTEK HTG1390

HTG1390
4-bit Microcontroller
Preliminary
Features
•
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•
•
•
•
•
•
•
•
•
•
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•
Operating voltage: 1.2V~1.8V
7 input lines
3 output lines
Halt feature reduces power consumption
Up to 16µs instruction cycle with 256kHz
system clock at VDD=1.5V
All instructions in 1 or 2 machine cycles
4K×8 program ROM
Data memory RAM size 128×4 bits
27×3 segment LCD driver
8-bit table read instruction
5 working registers
Internal timer overflow interrupt
One level subroutine nesting
RC oscillator for system clock
8-bit timer with internal clock source
Sound effect circuit
General Description
tiple LCD low power applications among which
are calculators, scales, and hand held LCD
products.
The HTG1390 is the processor from Holtek’s
4-bit stand alone single chip microcontroller
range specifically designed for LCD product applications. The device is ideally suited for mul-
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17th Nov ’98
Preliminary
HTG1390
Block Diagram
Notes: ACC: Accumulator
PA: Output port
PC: Program counter
PS,PP: Input ports
R0~R4: Working registers
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17th Nov ’98
Preliminary
HTG1390
Pad Assignment
Chip size: 1960 × 2300 (µm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
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17th Nov ’98
Preliminary
HTG1390
Unit: µm
Pad Coordinates
Pad No.
X
Y
Pad No.
X
Y
1
2
3*
4*
5
6
7
8
9*
10*
11
12
13
14
15
16
17
18
19*
20*
21*
22*
23
24
25
26
–843.74
–843.74
–843.74
–843.74
–843.74
–843.74
–843.74
–843.74
–843.74
–843.74
–843.74
–843.74
–843.74
–798.04
–668.04
–415.94
–287.94
–154.74
–25.94
107.26
236.26
398.66
518.66
638.66
853.56
853.56
866.29
674.39
554.39
434.39
314.39
194.39
74.39
–45.61
–165.61
–285.61
–405.61
–525.61
–645.61
–856.71
–882.11
–809.01
–853.41
–853.41
–853.41
–853.41
–853.41
–940.91
–940.91
–940.91
–884.11
–764.11
27*
28*
29*
30*
31*
32*
33
34*
35*
36*
37*
38*
39*
40*
41*
42*
43*
44*
45*
46*
47*
48*
49*
50*
51*
52*
853.56
853.56
853.56
853.56
853.56
853.56
853.56
853.56
853.56
853.56
853.56
853.56
838.76
718.76
598.76
478.76
358.76
238.76
118.76
–1.24
–121.24
–241.24
–361.24
–481.24
–601.24
–721.24
–644.11
–524.11
–404.11
–284.11
–164.11
–44.11
75.89
195.89
315.89
435.89
555.89
675.89
935.39
935.39
935.39
935.39
935.39
935.39
935.39
935.39
935.39
935.39
935.39
935.39
935.39
935.39
∗ These pins must be bonded out for functional testing.
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17th Nov ’98
Preliminary
HTG1390
Pad Description
Pad No.
Pad Name
I/O Mask Option
Note 1
Function
17, 18
BZ,BZ
O
Sound effect outputs
8
9
TEST1
TEST2
I
I
—
5~7
COM2~COM0
O
Note 2
10~13
PS3~PS0
I
16
VSS
I
—
Negative power supply, GND
15
14
OSCI
OSCO
I
O
—
OSCI,OSCO are connected to an external resistor
for an internal system clock
19~21
PA2~PA0
O
CMOS or
NMOS Open
Drain
22~24
PP0~PP2
I
Pull-high or
3-bit port for input only
None. Note 2
25
RES
I
—
Input to reset an internal LSI
Reset is active on logical low level
26~52
SEG0~SEG26
O
—
LCD driver outputs for LCD panel segment
1
VDD
I
—
Positive power supply
4
V3
I
—
LCD system power 1/2 bias generated
2, 3
C1, C2
I
—
LCD system voltage booster condensor connecting
terminal
For test mode only
TEST1 and TEST2 are left open when the
HTG1390 is in normal operation (with an internal
pull high resistor).
Output for LCD panel common plate
Pull-high or
4-bit port for input only
None. Note 3
3-bit latch port for output only
Notes: The system clock provides 6 different sources selectable by mask option to drive the sound
effect clock. If the Holtek sound library is used only 128K and 64K are acceptable.
Each bit of ports PS and PP can be a trigger source of the HALT interrupt, selectable by mask
option.
Absolute Maximum Ratings*
Supply Voltage ................................. –0.3V~5.5V
Input Voltage.....................VSS–0.3V~VDD+0.3V
Storage Temperature.................... –50°C~125°C
Operating Temperature...................... 0°C~70°C
*Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this
device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
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17th Nov ’98
Preliminary
HTG1390
Ta=25°C
D.C. Characteristics
Symbol
Test Conditions
Parameter
VDD
Conditions
—
VDD
Operating Voltage
—
IDD
Operating Current
1.5V
ISTB
Standby Current
VIL
Min. Typ.
Max. Unit
1.2
1.5
1.8
V
No load,
fSYS=256kHz
—
20
—
µA
1.5V
No load,
HALT mode
—
—
1
µA
Input Low Voltage
1.5V
—
0
—
0.4
V
VIH
Input High Voltage
1.5V
—
1.0
—
1.5
V
IOL1
Port A, BZ & BZ Output Sink
V =1.5V,
1.5V DD
Current
VOL=0.15V
95
100
—
µA
IOH1
Port A, BZ & BZ Output
Source Current
1.5V
600
700
—
µA
IOL2
Segment Output Sink
Current
1.5V VLCD=3V, VOL=0.3V
100
150
—
µA
IOH2
Segment Output Source
Current
1.5V VLCD=3V, VOH=2.7V
–20
–40
—
µA
RPH
Pull–high Resistance
1.5V PS, PP, RES
30
—
300
kΩ
VDD=1.5V,
VOH=1.35V
Ta=25°C
A.C. Characteristics
Symbol
Parameter
Test Conditions
VDD
Min.
Typ.
Max.
Unit
Conditions
fSYS
System Clock
1.5V R:36kΩ~2MΩ
38
—
400
kHz
fLCD
LCD Clock
1.5V
—
128*
—
Hz
tCOM
LCD Common Period
—
1/3 duty
—
(1/fLCD)×3
—
s
tCY
Cycle Time
—
fSYS=256kHz
—
16
—
µs
tRES
Reset Pulse Width
—
—
5
—
—
ms
fSOUND
Sound Effect Clock
—
—
—
64 or 128
**
—
kHz
—
Notes: * In general, fLCD is selected and optimized by Holtek depending upon fSYS and the operating
voltage.
** Only these two clocking signal frequencies are supported by the Holtek sound library.
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17th Nov ’98
Preliminary
HTG1390
System Architecture
Program counter – PC
This counter addresses the program ROM and
is arranged as an 12-bit binary counter from
PC0 to PC11 whose contents specify a maximum of 4096 addresses. The program counter
counts with an increment of 1 or 2 with each
execution of an instruction.
When executing the jump instruction (JMP,
JNZ, JC, JTMR,...), a subroutine call, initial
reset, internal interrupt, external interrupt or
returning from a subroutine, the program
counter is loaded with the corresponding instruction data as shown in the table.
Program memory
• Location 8
Activating the PS or PP input pins of the
processor with the interrupts enabled during
Halt mode causes the program to jump to this
location.
Notes: P0~P11: Instruction code
@: PC11 keeps current value
S0~S11: Stack register bits
• Locations n00H to nFFH
Program memory – ROM
These are the 256 bytes of each page in program memory. This area from n00H to nFFH
and F00H to FFFH can be used as a look–up
table. Instructions such as READ R4A, READ
MR0A, READF R4A, READF MR0A can read
the table and transfer the contents of the
table to ACC and R4 or to ACC and a data
memory address specified by the register pair
R1,R0. However as R1,R0 can only store 8
bits, these instructions cannot fully specify
the full 12 bit program memory address. For
this reason a jump instruction should be first
used to place the program counter in the right
page. The above instructions can then be used
to read the look up table data.
The program memory is the executable memory
and is arranged in a 4096×8 bit format. The
address is specified by the program counter
(PC). Four special locations are reserved as described as follows.
• Location 0
Activating the processor RES pin causes the
first instruction to be fetched from location 0.
• Location 4
Contains the timer interrupt resulting from a
TIMER overflow. If the interrupts are enabled it
causes the program to jump to this subroutine.
Mode
Program Counter
PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
Internal interrupt
0
0
0
0
0
0
0
0
0
1
0
0
External interrupt
0
0
0
0
0
0
0
0
1
0
0
0
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
@
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Jump, call instruction
Conditional branch
Return from subroutine
Program memory
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17th Nov ’98
Preliminary
HTG1390
The program memory mapping is shown in the
diagram.
There are two areas in the data memory, the
temporary data area and the display data area.
Access to the temporary data area is from 00H
to 7FH. Locations E0H to FAH represent the
display data area. The locations between the
temporary and display data areas are undefined and cannot be used.
In the execution of an instruction the program
counter is added before the execution phase, so
careful manipulation of READ MR0A and
READ R4A is needed in the page margin.
When data is written into the display data area
it is automatically read by the LCD driver
which then generates the corresponding LCD
driving signals.
Note that the page number n must be greater
than zero as some locations in page 0 are reserved for specific usage as mentioned. This
area may function as normal program memory
as required.
Stack register
The stack register is a group of registers used to
save the contents of the program counter (PC)
and is arranged in 13 bits×1 level. One bit is
used to store the carry flag. An interrupt will
force the contents of the PC and the carry flag
onto the stack register. A subroutine call will
also cause the PC contents to be pushed onto
the stack; however the carry flag will not be
stored. At the end of a subroutine or an interrupt (indicated by a return instruction RET or
RETI), the contents of the stack register are
returned to the PC.
Data memory
Accumulator – ACC
The accumulator is the most important data
register in the processor. It is one of the sources
of input to the ALU and the destination of the
results of the operations performed in the ALU.
Data to and from the I/O ports and memory also
passes through the accumulator.
Executing “RETI” instruction will restore the
carry flag from stack register, but “RET” doesn’t.
Working registers – R0,R1,R2,R3,R4
There are 5 working registers (R0,R1,R2,R3,
R4) usually used to store the frequently accessed intermediate results. Using the instructions INC Rn and DEC Rn the working
registers can increment (+1) or decrement (–1).
The JNZ Rn (n=0,1,4) instruction makes efficient use of the working registers as a program
loop counter. Also the register pairs R0,R1 and
R2,R3 are used as a data memory pointer when
the memory transfer instruction is executed.
Arithmetic and logic unit – ALU
This circuit performs the following arithmetic
and logical operations ...
• Add with or without carry
• Subtract with or without carry
• AND, OR, Exclusive-OR
• Rotate right, left through carry
• BCD decimal adjust for addition
Data memory – RAM
• Increment, decrement
• Data transfers
The static data memory (RAM) is arranged in
256×4 bit format and is used to store data. All of
the data memory locations are indirectly addressable through the register pair R1,R0 or
R3,R2; for example MOV A,[R3R2] or MOV
[R3R2],A.
• Branch decisions
The ALU not only outputs the results of data
operations, but also sets the status of the carry
flag (CF) in some instructions.
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17th Nov ’98
Preliminary
Likewise when the timer flag is set in the enable interrupt mode and the program is not
within a CALL subroutine the internal interrupt is activated. This causes a subroutine call
to location 4 and resets the timer flag.
Timer
The HTG1390 contains a programmable 8-bit countup counter which can be used as a clock to generate
an accurate time base.
The Timer may be set and read with software
instructions and stopped by a hardware reset or
a TIMER OFF instruction. To restart the timer
load the counter with the value XXH and then
issue a TIMER ON instruction. Note that XX is
the desired start count immediate value of the
8 bits. Once the Timer/Counter is started it
increments to a maximum count of FFH and
then overflows to zero (00H). It then continues
to count until stopped by a TIMER OFF instruction or a reset.
When running under a CALL subroutine or DI
the interrupt acknowledge is on hold until the
RET or EI instruction is invoked. The CALL
instruction should not be used within an interrupt routine as unpredictable behaviour may
occur. If within a CALL subroutine internal
interrupt occur, the internal interrupt will be
serviced after leaving the CALL subroutine.
The interrupts are disabled by a hardware reset
or a DI instruction. They remain disabled until
the EI instruction is executed.
The increment from the maximum count of
FFH to a zero (00H) triggers a timer flag TF and
an internal interrupt request. The interrupt
may be enabled or disabled by executing the EI
and DI instruction. If the interrupt is enabled
the timer overflow will cause a subroutine call
to location 4. The state of the timer flag is also
testable with the conditional jump instruction
JTMR. The timer flag is cleared after the interrupt or the JTMR instruction is executed.
Each input port pin can be programmed by
mask option to have an external interrupt function in the HALT mode.
Initial reset
The HTG1390 provides an RES pin for system
initialization. This pin is equipped with an internal pull high resistor and in combination
with an external 0.1µ~1µF capacitor, provides
an internal reset pulse of sufficient length to
guarantee a reset to all internal circuits. If the
reset pulse is generated externally, the RES pin
must be held low for at least 5ms. Normal circuit operation will not commence until the RES
pin returns high.
If an internal source is used the frequency is
determined by the system clock and the parameter n as defined in the equation. The frequency of the internal frequency source can be
selected by mask option.
Frequency of TIMER clock =
HTG1390
system clock
The reset performs the following functions:
2n
where n=0,1,2 ...13 selectable by mask option.
PC
Note that n cannot have the value of 6, which is
reserved for internal use.
TIMER
Stop
Time flag
Reset (Low)
SOUND
Sound off and one sing
mode
Output Port A
high (or floating state)
Interrupt
Disabled
BZ and BZ output
Low level
Interrupt
The HTG1390 provides both internal and external interrupt modes. The DI and EI instructions are used to disable and enable the
interrupts. During Halt mode, if the PP or PS
input pin is triggered on a high to low transition
in the enable interrupt mode and the program
is not within a CALL subroutine, the external
interrupt is actived. This causes a subroutine
call to location 8 and resets the interrupt latch.
9
000H
17th Nov ’98
Preliminary
Halt
HTG1390
Frequency of sound effect circuit =
This is a special feature of the HTG1390. It will
stop the chip’s normal operation and reduce
power consumption. When the instruction
“HALT” is executed, then
system clock
2m
...where m=0,1,2,3,4,5.
Holtek’s sound library supports only sound
clock frequencies of 128K or 64K. To use
Holtek’s sound library the proper system clock
and mask option should be selected.
• The system clock will be stopped
• The contents of the on-chip RAM and regis-
ters remain unchanged
LCD display memory
• LCD segments and commons keep 2VDD volt-
As mentioned in the data memory section the
LCD display memory is embedded in the data
memory. It can be read and written to in the
same way as normal data memory.
age (i.e. LCD becomes blank)
The system can escape HALT mode by ways of
initial reset or external interrupt and wake-up
from the following entry of program counter
value.
The figures show the mapping between the display memory and LCD pattern for the
HTG1390.
• Initial reset: 000H.
• Interrupt (enabled): 008H
• Interrupt (disabled): next address of HALT
To turn the display on or off a 1/0 is written to
the corresponding bit of the display memory.
instruction.
In HALT mode, each bit of port PS, PP0~PP2,
can be used as external interrupt by mask option to wake-up system. This signal is active in
low-going transition.
The LCD display module may have any form as
long as the number of commons does not exceed
3 and the number of segments does not exceed
27.
Sound effects
The HTG1390 includes sound effect circuitry
which offers up to 16 sounds with 3 tone, boom
and noise effects. Holtek supports a sound library which has melodies, alarms, machine
guns etc..
Whenever the instruction “SOUND n” or
“SOUND A” is executed, the specified sound
will begin. Whenever “SOUND OFF” is executed, it terminates the singing sound immediately.
There are two singing modes, SONE mode and
SLOOP mode activated by SOUND ONE and
SOUND LOOP. In SONE mode the specified
sound plays just once. In SLOOP mode the
specified sound keeps re-playing.
LCD display memory
Since sounds 0~11 contain 32 notes and sounds
12~15 contain 64 notes the latter possesses better sound than the former.
The frequency of the sound effect circuit can be
selected by mask option.
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17th Nov ’98
Preliminary
HTG1390
LCD driver output
Interfacing
All LCD segments are random after an initial
clear. The bias voltage circuits of the LCD display is built-in and no external resistor is
needed.
The HTG1390 microcontroller communicate
with the outside world through 4-bit input port
PS, 3-bit input port PP and one 4-bit output port
PA.
The output number of the HTG1390 LCD driver
is 27×3 which can directly drive an LCD with
1/3 duty cycle and 1/2 bias.
Input ports – PP, PS
All ports can have internal pull high resistors
determined by mask option. Every bit of the
input ports PP and PS can be specified to be a
trigger source to wake up the HALT interrupt
by mask option . A high to low transition on one
of these pins will wake up the device from a
HALT status.
The frequency of the LCD driving clock is fixed
at about 128Hz. This is set by Holtek according
to the application and cannot be changed.
LCD driver output
Input ports PP and PS
Note: VLCD is produced by double voltage
circuit, therefore its value is double by
VDD.
Output port – PA
A mask option is available to select whether the
output is a CMOS or open drain NMOS type.
After an initial clear the output port PA defaults
to be high for CMOS or floating for NMOS.
Oscillator
Only one external resistor is needed for the
HTG1390 oscillator circuit.
The system clock is also used as the reference
signal of the LCD driving clock, sound effect
clock and internal frequency source of TIMER.
One HTG1390 machine cycle consists of a sequence of 4 states numbered T1 to T4. Each
state lasts for one oscillator period. The machine cycle is 16µs if the system frequency is up
to 256kHz.
Output port PA
RC oscillator
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17th Nov ’98
Preliminary
HTG1390
• 8-bit programmable timer with external clock
Mask options
or internal frequency source. Thirteen internal frequency sources are available to provide
an internal clock. Note that a value of n=6
cannot be used for the devices.
The following either/or options are available by
mask option which the user must select prior to
manufacture.
• 4-bit input ports PP and PS with or without
• Six kinds of sound clock frequency:
pull high resistors
fSYS/2m, m=0, 1, 2, 3, 4, 5
• Each bit of PP and PS can wake up the proc-
essor from a HALT state
• Output Port PA to be CMOS or open drain
NMOS
Application Circuits
R*: Depends on the required system clock frequency. (R=36kΩ~2MΩ, at VDD=1.5V)
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17th Nov ’98
Preliminary
HTG1390
Instruction Set Summary
Mnemonic
Description
Byte
Cycle
CF
Add data memory to ACC
Add data memory with carry to ACC
Subtract data memory from ACC
Subtract data memory from ACC with borrow
Add immediate data to ACC
Subtract immediate data from ACC
Decimal adjust ACC for addition
1
1
1
1
2
2
1
1
1
1
1
2
2
1
√
√
√
√
√
√
√
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
—
—
—
—
—
—
—
—
—
Increment ACC
Increment register, n=0~4
Increment data memory
Increment data memory
Decrement ACC
Decrement register, n=0~4
Decrement data memory
Decrement data memory
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
Move register to ACC, n=0~4
Move ACC to register, n=0~4
Move data memory to ACC
Move data memory to ACC
Move ACC to data memory
Move ACC to data memory
Move immediate data to ACC
Move immediate data to R1 and R0
Move immediate data to R3 and R2
Move immediate data to R4
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
2
2
2
—
—
—
—
—
—
—
—
—
—
Arithmetic
ADD A,[R1R0]
ADC A,[R1R0]
SUB A,[R1R0]
SBC A,[R1R0]
ADD A,XH
SUB A,XH
DAA
Logic Operation
AND A,[R1R0]
OR A,[R1R0]
XOR A,[R1R0]
AND [R1R0],A
OR [R1R0],A
XOR [R1R0],A
AND A,XH
OR A,XH
XOR A,XH
Increment &
Decrement
INC A
INC Rn
INC [R1R0]
INC [R3R2]
DEC A
DEC Rn
DEC [R1R0]
DEC [R3R2]
Data Move
MOV A,Rn
MOV Rn,A
MOV A,[R1R0]
MOV A,[R3R2]
MOV [R1R0],A
MOV [R3R2],A
MOV A,XH
MOV R1R0,XXH
MOV R3R2,XXH
MOV R4,XH
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17th Nov ’98
Preliminary
Mnemonic
Description
HTG1390
Byte
Cycle
CF
Rotate ACC left
Rotate ACC left through the carry
Rotate ACC right
Rotate ACC right through the carry
1
1
1
1
1
1
1
1
√
√
√
√
Input port-i to ACC ,port–i=PS,PP
Output ACC to port-A
1
1
1
1
—
—
Jump unconditionally
Jump on carry=1
Jump on carry=0
Jump on timer overflow
Jump on ACC bit n=1
Jump on ACC is zero
Jump on ACC is not zero
Jump on register Rn not zero, n=0,1,4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
Subroutine call
Return from subroutine or interrupt
Return from interrupt service routine
2
1
1
2
1
1
—
—
Clear carry flag
Set carry flag
Enable interrupt
Disable interrupt
No operation
1
1
1
1
1
1
1
1
1
1
0
1
—
—
—
Set 8 bits immediate data to TIMER
Set TIMER start counting
Set TIMER stop counting
Move low nibble of TIMER to ACC
Move high nibble of TIMER to ACC
Move ACC to low nibble of TIMER
Move ACC to hight nibble of TIMER
2
1
1
1
1
1
1
2
1
1
1
1
1
1
—
—
—
—
—
—
—
Rotate
RL A
RLC A
RR A
RRC A
Input & Output
IN A,Pi
OUT PA,A
Branch
JMP addr
JC addr
JNC addr
JTMR addr
JAn addr
JZ A,addr
JNZ A,addr
JNZ Rn,addr
Subroutine
CALL addr
RET
RETI
√
Flag
CLC
STC
EI
DI
NOP
Timer
TIMER XXH
TIMER ON
TIMER OFF
MOV A,TMRL
MOV A,TMRH
MOV TMRL,A
MOV TMRH,A
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Preliminary
Mnemonic
Description
HTG1390
Byte
Cycle
CF
Read ROM code of current page to R4 & ACC
Read ROM code of current page to M(R1,R0), ACC
Read ROM code of page F to R4 & ACC
Read ROM code of page F to M(R1,R0),ACC
1
1
1
1
2
2
2
2
—
—
—
—
Activate SOUND channel n
Activate SOUND channel with ACC
Turn on SOUND one cycle
Turn on SOUND repeat cycle
Turn off SOUND
2
1
1
1
1
2
1
1
1
1
—
—
—
—
—
Enter power down mode
2
2
—
Table Read
READ R4A
READ MR0A
READF R4A
READF MR0A
Sound Control
SOUND n
SOUND A
SOUND ONE
SOUND LOOP
SOUND OFF
Miscellaneous
HALT
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Preliminary
HTG1390
Instruction Definitions
ADC A,[R1R0]
Add data memory contents and carry to accumulator
Machine code
00001000
Description
The contents of the data memory addressed by the register pair “R1,R0”
and the carry are added to the accumulator. Carry is affected.
Operation
ACC ← ACC+M(R1,R0)+CF
ADD A,XH
Add immediate data to accumulator
Machine code
01000000
Description
The specified data is added to the accumulator. Carry is affected.
Operation
ACC ← ACC+XH
ADD A,[R1R0]
Add data memory contents to accumulator
Machine code
00001001
Description
The contents of the data memory addressed by the register pair “R1,R0” is
added to the accumulator. Carry is affected.
Operation
ACC ← ACC+M(R1,R0)
AND A,XH
Logical AND immediate data to accumulator
Machine code
01000010
Description
Data in the accumulator is logically ANDed with the immediate data specified by the code.
Operation
ACC ← ACC “AND” XH
AND A,[R1R0]
Logical AND accumulator with data memory
Machine code
00011010
Description
Data in the accumulator is logically ANDed with the data memory addressed by the register pair “R1,R0”.
Operation
ACC ← ACC “AND” M(R1,R0)
AND [R1R0],A
Logical AND data memory with accumulator
Machine code
00011101
Description
Data in the data memory addressed by the register pair “R1,R0” is logically ANDed with the accumulator
Operation
M(R1,R0) ← M(R1,R0) “AND” ACC
0000dddd
0000dddd
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Preliminary
HTG1390
CALL address
Subroutine call
Machine code
1111aaaa
Description
The program counter bits 0~11 are saved in the stack and the specified address loaded into the program counter.
Operation
Stack ← PC+2
PC ← address
CLC
Clear carry flag
Machine code
00101010
aaaaaaaa
Description
The carry flag is reset to zero.
Operation
CF ← 0
DAA
Decimal-Adjust accumulator
Machine code
00110110
Description
The accumulator value is adjusted to BCD (Binary Code Decimal), if the
contents of the accumulator is greater than 9 or CF (Carry flag) is one.
Operation
If ACC>9 or CF=1 then
ACC ← ACC+6, CF ← 1
else
ACC ← ACC, CF ← CF
DEC A
Decrement accumulator
Machine code
00111111
Description
Data in the accumulator is decremented by one. Carry flag is not affected.
Operation
ACC ← ACC–1
DEC Rn
Decrement register
Machine code
0001nnn1
Description
Data in the working register “Rn” is decremented by one. Carry flag is not
affected.
Operation
Rn ← Rn–1; Rn=R0,R1,R2,R3,R4, for nnn=0,1,2,3,4
DEC [R1R0]
Decrement data memory
Machine code
00001101
Description
Data in the data memory specified by the register pair “R1,R0” is decremented by one. Carry flag is not affected.
Operation
M(R1,R0) ← M(R1,R0)–1
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Preliminary
HTG1390
DEC [R3R2]
Decrement data memory
Machine code
00001111
Description
Data in the data memory specified by the register pair “R3,R2” is decremented by one. Carry flag is not affected.
Operation
M(R3,R2) ← M(R3,R2)–1
DI
Disable interrupt
Machine code
00101101
Description
Internal time-out interrupt and external interrupt are disabled.
EI
Enable interrupt
Machine code
00101100
Description
Internal time-out interrupt and external interrupt are enabled.
HALT
Halt system clock
Machine code
00110111
Description
Turn off system clock, and enter power down mode.
Operation
PC ← PC+2
IN A,Pi
Input port to accumulator
Machine code
PS
00110011
PP
00110100
00111110
Description
The data on port “Pi” is transferred to the accumulator.
Operation
ACC ← Pi; Pi=PS or PP
INC A
Increment accumulator
Machine code
00110001
Description
Data in the accumulator is incremented by one. Carry flag is not affected.
Operation
ACC ← ACC+1
INC Rn
Increment register
Machine code
0001nnn0
Description
Data in the working register “Rn” is incremented by one. Carry flag is not
affected.
Operation
Rn ← Rn+1; Rn=R0~R4 for nnn=0~4
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HTG1390
INC [R1R0]
Increment data memory
Machine code
00001100
Description
Data in the data memory specified by the register pair “R1,R0” is incremented by one. Carry flag is not affected.
Operation
M(R1,R0) ← M(R1,R0)+1
INC [R3R2]
Increment data memory
Machine code
00001110
Description
Data memory specified by the register pair “R3,R2” is incremented by one.
Carry flag is not affacted.
Operation
M(R3,R2) ← M(R3,R2)+1
JAn address
Jump if accumulator bit n is set
Machine code
100nnaaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address but bit 11 of the program counter is unaffected, if accumulator bit
n is set to one.
Operation
PC (bit 0~10) ← address, if ACC bit n=1(n=0~3)
PC ← PC+2, if ACC bit n=0
JC address
Jump if carry is set
Machine code
11000aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address but bit 11 of the program counter is unaffected, if the CF (Carry
flag) is set to one.
Operation
PC (bit 0~10) ← address, if CF=1
PC ← PC+2, if CF=0
aaaaaaaa
aaaaaaaa
JMP address
Direct jump
Machine code
1110aaaa
Description
Bits 0~11 of the program counter are replaced with the directly-specified
address.
Operation
PC ← address
JNC address
Jump if carry is not set
Machine code
11001aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address and bit 11 of the program counter is unaffected, if the CF (Carry
flag) is set to zero.
Operation
PC (bit 0~10) ← address, if CF=0
PC ← PC+2, if CF=1
aaaaaaaa
aaaaaaaa
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Preliminary
HTG1390
JNZ A,address
Jump if accumulator is not zero
Machine code
10111aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address but bit 11 of the program counter is unaffected, if the accumulator
is not zero.
Operation
PC (bit 0~10) ← address, if ACC≠0
PC ← PC+2, if ACC=0
JNZ Rn,address
Jump if register is not zero
Machine code
R0
10100aaa
aaaaaaaa
R1
10101aaa
aaaaaaaa
R4
11011aaa
aaaaaaaa
aaaaaaaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address but bit 11 of the program counter is unaffected, if the register is
not zero.
Operation
PC (bit 0~10) ← address, if Rn≠0; Rn=R0,R1,R4
PC ← PC+2, if Rn=0
JTMR address
Jump if time-out
Machine code
11010aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address but bit 11 of the program counter is unaffected, if the TF (Timer
flag) is set to one.
Operation
PC (bit 0~10) ← address, if TF=1
PC ← PC+2, if TF=0
aaaaaaaa
JZ A,address
Jump if accumulator is zero
Machine code
10110aaa
Description
Bits 0~10 of the program counter are replaced with the directly-specified
address but bit 11 of the program counter is unaffected, if the accumulator
is zero.
Operation
PC (bit 0~10) ← address, if ACC=0
PC ← PC+2, if ACC≠0
MOV A,Rn
Move register to accumulator
Machine code
0010nnn1
Description
Data in the working register “Rn” is moved to the accumulator.
Operation
ACC ← Rn; Rn=R0~R4, for nnn=0~4
aaaaaaaa
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Preliminary
HTG1390
MOV A,TMRH
Move timer high nibble to accumulator
Machine code
00111011
Description
The high nibble data of the timer counter is loaded to the accumulator.
Operation
ACC ← TIMER (high nibble)
MOV A,TMRL
Move timer low nibble to accumulator
Machine code
00111010
Description
The low nibble data of the timer counter is loaded to the accumulator.
Operation
ACC ← TIMER (low nibble)
MOV A,XH
Move immediate data to accumulator
Machine code
0111dddd
Description
The 4-bit data specified by the code is loaded to the accumulator.
Operation
ACC ← XH
MOV A,[R1R0]
Move data memory to accumulator
Machine code
00000100
Description
Data in the data memory specified by the register pair “R1,R0” is moved to
the accumulator.
Operation
ACC ← M(R1,R0)
MOV A,[R3R2]
Move data memory to accumulator
Machine code
00000110
Description
Data in the data memory specified by the register pair “R3,R2” is moved to
the accumulator.
Operation
ACC ← M(R3,R2)
MOV R1R0,XXH
Move immediate data to R1 and R0
Machine code
0101dddd
Description
The 8-bit data specified by the code is loaded to the working registers R1
and R0, the high nibble of the data is loaded to R1, and the low nibble to
R0.
Operation
R1 ← XH (high nibble)
R0 ← XH (low nibble)
MOV R3R2,XXH
Move immediate data to R3 and R2
Machine code
0110dddd
Description
The 8-bit data specified by the code is loaded to the working registers R3
and R2, the high nibble of the data is loaded to R3, and the low nibble to
R2.
Operation
R3 ← XH (high nibble)
R2 ← XH (low nibble)
0000dddd
0000dddd
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Preliminary
HTG1390
MOV R4,XH
Move immediate data to R4
Machine code
01000110
Description
The 4-bit data specified by the code is loaded to the working register R4.
Operation
R4 ← XH
MOV Rn,A
Move accumulator to register
Machine code
0010nnn0
Description
Data in the accumulator is moved to the working register “Rn”.
Operation
Rn ← ACC; Rn=R0~R4, for nnn=0~4
MOV TMRH,A
Move accumulator to timer high nibble
Machine code
00111101
Description
The contents of the accumulator is loaded to the high nibble of the timer
counter.
Operation
TIMER(high nibble) ← ACC
MOV TMRL,A
Move accumulator to timer low nibble
Machine code
00111100
Description
The contents of the accumulator is loaded to the low nibble of the timer
counter.
Operation
TIMER(low nibble) ← ACC
MOV [R1R0],A
Move accumulator to data memory
Machine code
00000101
Description
Data in the accumulator is moved to the data memory specified by the register pair “R1,R0”.
Operation
M(R1,R0) ← ACC
MOV [R3R2],A
Move accumulator to data memory
Machine code
00000111
Description
Data in the accumulator is moved to the data memory specified by the register pair “R3,R2”.
Operation
M(R3,R2) ← ACC
NOP
No operation
Machine code
00111110
Description
Do nothing, but one instruction cycle is delayed.
0000dddd
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Preliminary
HTG1390
OR A,XH
Logical OR immediate data to accumulator
Machine code
01000100
Description
Data in the accumulator is logically ORed with the immediate data specified by the code.
Operation
ACC ← ACC “OR” XH
0000dddd
OR A,[R1R0]
Logical OR accumulator with data memory
Machine code
00011100
Description
Data in the accumulator is logically ORed with the data memory addressed by the register pair “R1,R0”.
Operation
ACC ← ACC “OR” M(R1,R0)
OR [R1R0],A
Logically OR data memory with accumulator
Machine code
00011111
Description
Data in the data memory addressed by the register pair “R1,R0” is logically ORed with the accumulator.
Operation
M(R1,R0) ← M(R1,R0) “OR” ACC
OUT PA,A
Output accumulator data to port A
Machine code
00110000
Description
The data in the accumulator is transferred to port PA and latched.
Operation
PA ← ACC
READ MR0A
Read ROM code of current page to M(R1,R0) and ACC
Machine code
01001110
Description
The 8-bit ROM code (current page) addressed by ACC and R4 is moved to
the data memory M(R1,R0) and the accumulator. The high nibble of the
ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is
loaded to the accumulator. The address of the ROM code is specified as below:
Current page → ROM code address bit 11~8
ACC → ROM code address bit 7~4
R4 → ROM code address bit 3~0
Operation
M(R1,R0) ← ROM code (high nibble)
ACC ← ROM code (low nibble)
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HTG1390
READ R4A
Read ROM code of current page to R4 and accumulator
Machine code
01001100
Description
The 8-bit ROM code (current page) addressed by ACC and M(R1,R0) is
moved to the working register R4 and the accumulator. The high nibble of
the ROM code is loaded to R4 and the low nibble of the ROM code is loaded
to the accumulator. The address of the ROM code is specified as below:
Current page → ROM code address bit 11~8
ACC → ROM code address bit 7~4
M(R1,R0) → ROM code address bit 3~0
Operation
R4 ← ROM code (high nibble)
ACC ← ROM code (low nibble)
READF MR0A
Read ROM Code of page F to M(R1,R0) and ACC
Machine code
01001111
Description
The 8-bit ROM code (page F) addressed by ACC and R4 is moved to the
data memory M(R1,R0) and the accumulator. The high nibble of the ROM
code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to
the accumulator.
Page F → ROM code address bit 11~8 are “1111”
ACC → ROM code address bit 7~4
R4 → ROM code address bit 3~0
Operation
M(R1,R0) ← high nibble of ROM code (page F)
ACC ← low nibble of ROM code (page F)
READF R4A
Read ROM code of page F to R4 and accumulator
Machine code
01001101
Description
The 8-bit ROM code (page F) addressed by ACC and M(R1,R0) is moved to
the working register R4 and the accumulator. The high nibble of the ROM
code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator.
Page F → ROM code address bit 11~8 are “1111”
ACC → ROM code address bit 7~4
M(R1,R0) → ROM code address bit 3~0
Operation
R4 ← high nibble of ROM code (page F)
ACC ← low nibble of ROM code (page F)
RET
Return from subroutine or interrupt
Machine code
00101110
Description
The program counter bits 0~11 are restored from the stack.
Operation
PC ← Stack
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HTG1390
RETI
Return from interrupt subroutine
Machine code
00101111
Decription
The program counter bits 0~11 are restored from the stack. The carry flag
before entering the interrupt service routine is restored.
Operation
PC ← Stack
CF ← CF (before interrupt service routine)
RL A
Rotate accumulator left
Machine code
00000001
Description
The contents of the accumulator are rotated left one bit. Bit 3 is rotated to
both bit 0 and the carry flag.
Operation
An+1 ← An, An: accumulator bit n (n=0,1,2)
A0 ← A3
CF ← A3
RLC A
Rotate accumulator left through carry
Machine code
00000011
Description
The contents of the accumulator are rotated left one bit. Bit 3 replaces the
carry bit, which is rotated into the bit 0 position.
Operation
An+1 ← An, An: Accumulator bit n (n=0,1,2)
A0 ← CF
CF ← A3
RR A
Rotate accumulator right
Machine code
00000000
Description
The contents of the accumulator are rotated right one bit. Bit 0 is rotated
to both bit 3 and the carry flag.
Operation
An ← An+1, An: Accumulator bit n (n=0,1,2)
A3 ← A0
CF ← A0
RRC A
Rotate accumulator right through carry
Machine code
00000010
Description
The contents of the accumulator are rotated right one bit. Bit 0 replaces
the carry bit, which bit is rotated into the bit 3 position.
Operation
An ← An+1, An: Accumulator bit n (n=0,1,2)
A3 ← CF
CF ← A0
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Preliminary
HTG1390
SBC A,[R1R0]
Subtract data memory contents and carry from ACC
Machine code
00001010
Description
The contents of the data memory addressed by the register pair “R1,R0”
and the complement of the carry are subtracted from the accumulator.
Carry is set if a borrow does not take place in subtraction; otherwise carry
is cleared.
Operation
ACC ← ACC+M(R1,R0)+CF
SOUND A
Activate SOUND channel with accumulator
Machine code
01001011
Description
The activated sound begins playing in accordance with the contents of accumulator when the specified sound channel is matched.
SOUND LOOP
Turn on sound repeat cycle
Machine code
01001001
Description
The activated sound plays repeatedly.
SOUND OFF
Turn off sound
Machine code
01001010
Description
The activated sound will terminate immediately.
SOUND ONE
Turn on sound one cycle
Machine code
01001000
Description
The activated sound plays once.
SOUND n
Activate SOUND channel n
Machine code
01000101
Description
The specified sound begins playing and overwrites the previous activated
sound. (nnnn=0~15)
0000nnnn
STC
Set carry flag
Machine code
00101011
Description
The carry flag is set to one.
Operation
CF ← 1
SUB A,XH
Subtract immediate data from accumulator
Machine code
01000001
Description
The specified data is subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared.
Operation
ACC ← ACC+XH+1
0000dddd
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Preliminary
HTG1390
SUB A,[R1R0]
Subtract data memory contents from accumulator
Machine code
00001011
Description
The contents of the data memory addressed by the register pair “R1,R0” is
subtracted from the accumulator. Carry is set if a borrow does not take
place in subtraction; otherwise carry is cleared.
Operation
ACC ← ACC+M(R1,R0)+1
TIMER OFF
Set timer stop counting
Machine code
00111001
Description
The timer stops counting, when the “TIMER OFF” instruction is executed.
TIMER ON
Set timer start counting
Machine code
00111000
Description
The timer starts counting, when the “TIMER ON” instruction is executed.
TIMER XXH
Set immediate data to timer counter
Machine code
01000111
Description
The 8-bit data specified by the code is loaded to the timer counter.
Operation
TIMER ← XXH
XOR A,XH
Logical XOR immediate data to accumulator
Machine code
01000011
Description
Data in the accumulator is Exclusive-ORed with the immediate data specified by the code.
Operation
ACC ← ACC “XOR” XH
XOR A,[R1R0]
Logical XOR accumulator with data memory
Machine code
00011011
Description
Data in the accumulator is Exclusive-ORed with the data memory addressed by the register pair “R1,R0”.
Operation
ACC ← ACC “XOR” M(R1,R0)
XOR [R1R0],A
Logical XOR data memory with accumulator
Machine code
00011110
Description
Data in the data memory addressed by the register pair “R1,R0” is logically Exclusive-ORed with the accumulator.
Operation
M(R1,R0) ← M(R1,R0) “XOR” ACC
dddddddd
0000dddd
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17th Nov ’98