HYNIX HY29F002T

HY29F002T
2 Megabit (256K x 8), 5 Volt-only, Flash Memory
KEY FEATURES
n 5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
n High Performance
– Access times as fast as 45 ns
n Low Power Consumption
– 20 mA typical active read current
– 30 mA typical program/erase current
– 1 µA typical CMOS standby current
n Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n Sector Erase Architecture
– Boot sector architecture with top boot
block location
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and three 64K byte sectors
– A command can erase any combination of
sectors
– Supports full chip erase
n Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
n Sector Protection
– Any combination of sectors may be
locked to prevent program or erase
operations within those sectors
n Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 7 sec typical
n Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n Minimum 100,000 Program/Erase Cycles
n Space Efficient Packaging
– Available in industry-standard 32-pin
TSOP and PLCC packages
GENERAL DESCRIPTION
LOGIC DIAGRAM
The HY29F002T is an 2 Megabit, 5 volt-only
CMOS Flash memory organized as 262,144
(256K) bytes. The device is offered in industrystandard 32-pin TSOP and PLCC packages.
The HY29F002T can be programmed and erased
in-system with a single 5-volt VCC supply. Internally generated and regulated voltages are provided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM programmers. Access times as fast as 55ns over the
full operating voltage range of 5.0 volts ± 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
A 45ns version operating over 5.0 volts ± 5% is
also available. To eliminate bus contention, the
Revision 4.1, May 2001
18
8
A[17:0]
RESET#
CE#
OE#
WE#
DQ[7:0]
HY29F002T
HY29F002T has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC single
power-supply Flash command set standard. Commands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte at a time
by executing the four-cycle Program Command.
This initiates an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
the device has a Sector Protect function which
hardware write protects selected sectors. The
sector protect and unprotect features can be enabled in a PROM programmer. Temporary Sector Unprotect, which requires a high voltage, allows in-system erasure and code changes in previously protected sectors.
Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
The HY29F002T’s sector erase architecture allows
any number of array sectors to be erased and reprogrammed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command. This initiates an
internal algorithm that automatically preprograms
the array (if it is not already programmed) before
executing the erase operation. During erase
cycles, the device automatically times the erase
pulse widths and verifies proper cell margin.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
reading the DQ[7] (Data# Polling) and DQ[6]
(toggle) status bits. Reading data from the device
is similar to reading from SRAM or EPROM devices. Hardware data protection measures include
a low VCC detector that automatically inhibits write
operations during power transitions.
To protect data in the device from accidental or
unauthorized attempts to program or erase the
device while it is in the system (e.g., by a virus),
The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
BLOCK DIAGRAM
DQ[7:0]
STATE
CONTROL
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
DQ[7:0]
WE#
COMMAND
REGISTER
I/O BUFFERS
CE#
RESET#
I/O CONTROL
ELECTRONIC
ID
DATA LATCH
PROGRAM
VOLTAGE
GENERATOR
VSS
VCC
A[17:0]
2
VCC DETECTOR
TIMER
ADDRESS LATCH
OE#
Y-DECODER
X-DECODER
Y-GATING
2 MBIT
FLASH
MEMORY
ARRAY
(7 Sectors)
Rev. 4.1/May 01
HY29F002T
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TSOP32
OE#
A[10]
CE#
DQ[7]
DQ[6]
DQ[5]
DQ[4]
DQ[3]
V SS
DQ[2]
DQ[1]
DQ[0]
A[0]
A[1]
A[2]
A[3]
A[12]
A[15]
A[16]
RESET#
V CC
WE#
A[17]
A[11]
A[9]
A[8]
A[13]
A[14]
A[17]
WE#
V CC
RESET#
A[16]
A[15]
A[12]
A[7]
A[6]
A[5]
A[4]
4 3 2 1 32 31 30
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
DQ[0]
5
6
7
8
9
10
11
12
13
PLCC32
29
28
27
26
25
24
23
22
21
A[14]
A[13]
A[8]
A[9]
A[11]
OE#
A[10]
CE#
DQ[7]
DQ[1]
DQ[2]
V SS
DQ[3]
DQ[4]
DQ[5]
DQ[6]
14 15 16 17 18 19 20
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this document, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the signal is asserted in a Low state (nominally 0 volts).
Rev. 4.1/May 01
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a number expressed in binary notation (X =
0, 1).
3
HY29F002T
SIGNAL DESCRIPTIONS
Name
A[17:0]
DQ[7:0]
C E#
OE#
WE#
RESET#
VCC
Type
Description
Address, active High. These eighteen inputs select one of 262,144 (256K)
bytes within the array for read or write operations. A[17] is the MSB and A[0] is
the LSB.
Inputs/Outputs Data Bus, active High. These pins provide an 8-bit data path for read and
Tri-state
write operations.
Chip Enable, active Low. This input must be asserted to read data from or
Input
wri te data to the HY29F002T. When Hi gh, the data bus i s tri -stated and the
device is placed in the Standby mode.
Output Enable, active Low . This input must be asserted for read operations
Input
and negated for write operations. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
W r ite E n a b le , a c tiv e L o w. C o ntro ls wri ti ng o f c o mma nd s o r c o mma nd
Input
se q ue nce s i n o rd e r to p ro g ra m d a ta o r p e rfo rm o the r o p e ra ti o ns. A wri te
operation takes place when WE# is asserted while CE# is Low and OE# is High.
Hardw are Reset, active Low. Provides a hardware method of resetting the
HY29F002T to the read array state. When the device is reset, it immediately
Input
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
5-volt (nominal) pow er supply.
-Inputs
V SS
Pow er and signal ground.
--
MEMORY ARRAY ORGANIZATION
The 256 Kbyte Flash memory array is organized
into seven blocks called sectors (S0, S1, . . . ,
S6). A sector is the smallest unit that can be
erased and which can be protected to prevent
accidental or unauthorized erasure. See the ‘Bus
Operations’ and ‘Command Definitions’ sections
of this document for additional information on these
functions.
In the HY29F002T, four of the sectors, which comprise the boot block, vary in size from 8 to 32
Kbytes, while the remaining three sectors are
uniformly sized at 64 Kbytes. In this device, the
boot block is located at the top of the address
range.
Table 1 defines the sector addresses and corresponding address ranges for the HY29F002T.
Table 1. HY29F002T Memory Array Organization
Sector
S0
S1
S2
S3
S4
S5
S6
4
Sector Address
Siz e
(Kbytes)
A[17]
A[16]
A[15]
A[14]
A[13]
64
64
64
32
8
8
16
0
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
0
1
1
1
X
X
X
X
0
0
1
X
X
X
X
0
1
X
Address Range
0x00000 - 0x0FFFF
0x10000 - 0x1FFFF
0x20000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x39FFF
0x3A000 - 0x3BFFF
0x3C000 - 0x3FFFF
Rev. 4.1/May 01
HY29F002T
Table 2. HY29F002T Normal Bus Operations 1
Operation
CE#
OE#
WE#
RESET #
A[17:0]
DQ[7:0]
Read
L
L
H
H
AIN
DOUT
Write
L
H
L
H
AIN
DIN
Output Disable
L
H
H
H
X
High-Z
CE# TTL Standby
H
X
X
H
X
High-Z
VCC ± 0.5V
X
X
VCC ± 0.5V
X
High-Z
Hardware Reset (TTL Standby)
X
X
X
L
X
High-Z
Hardware Reset (CMOS Standby)
X
X
X
VSS ± 0.5V
X
High-Z
CE# CMOS Standby
Notes:
1. L = VIL, H = VIH, X = Don’t Care, DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels.
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state machine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
Read Operation
Data is read from the HY29F002T by using standard microprocessor read cycles while placing the
address of the byte to be read on the device’s
address inputs, A[17:0]. As shown in Table 2, the
host system must drive the CE# and OE# inputs
Low and drive WE# High for a valid read operation to take place. The device outputs the specified array data on DQ[7:0].
The HY29F002T is automatically set for reading
array data after device power-up and after a hardware reset to ensure that no spurious alteration of
the memory content occurs during the power transition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register contents are altered.
data from or program data into any sector of
memory that is not marked for erasure. If the host
attempts to read from an address within an erasesuspended sector, or while the device is performing an erase or byte program operation, the device outputs status data instead of array data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read
array data with the same exceptions noted above.
After completing an internal program or internal
erase algorithm, the HY29F002T automatically returns to the read array data mode.
The host must issue a hardware reset or the software reset command (see Command Definitions)
to return a sector to the read array data mode if
DQ[5] goes high during a program or erase cycle,
or to return the device to the read array data mode
while it is in the Electronic ID mode.
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29F002T. Writes to the device are performed
by placing the byte address on the device’s address inputs while the data to be written is input
on DQ[7:0]. The host system must drive the CE#
and WE# pins Low and drive OE# High for a valid
write operation to take place. All addresses are
latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
Rev. 4.1/May 01
5
HY29F002T
Table 3. HY29F002T Bus Operations Requiring High Voltage 1, 2
Operation 3
C E#
Sector Protect
OE#
WE#
R E S E T#
A[17: 13]
4
A[9]
A[6]
A[1]
A[0]
DQ[7: 0]
VID
X
X
X
X
L
VID
X
H
SA
Sector Unprotect
VID
VID
X
H
X
VID
X
X
X
X
Temporary Sector
Unprotect
X
X
X
VID
X
X
X
X
X
X
Manufacturer Code
L
L
H
H
X
VID
L
L
L
0xAD
Device Code
L
L
H
H
X
VID
L
L
H
0xB0
L
L
H
H
SA 4
VID
L
H
L
Sector
Protection
Verification
Unprotected
0x00
Protected
0x01
Notes:
1. L = VIL, H = VIH, X = Don’t Care. See DC Characteristics for voltage levels.
2. Address bits not specified are Don’t Care.
3. See text for additional information.
4. SA = sector address. See Table 1.
The ‘Device Commands’ section of this document
provides details on the specific device commands
implemented in the HY29F002T.
Output Disable Operation
When the OE# input is at VIH, output data from the
device is disabled and the data bus pins are placed
in the high impedance state.
Standby Operation
When the system is not reading from or writing to
the HY29F002T, it can place the device in the
Standby mode. In this mode, current consumption is greatly reduced, and the data bus outputs
are placed in the high impedance state, independent of the OE# input. The Standby mode can
invoked using two methods.
The device enters the CE# CMOS Standby mode
if the CE# and RESET# pins are both held at VCC
± 0.5V. Note that this is a more restricted voltage
range than VIH. If both CE# and RESET# are held
High, but not within VCC ± 0.5V, the device will be
in the CE# TTL Standby mode, but the standby
current will be greater.
The device enters the RESET# CMOS Standby
mode when the RESET# pin is held at VSS ± 0.5V.
If RESET# is held Low but not within VSS ± 0.5V,
the HY29F002T will be in the RESET# TTL
Standby mode, but the standby current will be
greater. See Hardware Reset Operation section
for additional information on the reset operation.
6
The device requires standard access time (tCE) for
read access when the device is in either of the
standby modes, before it is ready to read data. If
the device is deselected during erasure or programming, it continues to draw active current until
the operation is completed.
Hardware Reset Operation
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven Low for the minimum
specified period, the device immediately terminates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the assertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation section above.
If RESET# is asserted during a program or erase
operation, the internal reset operation is completed
within a time of tREADY (during Automatic Algorithms). The system can perform a read or write
operation after waiting for a minimum of tREADY or
until tRH after the RESET# pin returns High, whichever is longer. If RESET# is asserted when a program or erase operation is not executing, the reRev. 4.1/May 01
HY29F002T
set operation is completed within a time of tRP. In
this case, the host can perform a read or write
operation tRH after the RESET# pin returns High.
The RESET# pin may be tied to the system reset
signal. Thus, a system reset would also reset the
device, enabling the system to read the boot-up
firmware from the Flash memory.
Sector Protect/Unprotect Operations
Hardware sector protection can be invoked to disable program and erase operations in any single
sector or combination of sectors. This function is
typically used to protect data in the device from
unauthorized or accidental attempts to program
or erase the device while it is in the system (e.g.,
by a virus) and is implemented using programming equipment. Sector unprotection re-enables
the program and erase operations in previously
protected sectors.
Table 1 identifies the seven sector in the top and
bottom boot block versions of the HY29F002T and
the address ranges that each covers. The device
is shipped with all sectors unprotected.
The sector protect/unprotect operations require a
high voltage (VID) on address pin A[9] and the CE#
and/or OE# control pins, as detailed in Table 3.
When implementing these operations, note that
VCC must be applied to the device before applying
VID, and that VID should be removed before removing VCC from the device.
The flow chart in Figure 1 illustrates the procedure for protecting sectors, and timing specifications and waveforms are shown in the specifications section of this document. Verification of protection is accomplished as described in the Electronic ID Mode section and shown in the flow chart.
The procedure for sector unprotection is illustrated
in the flow chart in Figure 2, and timing specifications and waveforms are given at the end of this
document. Note that to unprotect any sector, all
Rev. 4.1/May 01
unprotected sectors must first be protected prior
to the first unprotect write cycle.
Sectors can also be temporarily unprotected as
described in the next section.
Temporary Sector Unprotect Operation
This feature allows temporary unprotection of previously protected sectors to allow changing the
data in-system. Temporary Sector Unprotect
mode is activated by setting the RESET# pin to
VID. While in this mode, formerly protected sectors can be programmed or erased by invoking
the appropriate commands (see Device Commands section). Once VID is removed from RESET#, all the previously protected sectors are protected again. Figure 3 illustrates the algorithm.
Electronic ID Mode Operation
The Electronic ID mode provides manufacturer and
device identification and sector protection verification through identifier codes output on DQ[7:0].
This mode is intended primarily for programming
equipment to automatically match a device to be
programmed with its corresponding programming
algorithm. The Electronic ID information can also
be obtained by the host through a command sequence, as described in the Device Commands
section.
Operation in the Electronic ID mode requires VID
on address pin A[9], with additional requirements
for obtaining specific data items as listed in Table
2:
n A read cycle at address 0xXXX00 retrieves the
manufacturer code (Hynix = 0xAD).
n A read cycle at address 0xXXX01 returns the
device code (HY29F002T = 0xB0).
n A read cycle containing a sector address (Table
1) in A[17:13] and the address 0x02 in A[7:0]
returns 0x01 if that sector is protected, or 0x00
if it is unprotected.
7
HY29F002T
Wait t W P P 1
START
WE# = V IH
APPLY V
CC
A[9] = V ID
A[17:13] = Sector to Protect
OE# = CE# = V IL
A[6] = A[0] = V IL
A[1] = V IH
Set TRYCNT = 1
Increment TRYCNT
Read Data
Set A[9] = OE# = V
NO
ID
Data = 0x01?
Set Address:
A[17:13] = Sector to Protect
CE# = V IL
RESET# = V IH
WE# = V IL
NO
TRYCNT = 25?
YES
YES
Remove V ID from A[9]
Protect Another
Sector?
NO
DEVICE FAILURE
SECTOR PROTECT
COMPLETE
YES
Figure 1. Sector Protect Procedure
8
Rev. 4.1/May 01
HY29F002T
START
NOTE: All sectors must be
previously protected.
APPLY V
Increment TRYCNT
Set Sector Address:
A[17:13] = Sector NSEC
A[0] = A[6] = V IL
A[1] = V IH
CC
Set: TRYCNT = 1
Read Data
NO
Set: NSEC = 0
Data = 0x00?
Set: A[9] = CE# = OE# = V
Set: RESET# = V
NO
YES
TRYCNT = 1000?
ID
YES
IH
W E # = V IL
NSEC = 6?
YES
Remove V
Wait t W P P 2
NO
ID
from A[9]
NSEC = NSEC + 1
SECTOR UNPROTECT
COMPLETE
W E # = V IH
Set:
A[9] = V ID
OE# = CE# = V
DEVICE FAILURE
IL
Figure 2. Sector Unprotect Procedure
DEVICE COMMANDS
START
R E S E T # = V ID
(All protected sectors
become unprotected)
Perform Program or Erase
Operations
R E S E T # = V IH
(All previously protected
sectors return to
protected state)
Device operations are initiated by writing designated address and data command sequences into
the device. A command sequence is composed
of one, two or three of the following sub-segments:
an unlock cycle, a command cycle and a data
cycle. Table 4 summarizes the composition of the
valid command sequences implemented in the
HY29F002T, and these sequences are fully described in Table 5 and in the sections that follow.
Writing incorrect address and data values or writing them in the improper sequence resets the
HY29F002T to the Read mode.
Read/Reset 1, 2 Commands
TEMPORARY SECTOR
UNPROTECT COMPLETE
Figure 3. Temporary Sector Unprotect
Rev. 4.1/May 01
The HY29F002T automatically enters the Read
mode after device power-up, after the RESET#
input is asserted and upon the completion of certain commands. Read/Reset commands are not
required to retrieve data in these cases.
9
HY29F002T
Table 4. Composition of Command Sequences
Command
Sequence
Number of Bus Cycles
Unlock Command
Data
Read/Reset 1
0
1
Note 1
Read/Reset 2
2
1
Note 1
Byte Program
2
1
1
Chip Erase
4
1
1
Sector Erase
4
1
1 (Note 2)
Erase Suspend
0
1
0
Erase Resume
0
1
0
Electronic ID
2
1
Note 3
Notes:
1. Any number of Flash array read cycles are permitted.
2. Additional data cycles may follow. See text.
3. Any number of Electronic ID read cycles are permitted.
A Read/Reset command must be issued in order
to read array data in the following cases:
n If the device is in the Electronic ID mode, a
Read/ Reset command must be written to return to the Read mode. If the device was in the
Erase Suspend mode when the device entered
the Electronic ID mode, writing the Read/Reset command returns the device to the Erase
Suspend mode.
Note: When in the Electronic ID bus operation mode,
the device returns to the Read mode when VID is removed from the A[9] pin. The Read/Reset command is
not required in this case.
n If DQ[5] (Exceeded Time Limit) goes High during a program or erase operation, writing the
reset command returns the sectors to the Read
mode (or to the Erase Suspend mode if the
device was in Erase Suspend).
The Read/Reset command may also be used to
abort certain command sequences:
n In a Sector Erase or Chip Erase command sequence, the Read/Reset command may be
written at any time before erasing actually begins, including, for the Sector Erase command,
between the cycles that specify the sectors to
be erased (see Sector Erase command description). This aborts the command and resets the device to the Read mode. Once erasure begins, however, the device ignores Read/
Reset commands until the operation is complete.
10
n In a Program command sequence, the Read/
Reset command may be written between the
sequence cycles before programming actually
begins. This aborts the command and resets
the device to the Read mode, or to the Erase
Suspend mode if the Program command sequence is written while the device is in the
Erase Suspend mode. Once programming
begins, however, the device ignores Read/Reset commands until the operation is complete.
n The Read/Reset command may be written between the cycles in an Electronic ID command
sequence to abort that command. As described
above, once in the Electronic ID mode, the
Read/ Reset command must be written to return to the Read mode.
Byte Program Command
The host processor programs the device a byte at
a time by issuing the Program command sequence
shown in Table 5. The sequence begins by writing two unlock cycles, followed by the Program
setup command and, lastly, a data cycle specifying the program address and data. This initiates
the Automatic Programming algorithm, which provides internally generated program pulses and
verifies the programmed cell margin. The host is
not required to provide further controls or timings
during this operation. When the Automatic Programming algorithm is complete, the device returns to the Read mode. Several methods are
provided to allow the host to determine the status
of the programming operation, as described in the
Write Operation Status section.
Commands written to the device during execution
of the Automatic Programming algorithm are ignored. Note that a hardware reset immediately
terminates the programming operation. To ensure data integrity, the aborted program command
sequence should be reinitiated once the reset
operation is complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored “0” to a “1”.
Thus, a bit cannot be programmed from a “0” back
to a “1”. Attempting to do so will set DQ[5] to “1”,
and the Data# Polling algorithm will indicate that
the operation was not successful. A Read/Reset
command or a hardware reset is required to exit
Rev. 4.1/May 01
Rev. 4.1/May 01
XXX
555
555
555
555
XXX
XXX
555
3
Add
AA
F0
AA
AA
AA
AA
B0
30
Data
First
1
3
4
6
6
1
1
Write
Cycles
55
RD
55
55
55
55
Data
555
555
555
555
555
Add
90
F0
A0
80
80
Data
Third
RD
PD
AA
AA
AD
B0
STAT
X 00
X 01
VSA
Data
RA
PA
555
555
Add
Fourth
2A A
2A A
Add
55
55
Data
Fifth
PA = Address of the data to be programmed
PD = Data to be programmed at address PA
SA = Sector address of sector to be erased (see Note 3 and Table 1).
VSA = Address of the sector to be verified (see Note 3 and Table 1).
2A A
RA
2A A
2A A
2A A
2A A
Add
S eco n d
Bus Cycles 1, 2, 3
555
SA
Add
10
30
Data
Sixth
Notes:
1. All values are in hexadecimal.
2. All bus cycles are write operations unless otherwise noted.
3. Address is A[10:0] and A[17:11] are don’t care except as follows:
• For RA and PA, A[17:11] are the upper address bits of the byte to be read or programmed.
• For SA, A[17:13] are the sector address of the sector to be erased and A[12:0] are don’t care.
• For VSA, A[17:13] are the address of the sector to be verified, A[7:0] = 0x02, all other address bits are don’t care.
4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-erasing sectors, or enter the
Electronic ID mode, while in the Erase Suspend mode.
5. The Erase Resume command is valid only during the Erase Suspend mode.
6. The second bus cycle is a read cycle.
7. The fourth bus cycle is a read cycle.
8. Either command sequence is valid. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or if
DQ[5] goes High during a program or erase operation. It is not required for normal read operations.
Legend:
X = Don’t Care
RA = Memory address of data to be read
RD = Data read from location RA during the read operation
STAT = Sector protect status: 0x00 = unprotected, 0x01 = protected.
Read/Reset 1 6, 8
Reset/Reset 2 7, 8
Byte Program
Chip Erase
Sector Erase
Erase Suspend 4
Erase Resume 5
Manufacturer Code
Electronic
D
evice Code - HY29F002T
ID 7
Group Protect Verify
Command Sequence
Table 5. HY29F002T Command Sequences
HY29F002T
11
HY29F002T
START
START
Issue PROGRAM
Command Sequence:
Last cycle contains
program Address/Data
Check Programming Status
(See Write Operation Status
Section)
Issue CHIP ERASE
Command Sequence
DQ[5] Error Exit
Check Erase Status
(See Write Operation Status
Section)
DQ[5] Error Exit
Normal Exit
Normal Exit
CHIP ERASE COMPLETE
NO
Last Word/Byte
Done?
Figure 5. Chip Erase Procedure
YES
PROGRAMMING
COMPLETE
GO TO
ERROR RECOVERY
Figure 4. Programming Procedure
this state, and a succeeding read will show that
the data is still “0”.
Figure 4 illustrates the procedure for the Program
operation.
Chip Erase Command
The Chip Erase command sequence consists of
two unlock cycles, followed by the erase command,
two additional unlock cycles and then the chip erase
data cycle. During chip erase, all sectors of the
device are erased except protected sectors. The
command sequence starts the Automatic Erase algorithm, which preprograms and verifies the entire
memory, except for protected sectors, for an all zero
data pattern prior to electrical erase. The device
then provides the required number of internally
generated erase pulses and verifies cell erasure
within the proper cell margins. The host system is
not required to provide any controls or timings during these operations.
Commands written to the device during execution
of the Automatic Erase algorithm are ignored. Note
that a hardware reset immediately terminates the
erase operation. To ensure data integrity, the
aborted chip erase command sequence should be
reissued once the reset operation is complete.
When the Automatic Erase algorithm is finished,
the device returns to the Read mode. Several
methods are provided to allow the host to deter12
GO TO
ERROR RECOVERY
mine the status of the erase operation, as described in the Write Operation Status section.
Figure 5 illustrates the Chip Erase procedure.
Sector Erase Command
The Sector Erase command sequence consists
of two unlock cycles, followed by the erase command, two additional unlock cycles and then the
sector erase data cycle, which specifies which
sector is to be erased. As described later in this
section, multiple sectors can be specified for erasure with a single command sequence. During
sector erase, all specified sectors are erased sequentially. The data in sectors not specified for
erasure, as well as the data in any protected sectors specified for erasure, is not affected by the
sector erase operation.
The Sector Erase command sequence starts the
Automatic Erase algorithm, which preprograms
and verifies the specified unprotected sectors for
an all zero data pattern prior to electrical erase.
The device then provides the required number of
internally generated erase pulses and verifies cell
erasure within the proper cell margins. The host
system is not required to provide any controls or
timings during these operations.
After the sector erase data cycle (the sixth bus
cycle) of the command sequence is issued, a sector erase time-out of 50 µs (minimum), measured
from the rising edge of the final WE# pulse in that
bus cycle, begins. During this time, an additional
sector erase data cycle, specifying the sector address of another sector to be erased, may be written into an internal sector erase buffer. This buffer
Rev. 4.1/May 01
HY29F002T
may be loaded in any sequence, and the number
of sectors specified may be from one sector to all
sectors. The only restriction is that the time between these additional data cycles must be less
than 50 µs, otherwise erasure may begin before
the last data cycle is accepted. To ensure that all
data cycles are accepted, it is recommended that
host processor interrupts be disabled during the
time that the additional cycles are being issued
and then be re-enabled afterwards.
Note: The device is capable of accepting three ways
of invoking Erase Commands for additional sectors
during the time-out window. The preferred method,
described above, is the sector erase data cycle after
the initial six bus cycle command sequence. However, the device also accepts the following methods
of specifying additional sectors during the sector
erase time-out:
n Repeat the entire six-cycle command sequence, specifying the additional sector in the sixth cycle.
n Repeat the last three cycles of the six-cycle command
sequence, specifying the additional sector in the third
cycle.
If all sectors scheduled for erasing are within protected sectors, the device returns to reading array data after approximately 100 µs. If at least
one selected sector is not protected, the erase
operation erases the unprotected sectors, and ig-
nores the command for the selected sectors that
are protected.
The system can monitor DQ[3] to determine if the
50 µs sector erase time-out has expired, as described in the Write Operation Status section. If
the time between additional sector erase data
cycles can be insured to be less than the timeout, the system need not monitor DQ[3].
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
then rewrite the command sequence, including any
additional sector erase data cycles. Once the
sector erase operation itself has begun, only the
Erase Suspend command is valid. All other commands are ignored.
As for the Chip Erase command, note that a hardware reset immediately terminates the erase operation. To ensure data integrity, the aborted Sector Erase command sequence should be reissued
once the reset operation is complete.
When the Automatic Erase algorithm terminates,
the device returns to the Read mode. Several
methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section.
START
Check Erase Status
(See Write Operation Status
Section)
DQ[5] Error Exit
Normal Exit
Write First Five Cycles of
SECTOR ERASE
Command Sequence
ERASE COMPLETE
GO TO
ERROR RECOVERY
Setup First (or Next) Sector
Address for Erase Operation
Write Last Cycle (SA/0x30)
of SECTOR ERASE
Command Sequence
Sectors which require erasure
but which were not specified in
this erase cycle must be erased
later using a new command
sequence
NO
Erase An
Additional Sector?
YES
Sector Erase
Time-out (DQ[3])
Expired?
YES
NO
Figure 6. Sector Erase Procedure
Rev. 4.1/May 01
13
HY29F002T
Figure 6 illustrates the Sector Erase procedure.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system
to interrupt a sector erase operation to read data
from, or program data in, any sector not being
erased. The command causes the erase operation to be suspended in all sectors selected for
erasure. This command is valid only during the
sector erase operation, including during the 50 µs
time-out period at the end of the initial command
sequence and any subsequent sector erase data
cycles, and is ignored if it is issued during chip
erase or programming operations.
The HY29F002T requires a maximum of 20 µs to
suspend the erase operation if the Erase Suspend
command is issued during active sector erasure.
However, if the command is written during the timeout, the time-out is terminated and the erase operation is suspended immediately. Any subsequent attempts to specify additional sectors for
erasure by writing the sector erase data cycle (SA/
0x30) will be interpreted as the Erase Resume
command (XXX/0x30), which will cause the Automatic Erase algorithm to begin its operation. Note
that any other command during the time-out will
reset the device to the Read mode.
Once the erase operation has been suspended,
the system can read array data from or program
data to any sector not selected for erasure. Normal read and write timings and command definitions apply. Reading at any address within erasesuspended sectors produces status data on
DQ[7:0]. The host can use DQ[7], or DQ[6] and
DQ[2] together, to determine if a sector is actively
erasing or is erase-suspended. See “Write Operation Status” for information on these status bits.
After an erase-suspended program operation is
complete, the host can initiate another programming operation (or read operation) within non-suspended sectors. The host can determine the status of a program operation during the erase-suspended state just as in the standard programming
operation.
The system must write the Erase Resume command to exit the Erase Suspend mode and continue the sector erase operation. Further writes of
the Resume command are ignored. Another Erase
14
Suspend command can be written after the device has resumed erasing.
The host may also write the Electronic ID command sequence when the device is in the Erase
Suspend mode. The device allows reading Electronic ID codes even if the addresses used for the
ID read cycles are within erasing sectors, since
the codes are not stored in the memory array.
When the device exits the Electronic ID mode, the
device reverts to the Erase Suspend mode, and
is ready for another valid operation. See Electronic
ID section for more information.
Electronic ID Command
The Electronic ID operation intended for use in
programming equipment has been described previously. The host processor can also be obtain
the same data by using the Electronic ID command sequence shown in Table 5. This method
does not require VID on any pin. The Electronic ID
command sequence may be invoked while the
device is in the Read mode or the Erase Suspend
mode, but is invalid while the device is actively
programming or erasing.
The Electronic ID command sequence is initiated
by writing two unlock cycles, followed by the Electronic ID command. The device then enters the
Electronic ID mode, and:
n A read cycle at address 0xXXX00 retrieves the
manufacturer code (Hynix = 0xAD).
n A read cycle at address 0xXXX01 returns the
device code (0xB0).
n A read cycle containing a sector address in
A[17:13] and the address 0x02 in A[7:0] returns
0x01 if that sector is protected, or 0x00 if it is
unprotected.
The host system may read at any address any
number of times, without initiating another command sequence. Thus, for example, the host may
determine the protection status for all sectors by
doing successive reads at address 0x02 while
changing the sector address in A[17:13] for each
cycle.
The system must write the Reset command to exit
the Electronic ID mode and return to the Read
mode, or to the Erase Suspend mode if the device was in that mode when the command sequence was issued.
Rev. 4.1/May 01
HY29F002T
Table 6. Write and Erase Operation Status Summary
Mode
Operation
Programming in progress
Normal
Programming completed
1
DQ[6]
DQ[5]
DQ[3]
DQ[2]
DQ[7]#
Toggle
0/1 2
N/A
N/A
4
Data
Data
Data
2
DQ[7]
Data
Data
1
3
1
Toggle
Erase in progress
0
Toggle
0/1
Erase completed
1
Data 4
Data
Data
Data 4
Read within erase suspended sector
1
No toggle
0
N/A
Toggle
Data
Data
Data
Data
Data
DQ[7]#
Toggle
0/1 2
N/A
N/A
Data
Data 4
Data
Data
Data
Read within non-erase suspended sector
Erase
Suspend Programming in progress 5
Programming completed 5
Notes:
1. A valid address is required when reading status information. See text for additional information.
2. DQ[5] status switches to a ‘1’ when a program or erase operation exceeds the maximum timing limit.
3. A ‘1’ during sector erase indicates that the 50 µs timeout has expired and active erasure is in progress.
applicable to the chip erase operation.
4. Equivalent to ‘No Toggle’ because data is obtained in this state.
5. Programming can be done only in a non-suspended sector (a sector not marked for erasure).
DQ[3] is not
WRITE OPERATION STATUS
The HY29F002T provides a number of facilities to
determine the status of a program or erase operation. These are provided through certain bits
of a status word which can be read from the device during the programming and erase operations.
Table 6 summarizes the status indications and
further detail is provided in the subsections which
follow.
DQ[7] - Data# Polling
The Data# (“Data Bar”) Polling bit, DQ[7], indicates
to the host system whether an Automatic Algorithm is in progress or completed, or whether the
device is in Erase Suspend mode. Data# Polling
is valid after the rising edge of the final WE# pulse
in the Program or Erase command sequence.
The system must do a read at the program address to obtain valid programming status information on this bit. While a programming operation is
in progress, the device outputs the complement
of the value programmed to DQ[7]. When the programming operation is complete, the device outputs the value programmed to DQ[7]. If a program operation is attempted within a protected
sector, Data# Polling on DQ[7] is active for approximately 2 µs, then the device returns to reading array data.
The host must read at an address within any nonprotected sector scheduled for erasure to obtain
valid erase status information on DQ[7]. During
Rev. 4.1/May 01
an erase operation, Data# Polling produces a “0”
on DQ[7]. When the erase operation is complete,
or if the device enters the Erase Suspend mode,
Data# Polling produces a “1” on DQ[7]. If all sectors selected for erasing are protected, Data#
Polling on DQ[7] is active for approximately 100
µs, then the device returns to reading array data.
If at least one selected sector is not protected, the
erase operation erases the unprotected sectors,
and ignores the command for the selected sectors that are protected.
When the system detects that DQ[7] has changed
from the complement to true data (or “0” to “1” for
erase), it should do an additional read cycle to read
valid data from DQ[7:0]. This is because DQ[7]
may change asynchronously with respect to the
other data bits while Output Enable (OE#) is asserted low.
Figure 7 illustrates the Data# Polling test algorithm.
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Automatic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be
read at any address, and is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence, including during the sector
erase time-out. The system may use either OE#
or CE# to control the read cycles.
15
HY29F002T
Successive read cycles at any address during an
Automatic Program algorithm operation (including
programming while in Erase Suspend mode)
cause DQ[6] to toggle. DQ[6] stops toggling when
the operation is complete. If a program address
falls within a protected sector, DQ[6] toggles for
approximately 2 µs after the program command
sequence is written, then returns to reading array
data.
While the Automatic Erase algorithm is operating,
successive read cycles at any address cause
DQ[6] to toggle. DQ[6] stops toggling when the
erase operation is complete or when the device is
placed in the Erase Suspend mode. The host may
use DQ[2] to determine which sectors are erasing
or erase-suspended (see below). After an Erase
command sequence is written, if all sectors selected for erasing are protected, DQ[6] toggles for
START
Read DQ[7:0]
at Valid Address (Note 1)
Test for DQ[7] = 1?
for Erase Operation
DQ[7] = Data?
YES
YES
Read DQ[7:0]
at Valid Address (Note 1)
Test for DQ[7] = 1?
for Erase Operation
YES
NO
PROGRAM/ERASE
EXCEEDED TIME ERROR
PROGRAM/ERASE
COMPLETE
Notes:
1. During programming, the program address.
During sector erase, an address within any non-protected sector
scheduled for erasure.
During chip erase, an address within any non-protected sector.
2. Recheck DQ[7] since it may change asynchronously at the same time
as DQ[5].
Figure 7. Data# Polling Test Algorithm
16
Toggle Bit II, DQ[2], when used with DQ[6], indicates whether a particular sector is actively erasing or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the
final WE# pulse in the command sequence. The
device toggles DQ[2] with each OE# or CE# read
cycle.
DQ[2] toggles when the host reads at addresses
within sectors that have been selected for erasure,
but cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ[6], by
comparison, indicates whether the device is actively erasing or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and
mode information.
Figure 8 illustrates the operation of Toggle Bits I
and II.
DQ[5] is set to a ‘1’ when the program or erase
time has exceeded a specified internal pulse count
limit. This is a failure condition that indicates that
the program or erase cycle was not successfully
completed. DQ[5] status is valid only while DQ[7]
or DQ[6] indicate that an Automatic Algorithm is
in progress.
DQ[5] = 1?
DQ[7] = Data?
(Note 2)
DQ[2] - Toggle Bit II
DQ[5] - Exceeded Timing Limits
NO
NO
approximately 100 µs, then returns to reading array data. If at least one selected sector is not
protected, the Automatic Erase algorithm erases
the unprotected sectors, and ignores the selected
sectors that are protected.
The DQ[5] failure condition will also be signaled if
the host tries to program a ‘1’ to a location that is
previously programmed to ‘0’, since only an erase
operation can change a ‘0’ to a ‘1’.
For both of these conditions, the host must issue
a Read/Reset command to return the device to
the Read mode.
DQ[3] - Sector Erase Timer
After writing a Sector Erase command sequence,
the host may read DQ[3] to determine whether or
not an erase operation has begun. When the
sector erase time-out expires and the sector erase
operation commences, DQ[3] switches from a ‘0’
Rev. 4.1/May 01
HY29F002T
START
DQ[5] = 1?
Read DQ[7:0]
at Valid Address (Note 1)
NO
Read DQ[7:0]
YES
Read DQ[7:0]
at Valid Address (Note 1)
YES
DQ[6] Toggled?
NO
(Note 4)
NO
NO
(Note 3)
Read DQ[7:0]
at Valid Address (Note 1)
Read DQ[7:0]
DQ[6] Toggled?
(Note 2)
DQ[2] Toggled?
NO
YES
YES
PROGRAM/ERASE
COMPLETE
PROGRAM/ERASE
EXCEEDED TIME ERROR
SECTOR BEING READ
IS IN ERASE SUSPEND
SECTOR BEING READ
IS NOT IN ERASE SUSPEND
Notes:
1. During programming, the program address.
During sector erase, an address within any sector scheduled for erasure.
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.
3. Use this path if testing for Program/Erase status.
4. Use this path to test whether sector is in Erase Suspend mode.
Figure 8. Toggle Bit I and II Test Algorithm
to a ‘1’. Refer to the “Sector Erase Command”
section for additional information. Note that the
sector erase timer does not apply to the Chip Erase
command.
After the initial Sector Erase command sequence
is issued, the system should read the status on
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to
ensure that the device has accepted the command
sequence, and then read DQ[3]. If DQ[3] is a ‘1’,
the internally controlled erase cycle has begun and
all further sector erase data cycles or commands
(other than Erase Suspend) are ignored until the
erase operation is complete. If DQ[3] is a ‘0’, the
device will accept a sector erase data cycle to mark
an additional sector for erasure. To ensure that
the data cycles have been accepted, the system
software should check the status of DQ[3] prior to
and following each subsequent sector erase data
cycle. If DQ[3] is high on the second status check,
the last data cycle might not have been accepted.
HARDWARE DATA PROTECTION
The HY29F002T provides several methods of protection to prevent accidental erasure or programming which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
These methods are described in the sections that
follow.
Command Sequences
Commands that may alter array data require a
sequence of cycles as described in Table 5. This
provides data protection against inadvertent writes.
Rev. 4.1/May 01
Low VCC Write Inhibit
To protect data during VCC power-up and powerdown, the device does not accept write cycles
when VCC is less than VLKO (typically 3.7 volts). The
command register and all internal program/erase
circuits are disabled, and the device resets to the
Read mode. Writes are ignored until VCC is greater
than VLKO . The system must provide the proper
signals to the control pins to prevent unintentional
writes when VCC is greater than VLKO.
17
HY29F002T
Write Pulse “Glitch” Protection
Power-Up Write Inhibit
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
If WE# = CE# = VIL and OE# = VIH during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to the Read mode on powerup.
Logical Inhibit
Write cycles are inhibited by asserting any one of
the following conditions: OE# = VIL , CE# = VIH, or
WE# = VIH. To initiate a write cycle, CE# and WE#
must be a logical zero while OE# is a logical one.
18
Sector Protection
Additional data protection is provided by the
HY29F002T’s sector protect feature, described
previously, which can be used to protect sensitive
areas of the Flash array from accidental or unauthorized attempts to alter the data.
Rev. 4.1/May 01
HY29F002T
ABSOLUTE MAXIMUM RATINGS 4
Symbol
Value
Unit
TSTG
Storage Temperature
Parameter
-65 to +150
ºC
TBIAS
Ambient Temperature with Power Applied
-55 to +125
ºC
VIN2
Voltage on Pin with Respect to VSS :
VCC 1
A[9], OE#, RESET# 2
All Other Pins 1
-2.0 to +7.0
-2.0 to +12.5
-2.0 to +7.0
V
V
V
I OS
Output Short Circuit Current 3
200
mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to
-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10.
2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET#
may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on these pins is +12.5
V which may overshoot to 13.5 V for periods up to 20 ns.
3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
TA
V CC
1
Parameter
Ambient Operating Temperature:
Operating Supply Voltage:
HY29F002-45 Versions
All Other Versions
Value
Unit
0 to +70
ºC
+4.75 to +5.25
+4.50 to +5.50
V
V
Notes:
1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.
20 ns
20 ns
20 ns
V C C + 2.0 V
0.8 V
- 0.5 V
V C C + 0.5 V
2.0 V
- 2.0 V
20 ns
Figure 9. Maximum Undershoot Waveform
Rev. 4.1/May 01
20 ns
20 ns
Figure 10. Maximum Overshoot Waveform
19
HY29F002T
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Test Setup
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC Max
ILIT
A[9], OE#, RESET# Input
Load Current4
VCC = VCC Max,
A[9] = OE# = 12.5V
RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC Max
ICC1
VCC Active Read Current 1, 3
2, 3, 4
Min
Typ
Max
Unit
±1.0
µA
50
µA
±1.0
µA
CE# = VIL, OE# = VIH
20
30
mA
ICC2
VCC Active Write Current
CE# = VIL, OE# = VIH
30
40
mA
ICC3
VCC CE# Controlled
TTL Standby Current 3
CE# = OE# = VIH
RESET# = VIH
0.4
1.0
mA
ICC4
VCC RESET# Controlled
TTL Standby Current 3
RESET# = VIL
0.4
1.0
mA
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VID
Voltage for Electronic ID and
Temporary Sector Unprotect
VCC = 5.0V
11.5
12.5
V
VOL
Output Low Voltage
VCC = VCC Min,
IOL = 12.0mA
0.45
V
VOH
Output High Voltage
VCC = VCC Min,
IOH = -2.5 mA
VLKO
Low VCC Lockout Voltage 3
2.4
3.2
V
4.2
V
Notes:
1. Includes both the DC Operating Current and the frequency dependent component at 6 MHz. The read component of the
ICC current is typically less than 2 ma/MHz with OE# at VIH.
2. ICC active while Automatic Erase or Automatic Program algorithm is in progress.
3. ICC max measured with VCC = VCC max.
4. Not 100% tested.
20
Rev. 4.1/May 01
HY29F002T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Setup
Min
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC Max
ILIT
A[9], OE#, RESET# Input
Load Current 4
VCC = VCC Max,
A[9] = OE# = 12.5V
RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC Max
ICC1
VCC Active Read Current 1, 3
2, 3, 4
ICC2
VCC Active Write Current
ICC3
VCC CE# Controlled
CMOS Standby Current 3
ICC4
VCC RESET# Controlled
CMOS Standby Current 3
Typ
Max
Unit
±1.0
µA
50
µA
±1.0
µA
CE# = VIL, OE# = VIH
20
30
mA
CE# = VIL, OE# = VIH
30
40
mA
CE# = VCC ± 0.5V
RESET# = VCC ± 0.5V
1
5
µA
1
5
µA
RESET# = VSS ± 0.5V
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VID
Voltage for Electronic ID and
Temporary Sector Unprotect
VCC = 5.0V
11.5
12.5
V
VOL
Output Low Voltage
VCC = VCC Min,
IOL = 12.0ma
0.45
V
VOH
Output High Voltage
VCC = VCC Min,
IOH = -2.5 mA
0.85 x
VCC
V
VCC = VCC Min,
IOH = -100 µA
VCC - 0.4
V
Low VCC Lockout Voltage 3
VLKO
3.2
4.2
V
Notes:
1. Includes both the DC Operating Current and the frequency dependent component at 6 MHz. The read component of the
ICC current is typically less than 2 ma/MHz with OE# at VIH.
2. ICC active while Automatic Erase or Automatic Program algorithm is in progress.
3. ICC max measured with VCC = VCC max.
4. Not 100% tested.
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUT S
OUT PUT S
Steady
Changing from H to L
Changing from L to H
Rev. 4.1/May 01
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Centerline is High Impedance State
(High Z)
21
HY29F002T
TEST CONDITIONS
Table 7. Test Specifications
+ 5V
Test
Condition
2.7
KOhm
DEVICE
UNDER
TEST
CL
Output Load
All diodes
are
1N3064
or
equivalent
6.2
KOhm
- 45
- 55
- 70
- 90
Unit
1 TTL Gate
Output Load Capacitance (CL)
30
100
pF
Input Rise and Fall Times
5
20
ns
Input Signal Low Level
0.0
0.45
V
Input Signal High Level
3.0
2.4
V
Low Timing Measurement
Signal Level
1.5
0.8
V
High Timing Measurement
Signal Level
1.5
2.0
V
Figure 11. Test Setup
3.0 V
Input
1.5 V
1.5 V
Measurement Level
Output
0.0 V
HY29F002T-45, -55 Versions
2.4 V
2.0 V
Input
0.45 V
Measurement
Levels
0.8 V
2.0 V
Output
0.8 V
HY29F002T-70, -90 Versions
Figure 12. Input Waveforms and Measurement Levels
22
Rev. 4.1/May 01
HY29F002T
AC CHARACTERISTICS
Read Operations
Parameter
Description
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
CE# = VIL
OE# = VIL
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
tGLQV
t OE
Output Enable to Output Delay
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
tOEH
Output Enable
Hold Time (Note 1)
t OH
Output Hold Time from Addresses, CE#
or OE#, Whichever Occurs First (Note 1)
tAXQX
Speed Option
Test Setup
CE# = VIL
- 45 - 55
- 70
- 90
Unit
Min
45
55
70
90
ns
Max
45
55
70
90
ns
Max
45
55
70
90
ns
Max
15
15
20
20
ns
Max
25
25
30
35
ns
Max
15
15
20
20
ns
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Min
0
ns
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test conditions.
tR C
Addresses
Addresses Stable
tA C C
CE#
tO E
OE#
tO E H
WE#
Outputs
tD F
tC E
tO H
Output Valid
RESET#
Figure 13. Read Operation Timings
Rev. 4.1/May 01
23
HY29F002T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Speed Option
Test Setup
- 45 - 55
- 70
- 90
Unit
RESET# Pin Low (During Automatic
tREADY Algorithms) to Read or Write (see Note
1)
Max
20
µs
RESET# Pin Low (NOT During Automatic
tREADY Algorithms) to Read or Write (see Note
1)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (see
Note 1)
Min
50
ns
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test conditions.
CE#, OE#
tR H
RESET#
tR P
tR E A D Y
Reset Timings NOT During Automatic Algorithms
tR E A D Y
CE#, OE#
RESET#
tR P
tR H
Reset Timings During Automatic Algorithms
Figure 14. RESET# Timings
24
Rev. 4.1/May 01
HY29F002T
AC CHARACTERISTICS
Program and Erase Operations
Parameter
Speed Option
Description
JEDEC
Std
- 45 - 55
tAVAV
t WC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
45
- 70
- 90
70
90
55
0
Unit
ns
ns
tWLAX
tAH
Address Hold Time
Min
40
45
45
45
ns
tDVWH
tDS
Data Setup Time
Min
25
25
30
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
Min
0
ns
tGHWL
tGHWL Read Recovery Time Before Write
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
t WP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
20
ns
Typ
7
µs
Max
300
µs
Typ
1.8
sec
Max
5.4
sec
Typ
1
sec
tWHWH1
tWHWH1 Byte Programming Operation (Notes 1, 2, 3)
Chip Programming Operation (Notes 1, 2, 3, 5)
tWHWH2
tWHWH3
tWHWH2 Sector Erase Operation (Notes 1, 2, 4)
tWHWH3 Chip Erase Operation (Notes 1, 2, 4)
Erase and Program Cycle Endurance
tVCS
VCC Setup Time
30
30
35
45
ns
Max
8
sec
Typ
7
sec
Max
55
sec
Typ
1,000,000
cycles
Min
100,000
cycles
Min
50
µs
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 °C, VCC = 5.0 volts, 100,000 cycles. In addition,
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 °C, VCC = 4.5 volts (4.75 volts for 45 ns version), 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program
command. See Table 5 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum
byte program time specified is exceeded. See Write Operation Status section for additional information.
Rev. 4.1/May 01
25
HY29F002T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tW C
Addresses
tA S
0x555
Read Status Data (last two cycles)
tA H
PA
PA
PA
CE#
tG H W L
OE#
tC H
tW P
WE#
tC S
tW P H
Data
0xA0
tW H W H 1
PD
Status
D OUT
tD S
tD H
V CC
tV C S
Notes:
1. PA = Program Address, PD = Program Data, DOUT is the true data at the program address.
2. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 15. Program Operation Timings
26
Rev. 4.1/May 01
HY29F002T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tW C
Addresses
tA S
0x2AA
Read Status Data (last two cycles)
tA H
SA
VA
VA
0x555 for chip erase
CE#
tG H W L
OE#
tC H
tW P
WE#
tC S
tW P H
Data
0x55
0x30
0x10 for
chip erase
t W H W H 2 or t W H W H 3
Status
D OUT
tD S
tD H
V CC
tV C S
Notes:
1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section),
DOUT is the true data at the read address.(0xFF after an erase operation).
2. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 16. Sector/Chip Erase Operation Timings
Rev. 4.1/May 01
27
HY29F002T
AC CHARACTERISTICS
tR C
VA
Addresses
VA
VA
tA C C
tC H
tC E
CE#
tO E
OE#
tD F
tO E H
WE#
tO H
DQ[7]
Complement
DQ[6:0]
Status Data
Complement
Status Data
True
Valid Data
True
Valid Data
Notes:
1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section).
2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.
Figure 17. Data# Polling Timings (During Automatic Algorithms)
tR C
VA
Addresses
VA
VA
VA
Valid Data
tA C C
tC H
tC E
CE#
tO E
OE#
tO E H
WE#
DQ[6], [2]
tD F
tO H
Valid Status
Valid Status
Valid Status
(first read)
(second read)
(stops toggling)
Notes:
1. VA = Valid Address for reading Toggle Bits (DQ[2], DQ[6]) status data (see Write Operation Status section).
2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.
Figure 18. Toggle Polling Timings (During Automatic Algorithms)
28
Rev. 4.1/May 01
HY29F002T
AC CHARACTERISTICS
Enter
Automatic
Erase
WE#
Erase
Suspend
Erase
Enter Erase
Suspend
Program
Erase
Suspend
Read
Erase
Resume
Erase
Suspend
Program
Erase
Suspend
Read
Erase
Erase
Complete
DQ[6]
DQ[2]
Notes:
1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an
erase-suspended sector.
Figure 19. DQ[2] and DQ[6] Operation
Sector Protect and Unprotect, Temporary Sector Unprotect
Parameter
JEDEC
Speed Option
Description
Std
- 45 - 55
- 70
- 90
Unit
tST
Voltage Setup Time
Min
50
µs
tRSP
RESET# Setup Time for
Temporary Sector Group Unprotect
Min
4
µs
tCE
Chip Enable to Output Delay
Max
45
55
70
90
ns
t OE
Output Enable to Output Delay
Max
25
25
30
35
ns
tVIDR
Voltage Transition Time for
Temporary Sector Group Unprotect (Note 1)
Min
500
ns
tVLHT
Voltage Transition Time for
Sector Group Protect and Unprotect (Note 1)
Min
4
µs
tWPP1
Write Pulse Width for Sector Group Protect
Min
100
µs
tWPP2
Write Pulse Width for Sector Group Unprotect
Min
100
ms
tOESP
OE# Setup Time to WE# Active (Note 1)
Min
4
µs
tCSP
CE# Setup Time to WE# Active (Note 1)
Min
4
µs
Notes:
1. Not 100% tested.
Rev. 4.1/May 01
29
HY29F002T
AC CHARACTERISTICS
Sector Protect Cycle
A[17:13]
Protect Verify Cycle
SA X
SA Y
A[0]
A[1]
A[6]
t
V ID V L H T
A[9]
tV L H T
tS T
tV L H T
V ID
OE#
tO E S P
tV L H T
tW P P 1
tS T
WE#
tO E
CE#
Data
0x01
RESET#
tS T
tS T
V CC
Figure 20. Sector Protect Timings
30
Rev. 4.1/May 01
HY29F002T
AC CHARACTERISTICS
Sector Unprotect Cycle
Unprotect Verify Cycle
SA 0
A[17:13]
SA 1
A[0]
A[1]
A[6]
V ID
A[9]
tV L H T
tS T
tV L H T
V ID
tS T
OE#
tO E
tO E S P
V ID
CE#
tC S P
tW P P 2
tC E
WE#
Data
0x00
RESET#
V CC
tS T
Figure 21. Sector Unprotect Timings
Rev. 4.1/May 01
31
HY29F002T
AC CHARACTERISTICS
V ID
RESET#
0 or 5V
0 or 5V
t VIDR
t VIDR
CE#
WE#
tR S P
Figure 22. Temporary Sector Unprotect Timings
32
Rev. 4.1/May 01
HY29F002T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Std
tAVAV
t WC
Speed Option
Description
Write Cycle Time (Note 1)
- 45 - 55
Min
45
55
- 70
- 90
70
90
Unit
ns
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
40
45
45
45
ns
tDVWH
tDS
Data Setup Time
Min
25
25
30
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
Min
0
ns
tWLEL
t WS
WE# Setup Time
Min
0
ns
tEHWH
t WH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
tWHWH1
tWHWH1 Byte Programming Operation (Notes 1, 2, 3)
Chip Programming Operation (Notes 1, 2, 3, 5)
tWHWH2
tWHWH2 Sector Erase Operation (Notes 1, 2, 4)
tWHWH3
tWHWH3 Chip Erase Operation (Notes 1, 2, 4)
Erase and Program Cycle Endurance
30
30
35
45
ns
20
ns
Typ
7
µs
Max
300
µs
Typ
1.8
sec
Max
5.4
sec
Typ
1
sec
Max
8
sec
Typ
7
sec
Max
55
sec
Typ
1,000,000
cycles
Min
100,000
cycles
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 °C, VCC = 5.0 volts, 100,000 cycles. In addition,
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 °C, VCC = 4.5 volts (4.75 volts for 55 ns version), 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program
command. See Table 5 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum
byte program time specified is exceeded. See Write Operation Status section for additional information.
Rev. 4.1/May 01
33
HY29F002T
AC CHARACTERISTICS
0x555 for Program
0x2AA for Erase
PA for Program
SA for Sector Erase
0x555 for Chip Erase
Addresses
VA
tW C
tA S
tA H
WE#
tG H E L
tW H
OE#
tC P
tW S
tC P H
t W H W H 1 or t W H W H 2 or t W H W H 3
CE#
tD S
tD H
Data
Status
tR H
0xA0 for Program
0x55 for Erase
D OUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
RESET#
Notes:
1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write
Operation Status section), DOUT = array data read at VA.
2.
Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle.
3.
Word mode addressing shown.
4.
RESET# shown only to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
Figure 23. Alternate CE# Controlled Write Operation Timings
34
Rev. 4.1/May 01
HY29F002T
Latchup Characteristics
Description
Minimum
Maximum
Unit
Input voltage with respect to VSS on all pins except I/O pins
(including A[9], OE# and RESET#)
-1.0
12.5
V
Input voltage with respect to VSS on all I/O pins
- 1.0
VCC + 1.0
V
VCC Current
- 100
100
mA
Notes:
1. Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
TSOP Pin Capacitance
Symbol
CIN
Parameter
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
Typ
Max
Unit
VIN = 0
6
7.5
pF
VOUT = 0
8.5
12
pF
VIN = 0
7.5
9
pF
Test Setup
Typ
Max
Unit
VIN = 0
4
6
pF
VOUT = 0
8
12
pF
VIN = 0
8
10
pF
Minimum
Unit
Notes:
1. Sampled, not 100% tested.
2. Test conditions: TA = 25 ºC, f = 1.0 MHz.
PLCC and PDIP Pin Capacitance
Symbol
CIN
Parameter
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions: TA = 25 ºC, f = 1.0 MHz.
Data Retention
Parameter
Minimum Pattern Data Retention Time
Rev. 4.1/May 01
Test Conditions
150 ºC
10
Years
125 ºC
20
Years
35
HY29F002T
PACKAGE DRAWINGS
Physical Dimensions
TSOP32 - 32-pin Thin Small Outline Package (measurements in millimeters)
0.95
1.05
Pin 1 I.D.
1
32
7.90
8.10
16
0.50 BSC
17
0.05
0.15
18.30
18.50
19.80
20.20
0.08
0.20
1.20
MAX
0.10
0.21
o
0
o
5
0.25MM (0.0098") BSC
.015
.060
PLCC32 - 32-pin Plastic Leaded Chip Carrier (measurements in inches)
.485
.495
.585 .547
.595 .553
.447
.453
.009
.015
Pin 1
I.D.
SEATING
PLANE
.050 REF.
.026
.032
.125
.140 .080
.095
.400
REF
.013
.021
.490
.530
TOP VIEW
36
.042
.056
SIDE VIEW
Rev. 4.1/May 01
HY29F002T
ORDERING INFORMATION
Hynix products are available in several speeds, packages and operating temperature ranges. The
ordering part number is formed by combining a number of fields, as indicated below. Refer to the ‘Valid
Combinations’ table, which lists the configurations that are planned to be supported in volume. Please
contact your local Hynix representative or distributor to confirm current availability of specific configurations and to determine if additional configurations have been released.
HY29F002 X
X
-
X
X
X
SPECIAL INSTRUCTIONS
TEMPERATURE RANGE
Blank = Commercial ( 0 to +70 °C)
SPEED OPTION
45
55
70
90
=
=
=
=
45 ns
55 ns
70 ns
90 ns
PACKAGE TYPE
C = 32-Pin Plastic Leaded Chip Carrier (PLCC)
T = 32-Pin Thin Small Outline Package (TSOP)
BOOT BLOCK LOCATION
T= Top Boot Block
DEVICE NUMBER
HY29F002 = 2 Megabit (256K x 8) CMOS 5 Volt-Only Sector
Erase Flash Memory
VALID COMBINATIONS
P ackag e an d S p eed
TSOP
P LC C
Temperature
45 n s
55 n s
70 n s
90 n s
45 n s
55 n s
70 n s
90 n s
Commercial
T-45
T-55
T-70
T-90
C-45
C-55
C-70
C-90
Note:
1. The complete part number is formed by appending the Boot Block Location code and the suffix shown in the table above
to the Device Number. For example, the part number for a 90 ns, Commercial temperature range device in the TSOP
package with the top boot block is HY29F002TT-90.
Rev. 4.1/May 01
37
HY29F002T
Important Notice
© 2001 by Hynix Semiconductor America. All rights reserved.
No part of this document may be copied or reproduced in any
form or by any means without the prior written consent of Hynix
Semiconductor Inc. or Hynix Semiconductor America (collectively “Hynix”).
tions of Sale only. Hynix makes no warranty, express, statutory, implied or by description, regarding the information set
forth herein or regarding the freedom of the described devices
from intellectual property infringement. Hynix makes no warranty of merchantability or fitness for any purpose.
The information in this document is subject to change without
notice. Hynix shall not be responsible for any errors that may
appear in this document and makes no commitment to update
or keep current the information contained in this document.
Hynix advises its customers to obtain the latest version of the
device specification to verify, before placing orders, that the
information being relied upon by the customer is current.
Hynix’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed
between the customer and Hynix prior to use. Life support
devices or systems are those which are intended for surgical
implantation into the body, or which sustain life whose failure to
perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to
result in significant injury to the user.
Devices sold by Hynix are covered by warranty and patent indemnification provisions appearing in Hynix Terms and Condi-
Revision Record
Rev.
Date
4.1
5/01
Details
Change to Hynix format.
Removed bottom boot block option and PDIP package option
Memory Sales and Marketing Division
Hynix Semiconductor Inc.
10 Fl., Hynix Youngdong Building
89, Daechi-dong
Kangnam-gu
Seoul, Korea
Telephone: +82-2-580-5000
Fax: +82-2-3459-3990
Flash Memory Business Unit
Hynix Semiconductor America Inc.
3101 North First Street
San Jose, CA 95134
USA
Telephone: (408) 232-8800
Fax: (408) 232-8805
http://www.us.hynix.com
http://www.hynix.com
38
Rev. 4.1/May 01