ETC MTD655

MYSON
TECHNOLOGY
MTD655
5 Port 10M/100M Hub With 2 port Switch
FEATURES
GENERAL DESCRIPTION
• IEEE802.3 Clause 9 and IEEE802.3u Cluse 27
compliant.
• Provide 4 RMII (Reduced Media Independent
Interface) ports and 1 MII port.
• Provide 2 inter_repeater stacking bus for 10M
and 100M port expansion each.
• Support stacking to 4 units without any external
arbitration logic ( if use external arbitration
logic, theoretically can stack to 6 units and up) .
• Build_in 2 port switch controller, support up to
2048 MAC addresses filtering database.
• Optional back_pressure flow control
• Optional up_link_switch port function (in slave
hub), support 100FX 2km distance extension in
100FD mode.
• Meet Class_2 repeater specification for
100M_hub.
• Use simple and low cost asynchronous SRAM
(high speed ASRAM 128k*8 : one pcs only)
• 128 pin PQFP package, 5V operation voltage.
The MTD655 is a highly integrated, 10M/
100M dual speed hub with build_in 2 port switch.
Support 4 RMII ports and 1 MII port for 10M/
100M operation, and meet 100M_hub class_2
spec when connect with external PHYceivers.
The MTD655 provides two Inter-repeater
stacking bus for 10M and 100M expansion each,
easily stack to 4 units without any external arbitration logic. If using external arbitration logic and
proper bus driver, can stack to 6 units and up.
The build_in 2 port switch, support 2k MAC
addresses filtering, and use low cost asynchronous high speed SRAM (128k*8) one pcs only for
packet buffering. This 2 port switch can also be
configured to be up_link switch when hub is
under slave mode.
The MTD655 also support an simple and
effective LED display function, provide 10M_col,
100M_col, memory_test_fail, and per port’s partition status.
BLOCK DIAGRAM
ASRAM Interface
Two Port
Switch
Uplink Switch Enable(10/100,FD/HD)
RMII4
10M_HD
10M
Inter Hub Bus
RMII3
RMII2
10M
Hub
RMII1
100M_HD
100M
Inter Hub Bus
Port
Switch
Logic
MII0
100M
Hub
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of
the product.
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MYSON
TECHNOLOGY
MTD655
SYSTEM DIAGRAM
DB25 Connector
10M
Inter Hub Bus
MTD655
100M
Inter Hub Bus
10M
Inter Hub Bus
MTD655
100M
Inter Hub Bus
10M
Inter Hub Bus
MTD655
100M
Inter Hub Bus
10M
Inter Hub Bus
ASRAM
(128kx8)
MTD655
100M
Inter Hub Bus
MII0
PHYsceiver
RMII1-4
QUAD
PHYsceiver
Transformer
RJ45
QUAD
Transformer
RJ45
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of
the product.
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111
112
113
114
115
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119
120
121
122
123
124
125
126
127
128
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
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18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VCC
A4
GND
OEB
A3
A10
A2
A1
D7
A0
D6
D0
D5
D1
GND
D4
D2
D3
VCC
SYSCLK
GND
LEDDAT
LEDCLK
MDC
MDIO
RSTB
GND
NC
VCC
NC
NC
GND
GND
SPD0
TXD0_3
TXD0_2
NC
TXCLK0
GND
GND
RXCLK0
TXD0_1
TXD0_0
TXEN0
RXD0_0
RXD0_1
GND
NC
NC
NC
GND
GND
RXD0_2
RXD0_3
RXDV0
CRS0
VCC
GND
CRSDV1
TXD1_1
TXD1_0
TXEN1
RXD1_0
RXD1_1
102
101
100
99
98
97
96
95
94
93
92
91
90
89
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83
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74
73
72
71
70
69
68
67
66
65
A11
A5
A9
A6
A8
A7
A13
A12
WEB
A14
GND
A15
A16
IREQ10_OUT
IREQ10_IN0
IREQ10_IN1
IREQ10_IN2
ICOLB10
IACKB10
ICLK10
GND
IDAT10
IREQ100_OUT
IREQ100_IN0
IREQ100_IN1
IREQ100_IN2
ICOLB100
IACKB100
GND
ICLK100
VCC
IDAT100_0
IDAT100_1
IDAT100_2
IDAT100_3
IMASTER
FD4
UPSWEN
MYSON
TECHNOLOGY
MTD655
1.0 PIN CONNECTION
MTD655
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59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
SPD1
SPD2
SPD3
SPD4
GND
VCC
RXD4_1
RXD4_0
TXEN4
TXD4_0
TXD4_1
CRSDV4
RXD3_1
RXD3_0
TXEN3
TXD3_0
TXD3_1
CRSDV3
GND
VCC
RXD2_1
RXD2_0
TXEN2
TXD2_0
TXD2_1
CRSDV2
MTD655 Revision 2.0 17/03/2000
MYSON
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MTD655
1.0 PIN DESCRIPTIONS
MII Port Interface Pins (port0)
Name
RXD0_0
RXD0_1
RXD0_2
RXD0_3
CRS0
Pin Number
19
20
27
28
I/O
Descriptions
I Port0 MII receive data bit_0.
I
Port0 MII receive data bit_1.
I
Port0 MII receive data bit_2.
Port0 MII receive data bit_3.
Port0 MII asynchronous carrier indicator from PHY device.
30
I
I
RXDV0
29
I
Port0 MII synchronous receive data valid signal from PHY device.
RXCLK0
15
I
Port0 MII receive clock.
TXEN0
18
O
Port0 MII transmit enable signal.
17
16
10
9
O
Port0 MII transmit data bit_0.
O
Port0 MII transmit data bit_1.
O
Port0 MII transmit data bit_2.
O
I
Port0 MII transmit data bit_3.
Port0 MII transmit clock.
TXD0_0
TXD0_1
TXD0_2
TXD0_3
TXCLK0
12
RMII Port Interface Pins (port1 ~port4)
Name
CRSDV1
RXD1_0
RXD1_1
TXEN1
TXD1_0
TXD1_1
CRSDV2
RXD2_0
RXD2_1
TXEN2
TXD2_0
TXD2_1
CRSDV3
RXD3_0
RXD3_1
TXEN3
TXD3_0
TXD3_1
CRSDV4
Pin Number
33
37
38
36
35
34
39
43
44
42
41
40
47
51
52
50
49
48
53
I/O
Descriptions
I Port1 RMII receive interface signal, CRSDV1 is asserted high when
I
port1 media is non_idle.
Port1 RMII receive data bit_0.
I
O
Port1 RMII receive data bit_1.
Port1 RMII transmit enable signal.
O
Port1 RMII transmit data bit_0.
O
I
I
Port1 RMII transmit data bit_1.
Port2 RMII receive interface signal, CRSDV2 is asserted high when
port2 media is non_idle.
Port2 RMII receive data bit_0.
I
O
Port2 RMII receive data bit_1.
Port2 RMII transmit enable signal.
O
Port2 RMII transmit data bit_0.
O
I
I
Port2 RMII transmit data bit_1.
Port3 RMII receive interface signal, CRSDV3 is asserted high when
port3 media is non_idle.
Port3 RMII receive data bit_0.
I
O
Port3 RMII receive data bit_1.
Port3 RMII transmit enable signal.
O
Port3 RMII transmit data bit_0.
O
I
Port3 RMII transmit data bit_1.
Port4 RMII receive interface signal, CRSDV4 is asserted high when
port4 media is non_idle.
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RMII Port Interface Pins (port1 ~port4)
Name
RXD4_0
RXD4_1
TXEN4
TXD4_0
TXD4_1
Pin Number
57
58
56
55
54
I/O
Descriptions
I Port4 RMII receive data bit_0.
I
O
Port4 RMII receive data bit_1.
Port4 RMII transmit enable signal.
O
Port4 RMII transmit data bit_0.
O
Port4 RMII transmit data bit_1.
High Speed Asynchronous SRAM Interface Pins
Name
WEB
OEB
D[7:0]
A[16:0]
Pin Number
94
106
111,113,115,
118,120,119,
116,114
90,91,93,96,
95,102,108,
I/O
Descriptions
O ASRAM control pin for write (low active).
O ASRAM control pin for read (low active).
I/O ASRAM data bus
O
ASRAM address bus
100,98,97,99
,101,104,107
,109,110,112
Note: Asynchronous SRAM acess time: 10/12 ns (max)
10M Inter-Bus Interface pins
Name
IMASTER
Pin Number
67
IACKB10
84
ICOLB10
85
IREQ10_IN0
IREQ10_IN1
IREQ10_IN2
IREQ10_OUT
88
87
86
89
I/O
I
Descriptions
Master hub selection:
when high: means hub internal inter_bus arbiter is enabled and hub
internal two_port switch is well conneted to 10M_hub core and
100M_hub core .
when low: means hub internal inter_bus arbiter is disabled and hub
internal two_port switch is not connected to 10M_hub core and
100M_hub core.
I/O 10M Inter-Bus port access acknowledge signal (low active). For master
hub, this pin is output; for slave hub is input, or while EXT_ARB
jumper was set to “1”, this pin is input from an external arbitration
device.
I/O 10M Inter-Bus collision signal (low active). For master hub, this pin can
output multi hub collision event to inform all slave hub ; for slave hub,
this pin is an input, or while EXT_ARB jumper was set to “1”, this pin
is input from an external arbitration device.
I 10M Inter-Bus port access request input.
I 10M Inter-Bus port access request input.
I 10M Inter-Bus port access request input.
O 10M Inter-Bus port access request output.
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10M Inter-Bus Interface pins
Name
ICLK10
IDAT10
Pin Number
83
81
I/O
Descriptions
I/O 10M Inter-Bus port clock.
I/O 10M Inter-Bus port data bit
100M Inter-Bus Interface pins
Name
IACKB100
Pin Number
75
ICOLB100
76
IREQ100_IN0
IREQ100_IN1
IREQ100_IN2
IREQ100_OUT
ICLK100
IDAT100_0
IDAT100_1
IDAT100_2
IDAT100_3
79
78
77
80
73
71
70
69
68
I/O
Descriptions
I/O 100M Inter-Bus port access acknowledge signal (low active). For master
hub, this pin is output; for slave hub is input, or while EXT_ARB
jumper was set to “1”, this pin is input from an external arbitration
device.
I/O 100M Inter-Bus collision signal (low active). For master hub, this pin
can output multi hub collision event to inform all slave hub ; for slave
hub, this pin is an input, or while EXT_ARB jumper was set to “1”, this
pin is input from an external arbitration device.
I 100M Inter-Bus port access request input.
I 100M Inter-Bus port access request input.
I 100M Inter-Bus port access request input.
O 100M Inter-Bus port access request output.
I/O 100M Inter-Bus port clock.
I/O 100M Inter-Bus port data bit 0.
I/O 100M Inter-Bus port data bit 1.
I/O 100M Inter-Bus port data bit 2.
I/O 100M Inter-Bus port data bit 3.
LED Interface Pins
Name
LEDDAT
Pin Number
I/O
I/O
124
LEDCLK
I/O
125
Descriptions
LED display serial data out; mapping for LEDCLK signal’s burst clock
, its serial out data sequence is : ( first bit be shifted out is from b00, and
end of burst bit is b23)
b00: ***********
b08: 10hub_col
b16: ************
b01: **********
b09: 100hub_col
b17: ************
b02: **********
b10: asram_test_fail
b18: ************
b03: port0 partition
b11: port0 partition
b19: port0 rx_activity
b04: port1 partition
b12: port1 partition
b20: port1 rx_activity
b05: port2 partition
b13: port2 partition
b21: port2 rx_activity
b06: port3 partition
b14: port3 partition
b22: port3 rx_activity
b07: port4 partition
b15: port4 partition
b23: port4 rx_activity
LED display clock signal, the signal is a discontinued clock for LED
data serial shift out. Every clock burst have 24 cycles ( period : 160 ns),
and the clock burst will be repeated with every 42ms.
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Miscellaneous Pins
Name
RSTB
SYSCLK
MDC
MDIO
UPSWEN
Pin Number
128
122
126
127
I/O
I
I
I/O
I/O
I
I
Descriptions
System reset input, low active.
50MHz system clock input
MII management clock inout
MII management data inout
Up_link switch port enabling : one of internal two_port switch port will
connect to 100M_hub domain, and another port will redirect to RMII
port4.
When up_link switch port enabling, this pin is port4’s full_deplex indicator, input from PHY. When hign , indicate port4 in running on
full_duplex mode. When low, indicate on half_duplex mode.
Port0 speed indicator, input from PHY.
I
SPD0 input low: 100M , input high: 10M.
Port1 speed indicator, input from PHY.
I
SPD1 input low: 100M , input high: 10M.
Port2 speed indicator, input from PHY.
I
SPD2 input low: 100M , input high: 10M.
Port3 speed indicator, input from PHY.
I
SPD3 input low: 100M , input high: 10M.
Port4 speed indicator, input from PHY.
65
FD4
I
66
SPD0
SPD1
SPD2
SPD3
SPD4
8
64
63
62
61
SPD4 input low: 100M , input high: 10M.
NC No connection pins
NC_pin
2,4,5,11,22,
VCC
23,24
3,31,45,59, PWR Power pins
GND
72,103,121
1,6,7,13,14, GND Ground pins
21,25,26,32,
46,60,74,82,
92,105,117,
123
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Power On Configuration Set Up Table
Name
NC_11
Pin Number
I/O
Descriptions
I/O Port0 MII interface enable : ( power on external jumper configuration )
- pin floating : Port0 MII interface disable (change to be RMII interface)
11
, not suit for 5 ports daul speed hub application.
- external pull_high: Port0 MII interface enable.
I/O Back_pressure disable : ( power on external jumper configuration )
TXEN0
18
- external pull_low (default ) : normal mode (back_pressure enbale)
- external pull_high: back_pressure disable
I/O Auto MII_setting bypass : ( power on external jumper configuration )
TXEN2
- external pull_low (default ) : normal mode ( auto MII_setting); after
42
power_on, MTD655 will auto setup PHY devices be forced in half_
duplex mode for repeater apllication.
- external pull_high: auto MII_setting bypass
I/O 1522 bytes packet accept enable : ( power on external jumper configuration )
MDC
126
LEDCLK
- external pull_low (default ) : normal mode ( <=1518 bytes packet
accept)
I/O
125
- external pull_high: <= 1522 bytes packet accept
Hub dealy enhance : ( power on external jumper configuration )
- external pull_low (default ) : nomal hub propagation delay mode.
- external pull_high: enhanced hub propagational delay mode, for covering long latency PHY devices).
I/O External arbiter enable : ( power on external jumper configuration )
LEDDAT
124
- external pull_low (default ) : normal mode (inter_repeater bus use
internal arbiter)
- external pull_high: inter_repeater bus use external arbiter .
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2.0 MTD655 FUNCTIONAL DESCRIPTIONS
The MTD655 is conformed to IEEE802.3 chapter 9 and IEEE802.3u clause 27 specifications. The
MTD655 provides 4 Redused MII interfaces, 1 MII interface and an embedded two port switch to construct a 10M/100M dual speed Hub application. Two Inter-Bus are also provided for stackable 10M/
100M dual speed Hub application. The MTD655 functions are described as followmtd655s:
2.1 Repeat and data handling
4 independent RMII ports and 1 MII port integrated with IEEE802.3 chapter 9 and IEEE802.3u clause
27 repeater functions simultaneously. MTD655 embedded two Hub cores (10M and 100M) ,and each
dedicated RMII or MII interface port can get per port’s speed information from per port speed input pin,
and then MTD655 will switch individual port to their appropriated Hub core functions (10M or 100M).
The MTD655 receive packets from each RMII and MII ports, and redirect port’s input packet to 10M or
100M Hub core according each port’s speed. The internal IEEE802.3 chapter 9 or IEEE802.3u clause
27 repeater main state machine will starts to repeat the input packet to all ports except the input port. If
larger than or equal to two ports have input packet simultaneously, this will be treated as a collision, and
MTD655 will assert an arbitrary JAM pattern to all ports’output until collision event disappear and network is idle.
2.2 Partition
The MTD655 provides 10M/100M auto partition/reconnection functions to guarantee the network segment performance by means of dectecting a consecutive collisions. Each dedicated RMII or MII port
has implement a individual 10M/100M auto partition/reconnection state machine. If port’s consecutive
collision number over or equal to CClimit (10M CClimit default is 32, 100M CClimit default is 64), this
port will be partitioned. Reconnection will occurs after a larger than 512 bit time packet was received or
transmitted from this partitioned port without any collision.
When port is under partition state, MTD655 will not accept any input messages from this port (just monitor input message), but will continue output repeated messages to this partition port.
Some new partition criterions are also implement, such as long_collision_partition event,
jabber_partition event. In 10M/100M partition state machine, longer than 1024 bit time continueous collision will force port enter partition state. In 100M partition state machine, if port enter jabber_on state,
this port will be partitioned. In 10M, jabber_partition function is not implemented.
2.3 Jabber
The jabber protect function is used to prevent an illegally long packet reception. After the MTD655
received a longer than 65536 +/- 6.25% bit times packet, this receive port‘s receive/transmit path will be
inhibited until carrier is no longer detected.
2.4 MII Setting
Due to HUB is an half duplex device, the MTD655 need to force all connected phsical devices to work
in half duplex environment. The MTD655 will setting all PHY’s SMI register 4’s half/full duplex bit during
power on, and than restart auto-negotiation procedure to work in half duplex mode, and the PHY’s
device ID should be set by PCB maker from 5’h07 - 5’h0b(port0-4).
2.5 Inter-Bus Interface
Two Inter-Bus Interface are provided by the MTD655, One is 10M Inter-Bus Interface, the other is 100M
Inter-Bus Interface. The Inter-Bus interface is designed for stackable hub application. For each domain,
up to 4 MTD655s can be stacked through this Inter-Bus without any external arbitration logic. The InterBus Interface includes IMASTER, IDATA (100M: use IDAT<3:0>, 10M: use only IDAT), REQOUT,
REQIN0-2, ICLK, IACKB, ICOLB pins. IMASTER decide which MTD655 can arbitrate the Inter-Bus,
and only one MTD655’s IMASTER can be tie high in a stackable Hub. IDATA are synchronous with
ICLK. The MTD655 output REQOUT to inform Inter-Bus Interface that it need the Inter-Bus right. When
IACKB is asserted by Inter-Bus master after REQOUT asserted, the MTD655 which asserted
REQOUT will get the bus right and put the transmit data into IDATA. If the MTD655 did not assert
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REQOUT , but IACKB is asserted, means this MTD655 can get data from IDATA bus. When only one
MTD655 output REQOUT to Inter-Bus Interface, IACKB will be asserted by Inter-Bus master device, If
larger than two MTD655’s REQOUT were asserted, Inter-Bus master will not assert IACKB , but will
assert ICOLB to inform all the connected MTD655s.
The Inter-Bus interface can also be programmed to EXT_ARB mode, using LEDDAT pin’s jumper setting. In this mode, Inter-Bus interface need an external arbitration logic to arbitrate Inter-Bus operation.
And in this mode, the stackable capability is not limitted by the MTD655’s REQIN pins number.
2.6 10M/100M packet Switch
The MTD655 inplements a 10/100M two port switch for 10M/100M packet switching. Total 2K address
entrys are provided for packets’SA learning and DA routing; and alsoprovide automatic aging function
( aging time = 300secs). The input packet from 10MHub ( or 100M Hub) will be stored to external
memory first, while packet is good for forward ( CRC chech ok, 64Bytes < length > 1518Bytes, and not
local packets ) , than forward this packet to 100M Hub (or 10M Hub).
2.7 Uplink Switch Port
The MTD655 can config one switch port as an uplink switch port. When UPSWEN pin is high, and
IMASTER pin is low, one of the intenal switch port is connect to 100M HUB, the other is connected to
RMII port 4. In uplink switch mode, port 4 can work in 10M/100M(from SPD4 pin), half/full duplex(from
FD4 pin) mode.
2.8 Memory Interface
The MTD655 use asynchronous SRAM as two port switchs’packet buffers, total has 128K byte external memory for packet buffering.
2.9 MII management
The MTD655 can be managed through MDC, MDIO pins. The MTD655 implements 3 MII registers for
function control and status report (see Section 4.0 on page ).
The management frame format is compliant to IEEE802.3u clause 22, and the device ID is fixed to
5’h1f internally.
2.10 LED display
The MTD655 implements three display modes, port RX activity, 10/100M domain collision, port partition. The LED data pin LEDDAT is high actived.
One strobe pin LEDCLK(24 burst clock/per 42ms) is used to latch serial LEDDAT information, and user
can shift the latched data into byte aligned shift register to drive LEDs.
3.0 Registers
The MTD655 implements 3 MII registers, define as following tables:
TABLE 1. MII r egister s
REG
NO
0
Bits
0
1
2
3
4
5-8
9
Name
R/W
Descriptions
CtlReg0
R/W
CONTROL REGISTER 0
DisPar10
DisPar100
DisJab10
DisJab100
CClimit100
Default
Reserved.
1’b0
Set this bit will disable 10M hub core partition function.
1’b0
Set this bit will disable 100M hub core partition function.
1’b0
Set this bit will disable 10M hub core Jabber function.
1’b0
Set this bit will disable 100M hub core Jabber function.
1’b0
Reserved
4’b000
Set "1" will program 100M partition cclimit to 128.
1’b0(64)
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TABLE 1. MII r egister s
REG
NO
Bits
Name
10
11-15
CClimit10
1
0-7
8-15
2
3
4
CtlReg1
DisPort
AgeReg
R/W
Descriptions
Default
Set "1" will program 10M partition cclimit to 64.
Reserved
R/W
CONTROL REGISTER 1
Set bits "1" disable port 0-7 RMII ports.
Reserved.
Reserved
Reserved
R/W
AGE REGISTER
1’b0(32)
2’b00
16’h0000
8’h000
"R/W" means read/writable.
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4.0 Electrical Characteristics
4.1 Absolute Maximum Ratings
Symbol
Parameter
VCC
Power Supply Voltage
VIN
VOUT
TSTG
RATING
-0.3 to 6.0
Unit
V
Input Voltage
-0.3 to Vcc+0.3
V
Output Voltage
-0.3 to Vcc+0.3
Storage Temperature
V
ο
-55 to 150
C
4.2 Recommended Operating Conditions
Symbol
VCC
VIN
TOPR
Parameter
Commercial Power Supply Voltage
Industrial Power Supply Voltage
Input Voltage
Commercial Junction Operating Temperature
Industrial Junction Operating Temperature
Min.
4.75
4.5
0
Typ.
5
5
-
Max.
5.25
5.5
Vcc
Unit
V
V
V
0
25
115
ο
C
-40
25
125
ο
C
4.3 DC Electrical Characteristics
Symbol
Parameter
IIL
Input Leakage Current
IOZ
Tri-state Leakage Current
CIN
Conditions
no pull-up or down
Min.
-1
Typ.
-10
Max.
1
Unit
uA
10
uA
Input Capacitance
3
pF
COUT
Output Capacitance
3
pF
CBID3
Bi-direction buffer Capacitance
3
VIL
Input Low Voltage
VIH
Input High Voltage
VOH
Output High Voltage
CMOS
0.7*Vcc
IOL=2,4,8,12,16,24mA
VOL
Output Low Voltage
IOH=2,4,8,12,16,24mA
RI
Input Pull-up/down resistance
CMOS
VIL=0V or VIH=VCC
pF
0.3*Vcc
V
V
0.4
3.5
V
V
50
KOhm
(Under recommended operating conditions and Vcc = 4.75 ~ 5.25V, Tj = 0 to +115 oC)
12/18
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MYSON
TECHNOLOGY
MTD655
4.4 Electrical Characteristics
FIGURE 1. RMII timing
T1
REFCLK
T2
CRSDV
RXD[1:0]
Valid
T3
TXEN
TXD[1:0]
Symbol
T1
T2
T3
T4
T4
Valid
Parameter
RMII input setup time
RMII input hold time
RMII output setup time
RMII output hold time
Min.
1
1
3
5
Typ.
Max.
Unit
nS
nS
nS
nS
Note
Typ.
Max.
Unit
nS
nS
nS
nS
Note
FIGURE 2. MII timing
RXCLK0
T5
T6
CRS0/RXDV0
RXD0[3:0]
Valid
TXCLK0
T7
TXEN0
TXD0[3:0]
Symbol
T5
T6
T7
T8
Parameter
MII input setup time
MII input hold time
MII output setup time
MII output hold time
T8
Valid
Min.
10
10
3
5
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MTD655 Revision 2.0 17/03/2000
MYSON
TECHNOLOGY
MTD655
FIGURE 3. Memor y Inter face Timing
T9
WEB
T10
OEB
T11 T12
T15
A[16:0]
Valid
T13 T14
D[7:0]
Symbol
T9
T10
T11
T12
T13
T14
T15
T16
T16
Valid
Valid
Valid
Parameter
WEB pulse width
OEB pulse width
Write Address setup time
Write Address hold time
Write Data setup time
Write Data hold time
Read Address setup time
Read Address hold time
Min.
11.5
Typ.
Max.
16
20
10
1.5
10
1
18.5
7
12
4
19.5
0
Unit
nS
nS
nS
nS
nS
nS
nS
nS
Note
Unit
nS
nS
nS
nS
Note
FIGURE 4. Inter -Bus Inter face timing I
ICLK100,
ICLK10
T17
IDATA100,
IDAT10
Symbol
Parameter
T17
Inter-Bus output setup time(100M)
Inter-Bus output setup time(10M)
T18
Inter-Bus output hold time(100M)
Inter-Bus output hold time(10M)
T18
Valid
Min.
15
Typ.
Max.
20
50
20
25
50
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MTD655 Revision 2.0 17/03/2000
MYSON
TECHNOLOGY
MTD655
FIGURE 5. Inter -Bus Inter face timing II
IMASTER
REQOUT100,
REQOUT10
REQIN100,
REQIN10
T19
T20
T22
IACKB100,
IACKB10
T21
ICOLB100,
ICOLB10
Symbol
T19
T20
T21
T22
Parameter
Inter-Bus master REQOUT asserted
to IACKB asserted propogation delay
Inter-Bus master REQOUT deasserted to IACKB deasserted propogation delay
Inter-Bus master REQIN asserted to
IACKB deasserted(ICOLB asserted)
propogation delay(SOJ)
Inter-Bus master REQOUT deasserted to IACKB asserted(ICOLBdeasserted) propogation delay(EOJ)
Min.
Typ.
Max.
Unit
Note
20
nS
1
5
nS
1
17
nS
1
5
nS
1
7
0
1
5
0
1
Note 1 : In 10M/100M Inter-Bus interface, T19-T22 have the same value.
FIGURE 6. Inter -Bus Inter face timing III
IMASTER
REQOUT100,
REQOUT10
REQIN100,
REQIN10
T23
T24
T26
IACKB100,
IACKB10
T25
ICOLB100,
ICOLB10
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MTD655 Revision 2.0 17/03/2000
MYSON
TECHNOLOGY
Symbol
T23
T24
T25
T26
Parameter
Inter-Bus slave REQOUT asserted to
IACKB asserted propogation delay
Inter-Bus slave REQOUT deasserted
to IACKB deasserted propogation
delay
Inter-Bus slave REQIN asserted to
IACKB deasserted(ICOLB asserted)
propogation delay(SOJ)
Inter-Bus slave REQOUT deasserted
to IACKB asserted(ICOLBdeasserted) propogation delay(EOJ)
MTD655
Min.
Typ.
Max.
Unit
Note
5
20
nS
2
5
20
nS
2
5
20
nS
2
5
20
nS
2
Unit
nS
nS
nS
nS
nS
Note
Note 2 : In 10M/100M Inter-Bus interface, T23-T26 have the same value.
FIGURE 7. MII Management timing
T27
Input Timing
T28
MDC
T29
MDIO
Valid
Output Timing
MDC
T30
T31
MDIO
Symbol
T27
T28
T29
T30
T31
Parameter
MDC clock cycle
MDIO input setup time
MDIO input hold time
MDIO output setup time
MDIO output hold time
Valid
Min.
10
10
182
206
16/18
Typ.
400
Max.
194
218
MTD655 Revision 2.0 17/03/2000
MYSON
TECHNOLOGY
MTD655
FIGURE 8. LED output timing
T33
T32
....
LEDCLK
....
T34
LEDCLK
T35
T36
LEDDAT
Symbol
T32
T33
T34
T35
T36
Parameter
24 LED burst clocks duration
LED burst clock cycle time
LED burst clock cycle
LEDDAT to LEDCLK setup time
LEDDAT to LEDCLK setup time
Min.
17/18
Typ.
3.84
42
160
80
80
Max.
Unit
uS
mS
nS
nS
nS
Note
MTD655 Revision 2.0 17/03/2000
MYSON
TECHNOLOGY
MTD655
5.0 128 pin PQFP Package Data
D1
Symbol
D
102
65
103
128
39
1
38
e
A1
See Detail B
Max
Min
Norm
Max
A
-
-
0.134
-
-
3.40
A1
0.010
-
-
0.25
-
-
A2
0.107 0.112
0.117
2.73
2.85
2.97
B
0.007 0.009 0.011
0.17
0.22
0.27
C
0.004
0.09
-
0.20
D
0.906 0.913 0.921 23.00 23.20 23.40
-
0.008
D1
0.783 0.787 0.791 19.90 20.00 20.10
E
0.669 0.677 0.685 17.00 17.20 17.40
E1
0.547 0.551 0.555 13.90 14.00 14.10
e
0.020 BSC
L
0.029 0.035 0.041
0.50 BSC
L1
0.063 BSC
0.73
0.88
1.03
1.60 BSC
y
-
-
0.004
-
-
0.10
z
0o
-
7o
0o
-
7o
Note:
1.Dimension D1 & E1 do not include mold protrusion.
But mold mismatch is included. Allowable protrusion is .25mm/.010” per side.
2.Dimension B does not include dambar protrusion. Allowable dambar protrusion .08mm/.003”. Total in excess of the B dimemsion at maximum material
condition. Dambar cannot be located on the lower radius or the foot.
3.Controlling dimension : Millimeter.
A
A2
B
y
Dimension in mm
Norm
E
E1
64
Dimension in inch
Min
See Detail A
Seating Plane
B
C
With Plating
Gage Plane
z
L
Base Metal
L1
Detail A
Detail B
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MTD655 Revision 2.0 17/03/2000