CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
D Phase-Lock Loop Clock Driver for Double
D
D
D
D
D
D
D
D
D
PW PACKAGE
(TOP VIEW)
Data-Rate Synchronous DRAM
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 180 MHz
Low Jitter (cyc–cyc): ±50 ps
Distributes One Differential Clock Input to
Four Differential Clock Outputs
Enters Low Power Mode and Three-State
Outputs When Input CLK Signal Is Less
Than 20 MHz or PWRDWN Is Low
Operates From Dual 2.5-V Supplies
28-Pin TSSOP Package
Consumes < 200-µA Quiescent Current
External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
GND
Y0
Y0
VDDQ
GND
CLK
CLK
VDDQ
AVDD
AGND
VDDQ
Y1
Y1
GND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
GND
Y3
Y3
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
FBOUT
FBOUT
VDDQ
Y2
Y2
GND
description
The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of
feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency
with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is
shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below
a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit
detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the
PLL again and enables the outputs.
When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The CDCV855 is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV855 is characterized for both commercial and
industrial temperature ranges.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
TSSOP (PW)
0°C to 70°C
CDCV855PW
– 40°C to 85°C
CDCV855IPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
FUNCTION TABLE
(Select Functions)
INPUTS
OUTPUTS
PLL
AVDD
GND
PWRDWN
CLK
CLK
Y[0:3]
Y[0:3]
FBOUT
FBOUT
H
L
H
L
H
L
H
Bypassed/Off
GND
H
H
L
H
L
H
L
Bypassed/Off
X
L
L
H
Z
Z
Z
Z
Off
X
L
H
L
Z
Z
Z
Z
Off
2.5 V (nom)
H
L
H
L
H
L
H
On
2.5 V (nom)
H
H
L
H
L
H
L
On
2.5 V (nom)
X
<20 MHz{
<20 MHz{
Z
Z
Z
Z
Off
† Typically 10 MHz
functional block diagram
3
2
PWRDWN
12
24
Powerdown
and Test
Logic
9
AVDD
13
17
16
26
27
FBIN
PLL
23
22
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
10
Ground for 2.5-V analog supply
AVDD
CLK, CLK
9
2.5-V analog supply
FBIN, FBIN
FBOUT, FBOUT
GND
PWRDWN
6, 7
I
Differential clock input
23, 22
I
Feedback differential clock input
19, 20
O
Feedback differential clock output
1, 5, 14, 15, 28
24
Ground
I
Control input to turn device in the power-down mode
VDDQ
Y[0:3]
4, 8, 11, 18, 21, 25
3, 12, 17, 26
O
Buffered output copies of input clock, CLK
Y[0:3]
2, 13, 16, 27
O
Buffered output copies of input clock, CLK
2
Y1
Y1
Y2
Y2
Y3
Y3
FBOUT
20 FBOUT
7
CLK
FBIN
19
6
CLK
Y0
Y0
2.5-V supply
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CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDDQ, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current to GND or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105.8°C/W
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
Supply voltage, VDDQ, AVDD
TYP
PWRDWN
CLK, CLK, FBIN, FBIN
High level input voltage,
High-level
voltage VIH
PWRDWN
DC input signal voltage (see Note 5)
2.7
V
–0.3
VDDQ/2 – 0.18
0.7
V
VDDQ/2 + 0.18
1.7
CLK, FBIN
Output differential cross-voltage, VO(X) (see Note 7)
0.36
VDDQ/2 – 0.2
VDDQ/2 – 0.2
Input differential pair cross-voltage, VI(X) (see Note 7)
Commercial
Industrial
V
V
V
mA
12
mA
1
4
V/ns
0
85
–40
85
Low-level output current, IOL
Input slew rate, SR (see Figure 7)
VDDQ/2
VDDQ + 0.6
VDDQ/2 + 0.2
V
VDDQ/2 + 0.2
–12
High-level output current, IOH
Operating free
free-air
air temperature
temperature, TA
VDDQ + 0.3
VDDQ
–0.3
Differential input signal voltage, VID (see Note 6)
UNIT
2.3
CLK, CLK, FBIN, FBIN
Low level input voltage,
Low-level
voltage VIL
MAX
V
°C
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.
5. DC input signal voltage specifies the allowable dc execution of differential input.
6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.
7. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be
crossing.
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CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MAX
UNIT
–1.2
V
Input voltage
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
IOH
IOL
VOD
Output voltage swing
VOX
Output differential
cross-voltage}
II
Input current
VDDQ = 2.7 V,
VI = 0 V to 2.7 V
±10
µA
IOZ
High-impedance-state output
current
VDDQ = 2.7 V,
VO = VDDQ or GND
±10
µA
IDD(PD)
Power-down current on
VDDQ + AVDD
CLK and CLK = 0 MHz; PWRDWN = Low;
Σ of IDD and AIDD
100
200
µA
Differential outputs
are terminated with
120 Ω / CL = 14 pF
150
180
AIDD
CI
VDDQ = 2.3 V,
II = –18 mA
VDDQ = min to max, IOH = –1 mA
TYP†
VIK
IDD
All inputs
MIN
High-level output current
VDDQ = 2.3 V,
VDDQ = 2.3 V,
IOL = 12 mA
VO = 1 V
Low-level output current
VDDQ = 2.3 V,
VO = 1.2 V
Dynamic current on VDDQ
Supply current on AVDD
VDDQ – 0.1
1.7
VDDQ = 2.3 V,
IOH = –12 mA
VDDQ = min to max, IOL = 1 mA
V
0.1
–18
–32
mA
26
35
mA
1.1
Differential outputs are terminated with
120 Ω
Differential outputs
are terminated with
120 Ω / CL = 0 pF
V
0.6
VDDQ/2 – 0.2
VDDQ – 0.4
VDDQ/2
V
VDDQ/2 + 0.2
fO = 167 MHz
fO = 167 MHz
VDDQ = 2.5 V
mA
130
160
8
10
mA
Input capacitance
VI = VDDQ or GND
2
2.5
3
pF
CO
Output capacitance
VDDQ = 2.5 V
VO = VDDQ or GND
2.5
3
3.5
pF
† All typical values are at respective nominal VDDQ.
‡ Differential cross-point voltage is expected to track variation of VDDQ and is the voltage at which the differential signals must be crossing.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
fCLK
Operating clock frequency
Input clock duty cycle
MIN
MAX
UNIT
60
180
MHz
40%
60%
Stabilization time (PLL mode)W
10
µs
Stabilization time (Bypass mode)w
30
ns
§ Recovery time required when the device goes from power-down mode into bypass mode (test mode with AVDD at GND).
¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
4
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CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
switching characteristics
PARAMETER
tPLH}
tPHL}
tjit(per)
( )§
Test mode/CLK to any output
High-to-low level propagation delay time
Test mode/CLK to any output
Jitter (period),
(period) See Figure 5
tjit(cc)
( )§
Jitter (cycle-to-cycle),
(cycle to cycle) See Figure 2
tjit(hper)
jit(h er)§
Half-period
Half
eriod jitter, See Figure 6
tslr(o)
TEST CONDITIONS
Low-to-high level propagation delay time
Output clock slew rate,
rate See Figure 7
tsk(o)¶
Output skew, See Figure 4
ns
4.5
ns
ps
ps
100/133/167/180 MHz
–35
35
66 MHz
–60
60
100/133/167/180 MHz
–50
50
66 MHz
–130
130
100 MHz
–90
90
133/167/180 MHz
–75
75
Load = 120Ω / 14 pF
1
2
V/ns
Load = 120Ω / 4 pF
1
3
V/ns
66 MHz
–180
180
100/133 MHz
–130
130
167/180 MHz
–90
90
66 MHz
–230
230
100/133 MHz
–170
170
167/180 MHz
–100
100
66 MHz
–150
150
100/133/167/180 MHz
–100
100
tr, tf
Output rise and fall times (20% – 80%)
Load: 120 Ω/14 pF
† All typical values are at a respective nominal VDDQ.
‡ Refers to transition of noninverting output
§ This parameter is assured by design but can not be 100% production tested.
¶ All differential output pins are terminated with 120 Ω/14 pF.
POST OFFICE BOX 655303
UNIT
55
SSC on
Static phase offset,
offset See Figure 3(a)
MAX
4.5
–55
Dynamic phase
hase offset (this includes jitter),
See Figure 3(b)
t(Ø)
TYP†
66 MHz
SSC off
td(Ø)w
MIN
• DALLAS, TEXAS 75265
650
ps
ps
s
ps
ps
50
ps
900
ps
5
CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VDD/2
CDCV855
SCOPE
C = 14 pF
–VDD/2
Z = 50 Ω
R = 10 Ω
Z = 60 Ω
R = 50 Ω
V(TT)
Z = 60 Ω
R = 10 Ω
Z = 50 Ω
C = 14 pF
R = 50 Ω
–VDD/2
V(TT)
–VDD/2
NOTE: V(TT) = GND
Figure 1. Output Load Test Circuit
Yx, FBOUT
Yx, FBOUT
tc(n)
tc(n+1)
tjit(cc) = tc(n) – tc(n+1)
Figure 2. Cycle-to-Cycle Jitter
6
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• DALLAS, TEXAS 75265
CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
CLK
CLK
FBIN
FBIN
t(φ) n
∑1
t(φ) n+1
n=N
t(φ) n
t(φ) =
N
(N is a Large Number of Samples)
(a) Static Phase Offset
CLK
CLK
FBIN
FBIN
t(φ)
td(φ)
t(φ)
td(φ)
td(φ)
td(φ)
(b) Dynamic Phase Offset
Figure 3. Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure 4. Output Skew
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CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
tc(n)
Yx, FBOUT
Yx, FBOUT
1
fo
tjit(per) = tc(n) –
1
fo
Figure 5. Period Jitter
Yx, FBOUT
Yx, FBOUT
t(hper_n+1)
t(hper_n)
1
fo
1
tjit(hper) = t(hper_n) –
2xfo
Figure 6. Half-Period Jitter
80%
80%
VID, VOD
Clock Inputs
and Outputs
20%
20%
tslrr(i), tslrr(o)
tslrf(i), tslrf(o)
Figure 7. Input and Output Slew Rates
8
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CDCV855, CDCV855I
2.5-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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