TI SN74LVC07ADBRG4

SN74LVC07A
www.ti.com.................................................................................................................................................... SCAS595R – OCTOBER 1997 – REVISED APRIL 2008
HEX BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
FEATURES
1
•
•
Operates From 1.65 V to 5 V
Inputs and Open-Drain Outputs Accept
Voltages up to 5.5 V
•
•
Max tpd of 2.6 ns at 5 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
DESCRIPTION/ORDERING INFORMATION
This hex buffer/driver is designed for 1.65-V to 5.5-V VCC operation.
The outputs of the SN74LVC07A device are open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of
this device as translators in a mixed-system environment.
ORDERING INFORMATION
PACKAGE (1) (2)
TA
QFN – RGY
Tube of 50
SN74LVC07AD
Reel of 2500
SN74LVC07ADR
Reel of 250
SN74LVC07ADT
SOP – NS
Reel of 2000
SN74LVC07ANSR
LVC07A
SSOP – DB
Reel of 2000
SN74LVC07ADBR
LC07A
Tube of 90
SN74LVC07APW
Reel of 2000
SN74LVC07APWR
Reel of 250
SN74LVC07APWT
Reel of 2000
SN74LVC07ADGVR
TSSOP – PW
TVSOP – DGV
(1)
(2)
TOP-SIDE MARKING
SN74LVC07ARGYR
SOIC – D
–40°C to 85°C
ORDERABLE PART NUMBER
Reel of 1000
LC07A
LVC07A
LC07A
LC07A
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2008, Texas Instruments Incorporated
SN74LVC07A
SCAS595R – OCTOBER 1997 – REVISED APRIL 2008.................................................................................................................................................... www.ti.com
FUNCTION TABLE
(EACH BUFFER/DRIVER)
INPUT
A
OUTPUT
Y
H
H
L
L
LOGIC DIAGRAM, EACH BUFFER/DRIVER (POSITIVE LOGIC)
A
Y
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
–0.5
6.5
V
–0.5
6.5
V
VI
Input voltage range
VO
Output voltage range
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
D package
(3)
DB package
θJA
Package thermal impedance
86
(3)
96
DGV package (3)
127
NS package (3)
76
PW package (3)
113
RGY package (4)
Tstg
(1)
(2)
(3)
(4)
2
Storage temperature range
°C/W
47
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
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Copyright © 1997–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A
SN74LVC07A
www.ti.com.................................................................................................................................................... SCAS595R – OCTOBER 1997 – REVISED APRIL 2008
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
High-level input voltage
MAX
1.65
5.5
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
Low-level input voltage
VI
Input voltage
VO
Output voltage
Low-level output current
TA
(1)
V
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
V
0.3 × VCC
VCC = 4.5 V to 5.5 V
IOL
V
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIH
MIN
0
5.5
V
0
5.5
V
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
VCC = 4.5 V
24
Operating free-air temperature
–40
mA
°C
85
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOL = 100 µA
IOL = 4 mA
VOL
IOL = 12 mA
IOL = 24 mA
II
VI or VO = 5.5 V
ICC
VI = VCC or GND,
ΔICC
Ci
(1)
VI = 5.5 V or GND
Ioff
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
VCC
MIN
TYP (1)
MAX
1.65 V to 5.5 V
0.2
1.65 V
0.45
2.3 V
0.7
2.7 V
0.4
3V
0.55
UNIT
V
3.6 V
±5
µA
0V
±10
µA
3.6 V
10
µA
2.7 V to 3.6 V
500
µA
3.3 V
5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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SN74LVC07A
SCAS595R – OCTOBER 1997 – REVISED APRIL 2008.................................................................................................................................................... www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 4)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
MAX
1
5.6
1
3.4
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MAX
MIN
MAX
MIN
MAX
3.3
1
3.6
1
2.6
UNIT
ns
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
per buffer/driver
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
1.8
2
2.5
3.78
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UNIT
pF
Copyright © 1997–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A
SN74LVC07A
www.ti.com.................................................................................................................................................... SCAS595R – OCTOBER 1997 – REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
TEST
S1
tPZL (see Note F)
2 × VCC
tPLZ (see Note G)
2 × VCC
tPHZ/tPZH
2 × VCC
GND
CL = 30 pF
(see Note A)
1 kΩ
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VCC
VCC/2
VOL
VOL + 0.15 V
VOL
tPHZ
Output
Waveform 2
S1 at 2 × VCC
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VCC
VCC − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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SN74LVC07A
SCAS595R – OCTOBER 1997 – REVISED APRIL 2008.................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
S1
tPZL (see Note F)
2 × VCC
tPLZ (see Note G)
2 × VCC
tPHZ/tPZH
2 × VCC
GND
CL = 30 pF
(see Note A)
500 Ω
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VCC
VCC/2
VOL
Output
Waveform 2
S1 at 2 × VCC
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VOL + 0.15 V
VOL
tPHZ
VCC/2
VCC
VCC − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.15 V.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
6
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Copyright © 1997–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A
SN74LVC07A
www.ti.com.................................................................................................................................................... SCAS595R – OCTOBER 1997 – REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 and 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPZL (see Note F)
6V
tPLZ (see Note G)
6V
tPHZ/tPZH
6V
LOAD CIRCUIT
tw
2.7 V
2.7 V
Timing
Input
0V
0V
2.7 V
1.5 V
1.5 V
0V
1.5 V
Output
Control
(low-level
enabling)
2.7 V
1.5 V
1.5 V
0V
tPLH
3V
1.5 V
tPZH
3V
1.5 V
tPLZ
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
VOL
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at 6 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
0V
tPZL
2.7 V
Output
VOLTAGE WAVEFORMS
PULSE DURATION
th
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
1.5 V
tsu
Data
Input
1.5 V
Input
3V
1.5 V
2.7 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at 1.5 V.
G. tPLZ is measured at VOL + 0.3 V.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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SN74LVC07A
SCAS595R – OCTOBER 1997 – REVISED APRIL 2008.................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC = 5 V ± 0.5 V
2 x VCC
500 Ω
2 x VCC
2 x VCC
500 Ω
2 x VCC
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
Output
Waveform 2
S1 at 2 x VCC
(see Note B)
0.3 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal connections such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal connections such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VCC/2.
G. tPLZ is measured at VOL + 0.3 V.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
8
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Product Folder Link(s): SN74LVC07A
PACKAGE OPTION ADDENDUM
www.ti.com
9-Apr-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC07AD
ACTIVE
SOIC
D
14
SN74LVC07ADBR
ACTIVE
SSOP
DB
SN74LVC07ADBRG4
ACTIVE
SSOP
SN74LVC07ADE4
ACTIVE
SN74LVC07ADG4
50
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ADGVR
ACTIVE
TVSOP
DGV
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ADGVRE4
ACTIVE
TVSOP
DGV
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ADGVRG4
ACTIVE
TVSOP
DGV
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ADR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ADRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ADRG3
PREVIEW
SOIC
D
14
2500
SN74LVC07ADRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ADT
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ADTE4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ADTG4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ANSR
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ANSRE4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ANSRG4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07APW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07APWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07APWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07APWLE
OBSOLETE
TSSOP
PW
14
SN74LVC07APWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07APWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07APWRG3
PREVIEW
TSSOP
PW
14
2000
SN74LVC07APWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
TBD
TBD
Addendum-Page 1
TBD
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CU NIPDAU
Call TI
Call TI
Call TI
Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com
9-Apr-2010
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC07APWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07APWTE4
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07APWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC07ARGYR
ACTIVE
VQFN
RGY
14
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN74LVC07ARGYRG4
ACTIVE
VQFN
RGY
14
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC07A :
SN74LVC07A-Q1
• Automotive:
• Enhanced Product: SN74LVC07A-EP
NOTE: Qualified Version Definitions:
- Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Automotive
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC07ADBR
SSOP
DB
14
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74LVC07ADGVR
TVSOP
DGV
14
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74LVC07ADR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC07ADR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC07ADT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LVC07ANSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LVC07APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC07APWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC07ARGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC07ADBR
SSOP
DB
14
2000
346.0
346.0
33.0
SN74LVC07ADGVR
TVSOP
DGV
14
2000
346.0
346.0
29.0
SN74LVC07ADR
SOIC
D
14
2500
346.0
346.0
33.0
SN74LVC07ADR
SOIC
D
14
2500
333.2
345.9
28.6
SN74LVC07ADT
SOIC
D
14
250
346.0
346.0
33.0
SN74LVC07ANSR
SO
NS
14
2000
346.0
346.0
33.0
SN74LVC07APWR
TSSOP
PW
14
2000
346.0
346.0
29.0
SN74LVC07APWT
TSSOP
PW
14
250
346.0
346.0
29.0
SN74LVC07ARGYR
VQFN
RGY
14
3000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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