TI SM320C80GFM50

SGUS025B – AUGUST 1998 – REVISED JUNE 2002
D Single-Chip Parallel Multiple
D
D
D
D
D
D
D
D
D
D
D
D
Instruction/Multiple Data (MIMD) Digital
Signal Processor (DSP)
More Than Two Billion RISC-Equivalent
Operations per Second
Master Processor (MP)
– 32-Bit Reduced Instruction Set
Computing (RISC) Processor
– IEEE-754 Floating-Point Capability
– 4K-Byte Instruction Cache
– 4K-Byte Data Cache
Four Parallel Processors (PP)
– 32-Bit Advanced DSPs
– 64-Bit Opcode Provides Many Parallel
Operations per Cycle
– 2K-Byte Instruction Cache and 8K-Byte
Data RAM per PP
Transfer Controller (TC)
– 64-Bit Data Transfers
– Up to 400 Megabytes per Second (MBps)
Transfer Rate
– 32-Bit Addressing
– Direct DRAM/VRAM Interface With
Dynamic Bus Sizing
– Intelligent Queuing and Cycle
Prioritization
Video Controller (VC)
– Provides Video Timing and Video
Random-Access Memory (VRAM)
Control
– Dual-Frame Timers for Two Simultaneous
Image-Capture and/or Display Systems
Big- or Little-Endian Operation
50K-Byte On-Chip RAM
4G-Byte Address Space
20-ns Cycle Time
3.3-V Operation
IEEE Standard 1149.1† Test Access Port
(JTAG)
Operating Temperature Range
–55°C to 125°C - M-Temperature
–40°C to 85°C - A-Temperature
GF PACKAGE
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
Copyright  2002, Texas Instruments Incorporated
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1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
GF Pin Assignments – Numerical Listing . . . . . . . . . . . . . . . . 3
GF Pin Assignments – Alphabetical Listing . . . . . . . . . . . . . . 5
HFH Pin Assignments – Numerical Listing . . . . . . . . . . . . . . 7
HFH Pin Assignments – Alphabetical Listing . . . . . . . . . . . . 9
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
master processor (MP) architecture . . . . . . . . . . . . . . . . . . . 17
MP control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MP parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MP interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PP architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PP data-unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PP address-unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PP program flow control (PFC) unit registers . . . . . . . . . . . 40
PP cache architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PP parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PP-interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PP data-unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PP multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PP program-flow-control unit architecture . . . . . . . . . . . . . . 46
PP address-unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . 48
PP instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PP opcode formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
EALU operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
TC architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
external memory timing examples . . . . . . . . . . . . . . . . . . . . 73
host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over specified temperature
ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions . . . . . . . . . . . . . . . . . .
electrical characteristics over recommended range of
supply voltage and specified temperature . . . . . . . .
signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
timing parameter symbology . . . . . . . . . . . . . . . . . . . . . . . .
general notes on timing parameters . . . . . . . . . . . . . . . . . .
CLKIN timing requirements . . . . . . . . . . . . . . . . . . . . . . . . .
local-bus switching characteristics over full operating
range: CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device reset timing requirements . . . . . . . . . . . . . . . . . . . .
local bus timing requirements: cycle configuration
inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
local bus timing: cycle completion inputs . . . . . . . . . . . . . .
general output signal characteristics over operating
conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
local bus timing: 2-cycle/column CAS timing . . . . . . . . . . .
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XPT input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
host-interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
video interface timing: SCLK timing . . . . . . . . . . . . . . . . . .
video interface timing: FCLK input and video outputs . . .
video interface timing: external sync inputs . . . . . . . . . . .
emulator interface connection . . . . . . . . . . . . . . . . . . . . . . .
MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
128
128
129
129
129
130
131
132
132
132
133
134
135
138
140
141
142
143
144
145
146
147
148
151
152
description
The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations
per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations
per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer
controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly
through an on-chip crossbar that provides shared access to on-chip RAM. This performance and
programmability make the ’C80 ideally suited for video, imaging, and high-speed telecommunications
applications.
2
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF Pin Assignments – Numerical Listing
PIN
NUMBER
PIN
PIN
PIN
NAME
NUMBER
NAME
NUMBER
NAME
A5
CT1
C21
VDD
HACK
C23
VDD
W
E33
A7
E35
C25
DBEN
F2
C27
C29
VSS
CAREA0
F4
A13
VSS
CAS/DQM7
A15
CAS/DQM5
C31
CBLNK0/VBLNK0
F10
A17
D2
RETRY
F12
A19
VDD
VSS
D4
F14
A21
RAS
D6
VDD
VSS
A23
DSF
D8
AS0
F18
A25
VSS
SCLK1
D10
UTIME
F20
D12
F22
D14
A31
VDD
EINT1
VSS
RESET
D16
REQ0
F26
B2
NC
D18
F28
B4
BS1
D20
VSS
CAS/DQM0
B6
D22
FCLK1
F34
B8
VDD
PS1
D24
B10
REQ1
D26
VSS
CAREA1
B12
D28
SCLK0
B14
VDD
CAS/DQM6
D30
EINT2
R5
CAS/DQM3
D32
G33
CBLNK1/VBLNK1
R31
B18
D34
G35
E1
AS1
H2
VDD
STATUS0
R33
B20
VDD
CAS/DQM1
VSS
VDD
VSYNC0
G31
B16
B22
TRG/CAS
E3
FAULT
H4
A3
T2
VSS
A5
B24
E5
CSYNC1/HBLNK1
T4
A13
E7
VSS
STATUS2
H32
B26
VDD
DDIN
H34
TDI
T32
D62
B28
FCLK0
E9
READY
J1
STATUS1
T34
EMU0
B30
VDD
CSYNC0/HBLNK0
E11
BS0
J3
J5
U3
VDD
A10
J31
VSS
VDD
VDD
U1
E13
U5
PS3
A9
A11
A27
A29
B32
NUMBER
NAME
HSYNC0
L5
TCK
L31
VSS
VSS
VDD
VSS
L33
TRST
L35
XPT1
VDD
VSS
M2
VDD
VSS
VDD
PS0
M32
VSS
CT2
N1
VSS
VDD
VDD
N3
A8
N5
N31
VSS
VSS
VDD
VSS
N33
TMS
N35
VDD
VSS
P2
VDD
A4
P4
A9
P32
TDO
G1
VDD
VDD
P34
XPT0
G3
A2
R1
G5
A1
R3
VSS
VDD
VDD
F8
F16
VDD
VSS
F24
F32
M4
M34
R35
VDD
VDD
E15
C5
VSS
STATUS3
VSS
HREQ
E17
CAS/DQM4
J33
NC
AS2
E19
RL
J35
VSS
EMU1
U31
C7
U33
D61
C9
VSS
CT0
E21
STATUS5
K2
STATUS4
U35
C11
E23
K4
A6
V2
VDD
VDD
C13
PS2
E25
VSS
CLKOUT
K32
VSYNC1
V4
C15
VDD
CLKIN
E27
LINT4
K34
HSYNC1
V32
C17
E29
EINT3
L1
A0
V34
C19
CAS/DQM2
E31
VSS
L3
A7
W1
C3
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VSS
VSS
VDD
A11
3
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF Pin Assignments – Numerical Listing (Continued)
PIN
NUMBER
NUMBER
PIN
NAME
NUMBER
PIN
NAME
NUMBER
NAME
W3
A18
AG1
A16
AL17
D20
AN29
D35
W5
AG3
VSS
VDD
AL19
D21
AN31
D45
W31
VSS
VSS
AL21
D24
AN33
W33
D59
AG31
AL23
VDD
A27
D63
AG33
AL25
VSS
D29
AP4
W35
VDD
VSS
Y2
A12
AG35
D57
AL27
D32
AP8
VDD
D5
Y4
A19
AH2
A20
AL29
D38
AP10
D8
Y32
XPT2
AH4
A30
AL31
AP12
Y34
D56
AH32
D44
AL33
VSS
D48
AP14
VDD
D13
AA1
VSS
VDD
AH34
D54
AL35
D53
AP16
D17
AJ1
A24
AP18
AJ3
VDD
A31
AM2
VDD
VDD
AM4
AP20
VDD
D26
AM6
AP22
D34
AJ31
AM8
D2
AP24
AA35
VDD
VSS
VSS
VSS
VDD
VSS
AJ33
D42
AM10
D6
AP26
VDD
D39
AB2
A14
AJ35
D41
AK2
AM14
VSS
D14
AP28
A21
VDD
VDD
AM12
AB4
AP30
AB32
D55
AK4
AM16
D19
AP32
VDD
D47
AB34
D60
AK8
VSS
VDD
AM18
D0
VDD
A22
AK10
VSS
VDD
AM20
VSS
D23
AR5
AC1
AR7
AM22
D25
AR9
VDD
D7
AK14
AM26
VSS
D31
AR11
AK16
VSS
VDD
AM24
AC31
VSS
VSS
AR13
VSS
D11
AC33
D52
AK18
NC
AM28
D33
AR15
D15
AC35
VDD
VDD
AK20
VSS
D27
AM30
AR17
AM32
VSS
VDD
AR19
VSS
VDD
VSS
VSS
AK24
VDD
VSS
AM34
D50
AR21
D30
AN5
A29
AR23
D36
VDD
A15
AK28
VDD
VSS
AN7
D1
AR25
AE1
AN9
AR27
VSS
D40
AE3
A26
AK34
AN11
AE5
AL1
AN13
D12
AR31
AE31
VSS
VSS
VDD
A23
VSS
D9
AL3
A25
AN15
AE33
D51
AL5
AN17
AE35
D58
AL7
VSS
D3
VDD
D18
AN19
D22
AF2
A17
AL9
D4
AN21
AF4
A28
AL11
D10
AN23
VDD
D28
AF32
D46
AL13
AN25
D37
AF34
D49
AL15
VSS
D16
AN27
VSS
AA3
AA5
AA31
AA33
AC3
AC5
AD2
AD4
AD32
AD34
4
PIN
NAME
AG5
AJ5
AK12
AK22
AK26
AK32
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AP6
AR29
VDD
D43
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF Pin Assignments – Alphabetical Listing
PIN
NAME
PIN
NUMBER
NAME
A0
L1
A1
G5
A2
A3
A4
PIN
NUMBER
NAME
CAS/DQM1
B20
CAS/DQM2
C19
G3
CAS/DQM3
H4
CAS/DQM4
P2
A5
A6
A7
PIN
NUMBER
NAME
NUMBER
D24
AL21
DBEN
C25
D25
AM22
DDIN
B26
B16
D26
AP20
DSF
A23
E17
D27
AK22
EINT1
A31
CAS/DQM5
A15
D28
AN23
EINT2
G31
T2
CAS/DQM6
B14
D29
AL25
EINT3
E29
K4
CAS/DQM7
A13
D30
AR21
EMU0
T34
L3
CBLNK0/VBLNK0
C31
D31
AM26
EMU1
J35
A8
N3
CBLNK1/VBLNK1
G33
D32
AL27
FAULT
E3
A9
P4
CLKIN
C17
D33
AM28
FCLK0
B28
D22
A10
U3
CLKOUT
E25
D34
AP22
FCLK1
A11
W1
CSYNC0/HBLNK0
B32
D35
AN29
HACK
A9
A12
Y2
CSYNC1/HBLNK1
H32
D36
AR23
HREQ
E15
A13
T4
CT0
C11
D37
AN25
HSYNC0
E33
A14
AB2
CT1
A5
D38
AL29
HSYNC1
K34
A15
AE1
CT2
F18
D39
AP26
LINT4
E27
A16
AG1
D0
AR5
D40
AR27
NC
B2
A17
AF2
D1
AN7
D41
AP28
NC
U31
A18
W3
D2
AM8
D42
AJ33
NC
AK18
A19
Y4
D3
AL7
D43
AR31
PS0
F14
A20
AH2
D4
AL9
D44
AH32
PS1
B8
A21
AB4
D5
AP8
D45
AN31
PS2
C13
A22
AC3
D6
AM10
D46
AF32
PS3
U5
A23
AL1
D7
AR9
D47
AP32
RAS
A21
A24
AM2
D8
AP10
D48
AL33
READY
E9
A25
AL3
D9
AN11
D49
AF34
REQ0
D16
A26
AE3
D10
AL11
D50
AM34
REQ1
B10
A27
AP4
D11
AR13
D51
AE33
RESET
D14
A28
AF4
D12
AN13
D52
AC33
RETRY
D2
A29
AN5
D13
AP14
D53
AL35
RL
E19
A30
AH4
D14
AM14
D54
AH34
SCLK0
D28
A31
AJ3
D15
AR15
D55
AB32
SCLK1
A27
AS0
D8
D16
AL15
D56
Y34
STATUS0
H2
AS1
E1
D17
AP16
D57
AG35
STATUS1
J1
AS2
C7
D18
AN17
D58
AE35
STATUS2
E7
BS0
E11
D19
AM16
D59
W33
STATUS3
C5
STATUS4
K2
BS1
B4
D20
AL17
D60
AB34
CAREA0
C29
D21
AL19
D61
U33
CAREA1
D26
D22
AN19
D62
T32
CAS/DQM0
D20
D23
AM20
D63
W35
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5
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF Pin Assignments – Alphabetical Listing (Continued)
PIN
PIN
PIN
NUMBER
NAME
NUMBER
NAME
NUMBER
NAME
NUMBER
STATUS5
E21
VDD
VSS
AR29
VSS
VSS
AA35
E35
VDD
VDD
R31
TCK
VSS
VSS
A19
VSS
VSS
AC31
VSS
VSS
C3
VSS
VSS
AD32
VSS
VSS
C27
VSS
VSS
AE31
VSS
VSS
D12
VSS
VSS
AG33
VSS
VSS
D24
VSS
VSS
AJ31
VSS
VSS
E5
VSS
VSS
AK10
VSS
VSS
AK20
VSS
VSS
AK32
VSS
VSS
AL13
VSS
VSS
AL31
VSS
VSS
AM12
VSS
VSS
AM24
TDI
H34
TDO
P32
TMS
N33
TRG/CAS
B22
TRST
L33
UTIME
D10
VDD
VDD
A17
A7
VDD
VDD
A29
VDD
VDD
B12
VDD
VDD
B24
VDD
VDD
C15
VDD
VDD
6
PIN
NAME
B6
B18
B30
C21
D4
D32
VDD
VDD
F2
VDD
VDD
F12
VDD
VDD
F24
VDD
VDD
F34
VDD
VDD
G35
VDD
VDD
J31
VDD
VDD
M34
VDD
VDD
N35
VDD
F8
F20
F28
G1
J5
M2
VDD
VDD
VDD
VDD
R33
U1
U35
V2
V34
VDD
VDD
AA3
VDD
VDD
AA31
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AA5
AA33
AC1
AC35
AD2
AD34
AG5
AG31
AJ1
AJ35
VDD
VDD
AK2
VDD
VDD
AK12
VDD
VDD
AK24
VDD
VDD
AK34
VDD
VDD
AM32
VDD
VDD
AN21
VDD
VDD
AP6
AK8
AK16
AK28
AM4
AN15
AN33
AP12
VDD
VDD
AP18
AP30
R3
VDD
VDD
R5
VDD
N1
AP24
A11
A25
C9
D6
D18
D30
E13
VSS
VSS
E23
VSS
VSS
F4
E31
F10
VSS
VSS
F16
VSS
VSS
F26
VSS
VSS
J3
F22
F32
J33
VSS
VSS
L31
VSS
VSS
M32
VSS
VSS
N31
VSS
VSS
VSS
VSS
L5
M4
N5
R1
AC5
AD4
AE5
AG3
AJ5
AK4
AK14
AK26
AL5
AL23
AM6
AM18
AM30
VSS
VSS
AN27
AN9
VSS
VSS
AR17
AR11
AR25
R35
VSS
VSYNC0
V4
VSYNC1
K32
V32
D34
W
C23
W5
XPT0
P34
AR7
VSS
VSS
W31
XPT1
L35
AR19
VSS
AA1
XPT2
Y32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
HFH Pin Assignments – Numerical Listing
PIN
PIN
PIN
NUMBER
NAME
NUMBER
NAME
NUMBER
1
STATUS3
41
CAS/DQM6
2
42
3
VSS
STATUS2
VSS
CAS/DQM5
4
STATUS1
44
5
45
6
VDD
STATUS0
VDD
CAS/DQM4
46
7
AS2
47
8
AS1
PIN
NAME
NUMBER
NAME
81
LINT4
121
82
EINT3
122
VDD
D59
83
EINT2
123
84
EINT1
124
85
CBLNK1/VBLNK1
125
CAS/DQM3
86
CBLNK0/VBLNK0
126
VDD
D57
CT2
87
127
XPT2
48
CAS/DQM2
88
VSS
VSS
128
VSS
CAS/DQM1
89
CSYNC1/HBLNK1
129
VSS
D56
90
130
43
9
AS0
49
10
FAULT
50
VSS
D58
11
READY
51
91
12
RETRY
52
VDD
CAS/DQM0
VDD
VDD
92
CSYNC0/HBLNK0
132
D55
13
UTIME
53
RL
93
VSYNC1
133
14
BS1
54
RAS
94
VSYNC0
134
VSS
D54
15
BS0
55
95
CT1
56
96
VSS
VSS
135
16
VSS
VSS
17
CT0
57
97
HSYNC1
137
18
PS2
58
VSS
TRG/CAS
98
138
19
PS1
59
VDD
VDD
139
D52
20
PS0
60
140
21
VDD
RESET
61
101
141
VDD
D51
62
VDD
VDD
VDD
HSYNC0
102
TRST
142
D50
63
W
103
TCK
143
D49
24
VSS
HREQ
64
STATUS5
104
TMS
144
25
HACK
65
105
TDI
145
VSS
VSS
26
66
106
TDO
146
D48
27
VSS
VSS
VDD
DSF
EMU1
147
REQ1
68
VSS
DBEN
107
28
108
XPT0
148
VDD
VDD
29
REQ0
69
XPT1
149
VDD
VDD
70
VDD
DDIN
109
30
110
150
VDD
D47
71
CLKOUT
111
VSS
VSS
151
D46
VSS
VDD
VSS
72
CAREA1
112
EMU0
152
D45
73
VSS
SCLK1
113
153
114
VDD
D63
VSS
VSS
VSS
CLKIN
75
VDD
FCLK0
115
D62
155
D44
116
156
VSS
CAS/DQM7
77
VSS
SCLK0
117
VSS
D61
VDD
VDD
158
VDD
VDD
79
119
VSS
D60
159
VDD
D43
120
VDD
160
D42
22
23
31
32
33
34
35
36
37
38
39
40
67
74
76
78
80
VDD
FCLK1
VDD
CAREA0
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100
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• HOUSTON, TEXAS 77251–1443
131
136
154
157
VDD
VDD
VDD
D53
VSS
VSS
7
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
HFH Pin Assignments – Numerical Listing (Continued)
PIN
NUMBER
NUMBER
NAME
NUMBER
161
D41
162
163
VSS
VSS
201
D20
202
203
VDD
VDD
164
D40
204
D19
165
205
166
VDD
D39
167
D38
207
168
D37
208
169
VSS
D36
209
170
171
206
210
PIN
NAME
NUMBER
NAME
241
D0
281
242
282
VDD
VDD
243
VDD
VDD
244
A31
284
VDD
A15
VDD
D18
245
285
PS3
246
VSS
A30
286
A14
VSS
D17
247
A29
287
248
288
VSS
VSS
249
VSS
VSS
VSS
VDD
289
A13
250
A28
290
VDD
VDD
291
VSS
VSS
292
A12
293
VDD
A11
283
211
D16
251
212
213
VDD
D15
252
173
VSS
VDD
D35
174
D34
214
D14
254
VDD
A27
175
D33
215
D13
255
A26
295
176
VSS
D32
216
VSS
VSS
256
A25
296
217
257
297
218
D12
258
179
VDD
VDD
VSS
VSS
219
220
VSS
A24
299
D31
VDD
VDD
259
180
181
D30
221
222
VDD
VDD
301
D29
VDD
D11
261
182
302
VDD
A7
183
VSS
VSS
223
D10
263
303
A6
224
D9
264
VDD
A23
304
VSS
D28
225
VSS
D8
265
A22
305
VSS
VSS
266
306
A5
227
307
228
VDD
VDD
267
188
VDD
VDD
VDD
A21
308
VSS
A4
189
D27
229
D7
269
VSS
VSS
190
D26
230
D6
270
A20
310
191
D25
231
D5
271
311
192
VSS
D24
232
VSS
VSS
272
VDD
VDD
312
273
A19
313
VDD
VDD
234
D4
274
235
275
196
D23
236
VDD
D3
VSS
A18
314
195
276
A17
316
197
D22
237
D2
277
A0
238
318
239
VSS
D1
278
199
VSS
D21
VSS
VSS
317
198
319
200
VSS
240
VSS
280
VSS
A16
VDD
STATUS4
320
VSS
172
177
178
184
185
186
187
193
194
8
PIN
NAME
226
233
POST OFFICE BOX 1443
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260
262
268
279
• HOUSTON, TEXAS 77251–1443
294
298
300
309
315
VSS
A10
VDD
A9
VSS
A8
VDD
VDD
VDD
A3
VDD
A2
VSS
A1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
HFH Pin Assignments – Alphabetical Listing
PIN
PIN
PIN
PIN
NAME
NUMBER
NAME
NUMBER
NAME
NUMBER
NAME
NUMBER
A0
317
CAS/DQM1
50
D30
181
DBEN
68
A1
316
CAS/DQM2
48
D31
180
DDIN
70
A10
296
CAS/DQM3
46
D32
177
DSF
66
A11
294
CAS/DQM4
45
D33
175
EINT1
84
A12
292
CAS/DQM5
43
D34
174
EINT2
83
A13
289
CAS/DQM6
41
D35
173
EINT3
82
A14
286
CAS/DQM7
38
D36
170
EMU0
112
A15
284
CBLNK0/VBLNK0
86
D37
168
EMU1
107
A16
280
CBLNK1/VBLNK1
85
D38
167
FAULT
10
A17
276
CLKIN
36
D39
166
FCLK0
76
A18
275
CLKOUT
71
D4
234
FCLK1
60
A19
273
CSYNC0/HBLNK0
92
D40
164
HACK
25
A2
314
CSYNC1/HBLNK1
89
D41
161
HREQ
24
A20
270
CT0
17
D42
160
HSYNC0
101
A21
267
CT1
16
D43
159
HSYNC1
97
A22
265
CT2
47
D44
155
LINT4
81
A23
264
D0
241
D45
152
PS0
20
A24
260
D1
239
D46
151
PS1
19
A25
256
D10
223
D47
150
PS2
18
A26
255
D11
222
D48
146
PS3
285
A27
254
D12
218
D49
143
RAS
54
A28
250
D13
215
D5
231
READY
11
A29
247
D14
214
D50
142
REQ0
29
A3
312
D15
213
D51
141
REQ1
28
A30
246
D16
211
D52
139
RESET
22
A31
244
D17
208
D53
136
RETRY
12
A4
308
D18
206
D54
134
RL
53
A5
306
D19
204
D55
132
SCLK0
78
A6
303
D2
237
D56
129
SCLK1
74
A7
302
D20
201
D57
126
STATUS0
6
A8
300
D21
199
D58
124
STATUS1
4
A9
298
D22
197
D59
122
STATUS2
3
AS0
9
D23
196
D6
230
STATUS3
1
AS1
8
D24
193
D60
119
STATUS4
319
AS2
7
D25
191
D61
117
STATUS5
64
BS0
15
D26
190
D62
115
TCK
103
TDI
105
BS1
14
D27
189
D63
114
CAREA0
80
D28
186
D7
229
CAREA1
72
D29
182
D8
226
CAS/DQM0
52
D3
236
D9
224
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
9
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
HFH Pin Assignments – Alphabetical Listing (Continued)
PIN
PIN
PIN
NUMBER
NAME
NUMBER
NAME
NUMBER
NAME
NUMBER
TDO
106
VSS
VSS
110
VSS
VSS
259
104
VDD
VDD
243
TMS
VDD
VDD
252
VSS
VSS
116
VSS
VSS
268
VDD
VDD
261
VSS
VSS
123
VSS
VSS
27
VDD
VDD
263
VSS
VSS
133
VDD
VDD
271
VSS
VSS
138
VDD
VDD
281
VSS
VSS
145
VDD
VDD
283
VSS
VSS
154
VDD
VDD
293
VSS
VSS
163
VDD
VDD
30
VSS
VSS
171
VSS
VSS
183
VSS
VSS
185
VSS
VSS
198
VSS
VSS
200
VSS
VSS
209
VSS
VSS
217
VSS
VSS
23
TRG/CAS
58
TRST
102
UTIME
13
VDD
VDD
100
VDD
VDD
120
VDD
VDD
125
VDD
VDD
131
VDD
VDD
140
VDD
VDD
148
VDD
VDD
156
VDD
VDD
158
VDD
VDD
172
VDD
VDD
179
VDD
VDD
188
VDD
VDD
195
VDD
VDD
203
VDD
VDD
10
PIN
NAME
113
121
130
135
147
149
157
165
178
187
194
202
205
21
212
VDD
VDD
VDD
VDD
251
253
262
266
272
282
288
297
301
309
310
311
313
VDD
VDD
318
VDD
VDD
40
VDD
VDD
44
VDD
VDD
51
VDD
VDD
61
VDD
VDD
65
VDD
VDD
75
VDD
VDD
90
39
33
5
59
62
118
128
137
144
153
162
169
176
184
192
2
207
216
225
232
26
269
274
VSS
VSS
277
VSS
VSS
279
VSS
VSS
290
VSS
VSS
295
VSS
VSS
304
VSS
VSS
307
VSS
VSS
320
VSS
VSS
35
VSS
VSS
42
VSS
VSS
55
VSS
VSS
57
VSS
VSS
73
VSS
VSS
87
95
278
287
291
299
305
315
34
37
49
56
67
77
88
VSS
VSS
233
238
VSS
VSS
VSS
VSS
240
VSYNC0
94
245
VSYNC1
93
VSS
VSS
248
W
63
249
XPT0
108
VDD
VDD
219
VDD
VDD
221
VDD
VDD
228
XPT1
109
99
VSS
VSS
257
31
VDD
VDD
98
VDD
210
XPT2
127
VDD
242
VSS
32
VSS
258
220
227
235
69
111
79
91
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
96
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Terminal Functions
TERMINAL
NAME
DESCRIPTION
TYPE†
LOCAL MEMORY INTERFACE
A31–A0
O
Address bus. A31–A0 output the 32-bit byte address of the external memory cycle. The address can be
multiplexed for DRAM accesses.
AS2–AS0
I
Address-shift selection. AS2–AS0 determine how the column address appears on the address bus. Eight
shift values are supported, including zero.
BS1–BS0
I
Bus size selection. BS1–BS0 indicate the bus size of the memory or other devices being accessed,
allowing dynamic bus sizing for data buses less than 64 bits wide.
CT2–CT0
I
Cycle timing selection. CT2–CT0 signals determine the timing of the current memory access.
D63–D0
I/O
Data bus. D63–D0 transfer up to 64 bits of data per memory cycle into or out of the ’C80.
DBEN
O
Data-buffer enable. DBEN drives the active-low output enables of bidirectional transceivers that can be
used to buffer input and output data on D63–D0.
DDIN
O
Data direction indicator. DDIN indicates the direction of the data that passes through the transceivers.
When DDIN is low, the transfer is from external memory into the ’C80.
FAULT
I
Fault. FAULT is driven low by external circuitry to inform the ’C80 that a fault has occurred on the current
memory row access.
PS3–PS0
I
Page size indication. PS3–PS0 indicate the page size of the memory device(s) being accessed by the
current cycle. The ’C80 uses this information to determine when to begin a new row access.
READY
I
Ready. READY indicates that the external device is ready to complete the memory cycle. READY is driven
low by external circuitry to insert wait states into a memory cycle.
RL
O
Row latch. The high-to-low transition of RL can be used to latch the valid 32-bit byte address that is present
on A31–A0.
RETRY
I
Retry. RETRY is driven low by external circuitry to indicate that the addressed memory is busy. The ’C80
memory cycle is rescheduled.
STATUS5–STATUS0
O
Status code. At row time, STATUS5–STATUS0 indicate the type of cycle being performed. At column time,
they identify the processor and type of request that initiated the cycle.
UTIME
I
User-timing selection. UTIME causes the timing of RAS and CAS/DQM7–CAS/DQM0 to be modified so
that custom memory timings can be generated. During reset, UTIME selects the endian mode in which the
’C80 operates.
CAS/DQM7–
CAS/DQM0
O
Column-address strobes. CAS/DQM7–CAS/DQM0 drive the CAS inputs of DRAMs and VRAMs, or the
DQM input of synchronous dynamic random-access memories (SDRAMs). The eight strobes provide
byte-write access to memory.
DSF
O
Special function. DSF selects special VRAM functions such as block-write, load color register, split-register
transfer, and synchronous graphics random-access memory (SGRAM) block write.
RAS
O
Row-address strobe. RAS drives the RAS inputs of DRAMs, VRAMs, and SDRAMs.
TRG/CAS
O
Transfer/output enable or column-address strobe. TRG/CAS is used as an output enable for DRAMs and
VRAMs, and also as a transfer enable for VRAMs. TRG/CAS also drives the CAS inputs of SDRAMs.
W
O
Write enable. W is driven low before CAS during write cycles. W controls the direction of the transfer during
VRAM transfer cycles.
DRAM, VRAM, AND SDRAM CONTROL
† I = input, O = output, Z = high-impedance
‡ This pin has an internal pullup and can be left unconnected during normal operation.
§ This pin has an internal pulldown and can be left unconnected during normal operation.
¶ For proper operation, all VDD and VSS pins must be connected externally.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
TYPE†
HOST INTERFACE
O
Host acknowledge. The ’C80 drives HACK output low following an active HREQ to indicate that it has driven
the local memory bus signals to the high-impedance state and is relinquishing the bus. HACK is driven high
asynchronously following HREQ being detected inactive, and then the ’C80 resumes driving the bus.
HREQ
I
Host request. An external device drives HREQ low to request ownership of the local memory bus. When
HREQ is high, the ’C80 owns and drives the bus. HREQ is synchronized internally to the ’C80’s internal
clock. Also, HREQ is used at reset to determine the power-up state of the MP. If HREQ is low at the rising
edge of RESET, the MP comes up running. If HREQ is high, the MP remains halted until the first interrupt
occurrence on EINT3.
REQ1, REQ0
O
Internal cycle request. REQ1 and REQ0 provide a two-bit code indicating the highest-priority memory cycle
request that is being received by the TC. External logic can monitor REQ1 and REQ0 to determine if it is
necessary to relinquish the local memory bus to the ’C80.
CLKIN
I
Input clock. CLKIN generates the internal ’C80 clocks to which all processor functions (except the frame
timers) are synchronous.
CLKOUT
O
Local output clock. CLKOUT provides a way to synchronize external circuitry to internal timings. All ’C80
output signals (except the VC signals) are synchronous to this clock.
EINT1, EINT2, EINT3
I
Edge-triggered interrupts. EINT1, EINT2 and EINT3 allow external devices to interrupt the master
processor (MP) on one of three interrupt levels (EINT1 is the highest priority). The interrupts are rising-edge
triggered. EINT3 also serves as an unhalt signal. If the MP is powered-up halted, the first rising edge on
EINT3 causes the MP to unhalt and fetch its reset vector (the EINT3 interrupt-pending bit is not set in this
case).
LINT4
I
Level-triggered interrupt. LINT4 provides an active-low level-triggered interrupt to the MP. Its priority falls
below that of the edge-triggered interrupts. Any interrupt request should remain low until it is recognized
by the ’C80.
RESET
I
Reset. RESET is driven low to reset the ’C80 (all processors). During reset, all internal registers are set
to their initial state and all outputs are driven to their inactive or high-impedance levels. During the rising
edge of RESET, the MP reset mode and the ’C80’s operating endian mode are determined by the levels
of HREQ and UTIME pins, respectively.
XPT2–XPT0
I
External packet transfer. XPT2–XPT0 are used by external devices to request a high-priority XPT by the
TC.
I/O
Emulation pins. EMU0 and EMU1 are used to support emulation host interrupts, special functions targeted
at a single processor, and multiprocessor halt-event communications.
TCK‡
I
Test clock. TCK provides the clock for the ’C80 IEEE-1149.1 logic, allowing it to be compatible with other
IEEE-1149.1 devices, controllers, and test equipment designed for different clock rates.
TDI‡
I
Test data input. TDI provides input data for all IEEE-1149.1 instructions and data scans of the ’C80.
TDO
TMS‡
O
Test data output. TDO provides output data for all IEEE-1149.1 instructions and data scans of the ’C80.
I
Test-mode select. TMS controls the IEEE-1149.1 state machine.
TRST§
I
Test reset. TRST resets the ’C80 IEEE-1149.1 module. When low, all boundary-scan logic is disabled,
allowing normal ’C80 operation.
HACK
SYSTEM CONTROL
EMULATION CONTROL
EMU0, EMU1‡
† I = input, O = output, Z = high-impedance
‡ This pin has an internal pullup and can be left unconnected during normal operation.
§ This pin has an internal pulldown and can be left unconnected during normal operation.
¶ For proper operation, all VDD and VSS pins must be connected externally.
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
TYPE†
VIDEO INTERFACE
CAREA0, CAREA1
O
Composite area. CAREA0 and CAREA1 define a special area such as an overscan boundary. This area
represents the logical OR of the internal horizontal and vertical area signals.
Composite blanking/vertical blanking. Each of CBLNK0/VBLNK0 and CBLNK1/VBLNK1 provides one of
two blanking functions, depending on the configuration of the CSYNC/HBLNK pin:
CBLNK0/VBLNK0,
CBLNK1/VBLNK1
O
Composite blanking disables pixel display/capture during both horizontal and vertical retrace periods
and is enabled when CSYNC is selected for composite-sync video systems.
Vertical blanking disables pixel display/capture during vertical retrace periods and is enabled when
HBLNK is selected for separate-sync video systems.
Following reset, CBLNK0/VBLNK0 and CBLNK1 / VBLNK1 are configured as CBLNK0 and CBLNK1,
respectively.
Composite sync/horizontal blanking. CSYNC0/HBLNK0 and CSYNC1/HBLNK1 can be programmed for
one of two functions:
CSYNC0/HBLNK0,
CSYNC1/HBLNK1
I/O/Z
Composite sync is for use on composite-sync video systems and can be programmed as an input,
output, or high-impedance signal. As an input, the ’C80 extracts horizontal and vertical sync information
from externally generated active-low sync pulses. As an output, the active-low composite-sync pulses
are generated from either external HSYNC and VSYNC signals or the ’C80’s internal video timers. In
the high-impedance state, the pin is neither driven nor allowed to drive circuitry.
Horizontal blank disables pixel display/capture during horizontal retrace periods in separate-sync
video systems and can be used as an output only.
Immediately following reset, CSYNC0/HBLNK0 and
high-impedance CSYNC0 and CSYNC1, respectively.
FCLK0, FCLK1
HSYNC0,
HSYNC1
SCLK0, SCLK1
VSYNC0,
VSYNC1
CSYNC1/HBLNK1
are
configured
as
I
Frame clock. FCLK0 and FCLK1 are derived from the external video system’s dotclock and are used to
drive the ’C80 video logic for frame timer 0 and frame timer 1.
I/O/Z
Horizontal sync. HSYNC0 and HSYNC1 control the video system. They can be programmed as input,
output, or high impedance signals. As an input, HSYNC synchronizes the video timer to externally
generated horizontal sync pulses. As an output, HSYNC is an active-low horizontal sync pulse generated
by the ’C80 on-chip frame timer. In the high-impedance state, the pin is not driven, and no internal
synchronization is allowed to occur. Immediately following reset, HSYNC0 and HSYNC1 are in the
high-impedance state.
I
Serial data clock. SCLK0 and SCLK1 are used by the ’C80 shift register transfer (SRT) controller to track
the VRAM tap point when using midline reload. SCLK0 and SCLK1 should be the same signals that clock
the serial register on the VRAMs controlled by frame timer 0 and frame timer 1, respectively.
I/O/Z
Vertical sync. VSYNC0 and VSYNC1 control the video system. They can be programmed as inputs,
outputs, or high-impedance signals. As inputs, VSYNCx synchronize the frame timer to externally
generated vertical-sync pulses. As outputs, VSYNCx are active-low vertical-sync pulses generated by the
’C80 on-chip frame timer. In the high-impedance state, the pin is not driven and no internal synchronization
is allowed to occur. Immediately following reset, VSYNCx is in the high-impedance state.
POWER
VSS¶
VDD¶
I
Ground. Electrical ground inputs
I
Power. Nominal 3.3-V power supply inputs
MISCELLANEOUS
NC
No connect serves as an alignment key or is for factory use and must be left unconnected.
† I = input, O = output, Z = high-impedance
‡ This pin has an internal pullup and can be left unconnected during normal operation.
§ This pin has an internal pulldown and can be left unconnected during normal operation.
¶ For proper operation, all VDD and VSS pins must be connected externally.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
architecture
Figure 1 shows the major components of the ’C80: the master processor (MP), the parallel digital signal
processors (PPs), the transfer controller (TC), and the IEEE-1149.1 emulation interface. Shared access to
on-chip RAM is achieved through the crossbar. Crossbar connections are represented by . Each PP can
perform three accesses per cycle through its local (L), global (G), and instruction (I) ports. The MP can access
two RAMs per cycle through its crossbar/data (C/D) and instruction (I) ports, and the TC can access one RAM
through its crossbar interface. Up to nine simultaneous accesses are supported in each cycle. Addresses can
be changed every cycle, allowing the crossbar matrix to be changed on a cycle-by-cycle basis. Contention
between processors for the same RAM in the same cycle is resolved by a round-robin priority scheme. In
addition to the crossbar, a 32-bit data path exists between the MP and the TC and VC. This allows the MP to
access TC control registers that are memory-mapped into the MP memory space.
The ’C80 has a 4G-byte address space as shown in Figure 2. The lower 32M bytes are used to address internal
RAM and memory-mapped registers.
14
POST OFFICE BOX 1443
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
architecture (continued)
ADSP3
ADSP2
ADSP1
ADSP0
MP
VC
OCR
L G
I
32
64
L G
I
32
64
32
L G
I
32
64
32
L G
I
32
C/D
I
64
32
32
32
IEEE1149.1
(JTAG)
32
64
64
L
G
I
C/D
Instruction Cache
Data Cache
Instruction Cache
Data Cache
Parameter RAM
Data RAM0
Instruction Cache
Data RAM1
Data RAM2
Parameter RAM
Instruction Cache
Data RAM0
Data RAM1
Data RAM2
Parameter RAM
Data RAM0
Instruction Cache
Data RAM1
Data RAM2
Parameter RAM
Data RAM0
Instruction Cache
Data RAM1
Data RAM2
Parameter RAM
64
TC
Local port
Global port
Instruction port
Crossbar/data port
Figure 1. Block Diagram Showing Data Paths
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
architecture (continued)
0xFFFFFFFF
ADSP3 Parameter RAM
(2K bytes)
Reserved
(2K bytes)
ADSP2 Parameter RAM
(2K bytes)
External Memory
(4064M bytes)
Reserved
(2K bytes)
ADSP1 Parameter RAM
(2K bytes)
Reserved
(8063K bytes)
Memory-Mapped VC Registers
(512 bytes)
Memory-Mapped TC Registers
(512 bytes)
Reserved
(28K bytes)
MP Instruction Cache
(4K bytes)
Reserved
(28K bytes)
MP Data Cache
(4K bytes)
Reserved
(32K bytes)
ADSP3 Instruction Cache
(2K bytes)
Reserved
(6K bytes)
ADSP2 Instruction Cache
(2K bytes)
Reserved
(6K bytes)
ADSP1 Instruction Cache
(2K bytes)
Reserved
(6K bytes)
ADSP0 Instruction Cache
(2K bytes)
Reserved
(2K bytes)
0x02000000
0x01FFFFFF
0x01820400
0x018203FF
ADSP0 Parameter RAM
(2K bytes)
ADSP3 Data RAM2
(2K bytes)
0x01820000
0x0181FFFF
Reserved
(2K bytes)
0x01819000
0x01818FFF
ADSP2 Data RAM2
(2K bytes)
0x01818000
0x01817FFF
Reserved
(2K bytes)
0x01811000
0x01810FFF
ADSP1 Data RAM2
(2K bytes)
0x01810000
0x0180FFFF
Reserved
(2K bytes)
0x01808000
0x01807FFF
ADSP0 Data RAM2
(2K bytes)
0x01807800
0x018077FF
0x01805800
0x018057FF
ADSP3 Data RAM1
(2K bytes)
0x01804000
0x01803FFF
ADSP3 Data RAM0
(2K bytes)
0x01803800
0x018037FF
ADSP2 Data RAM1
(2K bytes)
0x01802000
0x01801FFF
ADSP2 Data RAM0
(2K bytes)
0x01801800
0x018017FF
ADSP1 Data RAM1
(2K bytes)
ADSP1 Data RAM0
(2K bytes)
0x01010800
0x010107FF
ADSP0 Data RAM1
(2K bytes)
0x01010000
0x0100FFFF
ADSP0 Data RAM0
(2K bytes)
0x01003800
Figure 2. Memory Map
POST OFFICE BOX 1443
0x01002800
0x010027FF
0x01002000
0x01001FFF
0x01001800
0x010017FF
0x01001000
0x01000FFF
0x01000800
0x010007FF
0x01000000
0x00FFFFFF
0x0000B800
0x0000B7FF
0x0000B000
0x0000AFFF
0x0000A800
0x0000A7FF
0x0000A000
0x00009FFF
0x00009800
0x000097FF
0x00009000
0x00008FFF
0x00008800
0x000087FF
0x00008000
0x00007FFF
Reserved
(16K bytes)
0x01806000
0x01805FFF
Registers
(50K bytes)
16
0x01003000
0x01002FFF
Reserved
(16338K bytes)
0x01820200
0x018201FF
Registers
(8132K bytes)
MP Parameter RAM
(2K bytes)
0x010037FF
• HOUSTON, TEXAS 77251–1443
0x00004000
0x00003FFF
0x00003800
0x000037FF
0x00003000
0x00002FFF
0x00002800
0x000027FF
0x00002000
0x00001FFF
0x00001800
0x000017FF
0x00001000
0x00000FFF
0x00000800
0x000007FF
0x00000000
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
master processor (MP) architecture
The master processor (MP) is a 32-bit RISC processor with an integral IEEE-754 floating-point unit. The MP
is designed for effective execution of C code and is capable of performing at well over 130000 dhrystones/s.
Major tasks which the MP typically performs are:
D Task control and user interface
D Information processing and analysis
D IEEE-754 floating point (including graphics transforms)
MP functional block diagram
Figure 3 shows a block diagram of the master processor. Key features of the MP include:
D 32-bit RISC processor
–
Load/store architecture
–
Three operand arithmetic and logical instructions
D 4K-byte instruction cache and 4K-byte data cache
D
D
D
D
D
D
D
D
–
Four-way set associative
–
Least-recently-used (LRU) information replacement
–
Data writeback
4K-byte noncached parameter RAM
Thirty-one 32-bit general-purpose registers
Register and accumulator scoreboard
15-bit or 32-bit immediate constants
32-bit byte addressing
Scalable timer
Leftmost-one and rightmost-one logic
IEEE-754 floating-point hardware
–
Four double-precision floating-point vector accumulators
–
Vector floating-point instructions
Floating-point operation and parallel load or store
Multiply and accumulate
D High performance
–
50 million instructions per second (MIPS)
–
100 million floating-point operations per second (MFLOPS)
–
Over 130000 dhrystones/s
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP functional block diagram (continued)
Register File
(Thirty-One 32-Bit Registers)
Scoreboard
Barrel Rotator
Mask Generator
Double-Precision
Floating-Point Multiplier
(Single-Precision Core)
Zero Comparator
Integer Arithmetic and
Logic Unit (ALU)
Leftmost/Rightmost One
Double-Precision Floating-Point
Accumulators
Timer
Control Registers
Double-Precision
Floating-Point Adder
Instruction Register
Program Counters (PCs)
PC Incrementer
Emulation Logic
Endian Multiplexers
Instruction Cache
Controller
Data-Cache
Controller
Crossbar Interface
Figure 3. MP Block Diagram
MP general-purpose registers
The MP contains 31 32-bit general-purpose registers, R1–R31. Register R0 always reads as zero and writes
to it are discarded. Double-precision values are always stored in an even-odd register pair with the
higher-numbered register always holding the sign bit and exponent. The R0/R1 pair is not available for this use.
A scoreboard keeps track of which registers are awaiting loads or the result of a previous instruction and stalls
the instruction pipeline until the register contains valid data. As a recommended software convention, R1 is
typically used as a stack pointer and R31 as a return-address link register.
Figure 4 shows the MP general-purpose registers.
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP general-purpose registers (continued)
Zero/Discard
Not Available
R1
R2
R2 R3
R2,
R3
R4
R4 R5
R4,
R5
•
•
•
•
•
•
R30
R30 R31
R30,
R31
32-Bit Registers
64-Bit Register Pairs
Figure 4. MP General-Purpose Registers
The 32-bit registers can contain signed-integer, unsigned-integer, or single-precision floating-point values.
Signed and unsigned bytes and halfwords are sign-extended or zero-filled. Doublewords can be stored in a
64-bit even/odd register pair. Double-precision floating-point values are referenced using the even register
number or the register pair. Figure 5 through Figure 7 show the register data formats.
31
Si l P
i i
Single-Precision
Floating Point
22
0
S E E E E E E E E M M M M M M M M M M M M M M M M M M M M M M M
MS
LS
31
Si
d 32-bit
32 bit
Signed
Integer
S
0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
MS
I
I
I
I
I
I
I
I
I
0
U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U
LS
MS
S
E
M
I
U
MS
LS
I
LS
31
U i
d 32-Bit
32 Bit
Unsigned
Integer
I
Sign bit
Exponent
Value
Signed integer value
Unsigned integer value
Most significant
Least signficant
Figure 5. MP Register 32-Bit Data Formats
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19
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP general-purpose registers (continued)
31
Signed Byte
7
S S S S S S S S S S S S S S S S S S S S S S S S S
0
I
I
I
I
I
I
MS
31
Unsigned Byte
0
LS
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U U U U U U U U
MS
31
Signed Halfword
0
I
I
I
I
I
I
MS
31
U
i
d
Unsigned
Halfword
0
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
I
I
I
I
I
I
I
I
LS
0
U U U U U U U U U U U U U U U U
MS
S
I
U
MS
LS
LS
15
S S S S S S S S S S S S S S S S S
I
LS
Sign bit(s)
Signed byte/halfword value
Unsigned byte/halfword value
Most significant
Least signficant
Figure 6. MP Register 8-Bit and 16-Bit Data Formats
31
Odd Register
0
Most Significant 32-Bit Word
MS
31
Even Register
0
Least Significant 32-Bit Word
LS
31
Odd Register
19
0
S E E E E E E E E E E E M M M M M M M M M M M M M M M M M M M M
MS
31
Even Register
0
M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M
LS
S
E
I
U
MS
LS
Sign bit(s)
Exponent
Signed byte/halfword value
Unsigned byte/halfword value
Most significant
Least signficant
Figure 7. MP Register 64-Bit Data Formats
20
POST OFFICE BOX 1443
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP double-precision floating-point accumulators
There are four double-precision floating-point registers (see Figure 8) to accumulate intermediate floating-point
results.
63
0
a0
Accumulator 0
a1
Accumulator 1
a2
Accumulator 2
a3
Accumulator 3
MSB
S
E
M
MS
LS
LSB
Sign bit
Exponent
Value
Most significant
Least signficant
Figure 8. Double-Precision Floating-Point Accumulators
MP control registers
In addition to the general-purpose registers, there are a number of control registers that are used to represent
the state of the processor. Table 1 shows the control register numbers of the accessible registers.
Table 1. Control Register Numbers
NUMBER
NAME
DESCRIPTION
NUMBER
NAME
0x0000
EPC
Exception Program Counter
0x0015–0x001F
—
0x0001
EIP
Exception Instruction Pointer
0x0020
SYSSTK
System Stack Pointer
0x0002
CONFIG
Configuration
0x0021
SYSTMP
System Temporary Register
0x0003
—
0x0022–0x002F
—
0x0004
INTPEN
Interrupt Pending Register
0x0030
MPC
Emulator Exception Program Counter
0x0005
—
Reserved
0x0031
MIP
Emulator Exception Instruction Pointer
0x0006
IE
Interrupt Enable Register
0x0032
—
0x0007
—
Reserved
0x0033
ECOMCNTL
0x0008
FPST
Floating-Point Status
0x0034
ANASTAT
0x0009
—
0x000A
PPERROR
0x000B
—
0x000C
—
Reserved
Reserved
DESCRIPTION
Reserved
Reserved
Reserved
Emulator Communication Control
Emulation Analysis Status Register
0x0035–0x0038
—
0x0039
BRK1
Emulation Breakpoint 1 Register
Reserved
0x003A
BRK2
Emulation Breakpoint 2 Register
Reserved
0x003B–0x01FF
—
0x0200 – 0x020F
iCACHET
Instruction Cache Tags 0 to 15
PP Error Register
Reserved
Reserved
0x000D
PKTREQ
Packet-Transfer Request
Register
0x000E
TCOUNT
Current Counter Value
0x0300
iCACHEL
Instruction Cache LRU Register
0x000F
TSCALE
Counter Reload Value
0x0010
FLTOP
0x0400–0x040F
dCACHET
Data Cache Tags 0 to 15
Faulting Operation
0x0500
dCACHEL
Data Cache LRU Register
0x0011
FLTADR
Faulting Address
0x4000
IN0P
Vector Load Pointer 0
0x0012
FLTTAG
Faulting Tag
0x4001
IN1P
Vector Load Pointer 1
0x0013
FLTDTL
Faulting Data (low)
0x4002
OUTP
Vector Store Pointer
0x0014
FLTDTH
Faulting Data (high)
POST OFFICE BOX 1443
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21
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP pipeline registers
The MP uses a three-stage fetch, execute, access (FEA) pipeline. The primary pipeline registers are
manipulated implicitly by branch and trap instructions and are not accessible by the user. The exception and
emulation pipeline registers are user-accessible as control registers. All pipeline registers are 32 bits.
Program Execution Mode
Normal
Exception
Emulation
PC
EPC
MPC
Instruction Pointer
IP
EIP
MIP
Instruction Register
IR
Program Counter
•
•
•
•
Instruction register (IR) contains the instruction being
executed.
Instruction pointer (IP) points to the instruction being
executed.
Program counter (PC) points to the instruction being
fetched.
•
Exception/emulator instruction pointer (EIP/MIP) points to the
instruction that would have been executed had the exception /
emulation trap not occurred.
Exception/emulator program counter (EPC/MPC) points to the
instruction to be fetched on returning from the exception/emulation
trap.
Figure 9. MP FEA Pipeline Registers
configuration (CONFIG) register (0x0002)
The CONFIG register controls or reflects the state of certain options as shown in Figure 10.
3
1
3
0
2
9
2
8
2
7
E
R
T
H
X
E
R
T
H
X
Type
Release
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
Reserved
1
6
1
5
1
4
1
3
1
2
Type
1
1
1
0
Reserved
Endian mode; 0 = big-endian, 1 = little-endian, read only
PPData RAM round robin; 0 = fixed, 1 = variable, read/write
TC packet transfer (PT) round robin; 0 = variable, 1 = fixed, read/write
High priority MP events; 0 = disabled, 1 = enabled, read/write
Externally initiated packet transfers; 0 = disabled, 1 = enabled, read/write
Number of PPs in device, read only
SMJ320C80 version number
Figure 10. CONFIG Register
22
POST OFFICE BOX 1443
9
• HOUSTON, TEXAS 77251–1443
8
7
6
5
Release
4
3
2
1
Reserved
0
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
interrupt-enable (IE) register (0x0006)
The IE register contains enable bits for each of the interrupts/traps as shown in Figure 11. The
global-interrupt-enable (ie) bit and the appropriate individual interrupt-enable bit must be set in order for an
interrupt to occur.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
p
e
x
4
x
3
b
p
p
b
p
c
m
i
pe
x4
x3
bp
pb
pc
mi
p3
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
p
3
p
2
p
1
p
0
i
o
m
f
PP error
External interrupt 4 (LINT4)
External interrupt 3 (EINT3)
Bad packet transfer
Packet transfer busy
Packet transfer complete
MP message interrupt
PP3 message interrupt
p2
p1
p0
io
mf
x2
x1
ti
1
3
1
2
1
1
1
0
9
8
7
6
5
x
2
x
1
ti
f
1
f
0
f
x
f
u
f
o
f1
f0
fx
fu
fo
fz
fi
ie
Frame-timer 1 interrupt
Frame-timer 0 interrupt
Floating-point inexact
Floating-point underflow
Floating-point overflow
Floating-point divide-by-zero
Floating-point invalid
Global-interrupt enable
PP2 message interrupt
PP1 message interrupt
PP0 message interrupt
Integer overflow
Memory fault
External interrupt 2 (EINT2)
External interrupt 1 (EINT1)
MP timer interrupt
4
3
2
fz
fi
1
0
ie
Figure 11. IE Register
interrupt-pending (INTPEN) register (0x0004)
The bits in INTPEN register show the current state of each interrupt/trap. Pending interrupts do not occur unless
the ie bit and corresponding interrupt-enable bit are set. Software must write a 1 to the appropriate INTPEN bit
to clear an interrupt. Figure 12 shows the INTPEN register locations.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
p
e
x
4
x
3
b
p
p
b
p
c
m
i
pe
x4
x3
bp
pb
pc
mi
p3
2
4
2
3
PP error
External interrupt 4 (LINT4)
External interrupt 3 (EINT3)
Bad packet transfer
Packet transfer busy
Packet transfer complete
MP message interrupt
PP3 message interrupt
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
p
3
p
2
p
1
p
0
i
o
m
f
p2
p1
p0
io
mf
x2
x1
ti
1
3
1
2
1
1
1
0
9
8
7
6
5
x
2
x
1
ti
f
1
f
0
f
x
f
u
f
o
f1
f0
fx
fu
fo
fz
fi
ie
Frame-timer 1 interrupt
Frame-timer 0 interrupt
Floating-point inexact
Floating-point underflow
Floating-point overflow
Floating-point divide-by-zero
Floating-point invalid
Global-interrupt enable
PP2 message interrupt
PP1 message interrupt
PP0 message interrupt
Integer overflow
Memory fault
External interrupt 2 (EINT2)
External interrupt 1 (EINT1)
MP timer interrupt
4
3
2
fz
fi
1
0
Figure 12. INTPEN Register
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
floating-point status (FPST) register (0x0008)
FPST contains status and control information for the floating-point unit (FPU) as shown in Figure 13. Bits 17–21
are read/write FPU control bits. Bits 22–26 are read/write accumulated status bits. All other bits show the status
of the last FPU instruction to complete and are read only.
0
1
2
dest
dest
ai
az
ao
au
ax
sm
fs
vm
drm
opcode
e1
3
.
4
0
0
1
0
0
2
ai
a
z
a
o
a
u
a
x
f
s
5
drm
0
3
0
.
0
4
0
opcode
0
0
e
1
e
0
0
1
pd
2
3
rm
The ninth MSB of exponent
Destination precision
00 – single float
01 – double float
Rounding mode
00 – nearest
01 – zero
Int multiply overflow
Invalid
Divide-by-zero
Overflow
Underflow
Inexact
e0
pd
Destination register value
Accumulated value invalid
Accumulated divide-by-zero
Accumulated overflow
Accumulated underflow
Accumulated inexact
Sequential mode select
Floating-point stall
Vector fast mode
Rounding mode
00 – nearest
10 – positive ∞
01 – zero
11 – negative ∞
Last opcode
The tenth MSB of exponent
0
rm
mo
i
z
o
u
x
.
4
0
i
z
o
u
x
10 – signed int
11 – unsigned int
10 – positive ∞
11 – negative ∞
Figure 13. FPST Register
PP error (PPERROR) register (0x000A)
The bits in the PPERROR register reflect parallel processor errors (see Figure 14). The MP can use these when
a PP error interrupt occurs to determine the cause of the error.
0
1
2
3
.
4
0
Reserved
PP#
h
I
f
0
1
0
1
0
0
2
0
3
h
h
h
h
3
2
1
0
0
.
0
4
0
0
0
0
i
i
i
i
PP#
3
2
1
0
Reserved
PPhalted
PP illegal instruction
PP fault type
icache
Direct external access (DEA)
Figure 14. PPERROR Register
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
0
1
2
3
.
4
f
f
f
f
PP#
3
2
1
0
Reserved
0
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
packet-transfer request (PKTREQ) register (0x000D)
PKTREQ controls the submission and priority of packet-transfer requests as shown in Figure 15. It also
indicates that a packet transfer is currently active.
0
1
2
3
.
4
0
0
1
0
0
2
0
3
0
.
0
4
0
0
0
0
0
1
2
3
.
Reserved
I
F
S
Q
P
4
0
I
F
S
Q
P
Immediate (urgent) priority selected
High (foreground) priority selected
Suspend packet transfer
Packet transfer queued; read only
Submit packet-transfer request
Figure 15. PKTREQ Register
memory-fault registers
The five read-only memory-fault registers contain information about memory address exceptions, as shown in
Figure 16.
FLTOP
(0x0010)
FLTTAG
(0x0011)
0
1
2
3
.
4
Dest
0
1
0
0
1
0
0
2
Reserved
2
3
.
4
0
0
3
0
.
0
4
K
0
1
0
0
2
0
SZ
0
3
0
.
0
4
0
0
0
0
0
1
i
d
x
r
0
0
0
0
1
2
3
.
4
P
D
P
D
P
D
P
D
22-Bit Cache Tag Address
2
3
.
4
Reserved
3
2
0
Block
1
0
0
Sub-Block
31
0
FLTADR
(0x0012)
Faulting Address Accessed by the Instruction
FLTDTH
(0x0013)
Faulting Write Most-Significant-Data Word
FLTDTL
(0x0014)
Faulting Write Least-Significant-Data Word
Dest
K
SZ
Destination Register Number
Kind of Operation:
00 – load
01 – unsigned load
10 – store
11 – cache flush/clean
Size of Data:
00 – 8-bit
01 – 16-bit
10 – 32-bit
11 – 64-bit
i
d
x
r
Block
P
D
MP icache fault
MP dcache fault
DEA Fault
Modified return sequence
Faulting block number
Sub-block is present.
Dirty bit set
Figure 16. Memory-Fault Registers
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP cache registers
The ILRU and DLRU registers track least-recently-used (LRU) information for the sixteen instruction-cache and
sixteen data-cache blocks. The ITAGxx registers contain block addresses and the present flags for each
sub-block. DTAGxx registers are identical to ITAGxx registers but include dirty bits for each sub-block. Figure 17
shows the cache registers.
ILRU (0x0300)
DLRU (0x0500)
0
MRU
1
NMRU
2
3
NLRU
.
4
LRU
MRU
0
NMRU
Set 3
0
1
0
NLRU
0
2
0
3
LRU
0
.
0
4
MRU
0
0
NMRU
Set 2
0
0
0
NLRU
1
LRU
2
3
MRU
.
4
NMRU
Set 1
NLRU
0
LRU
Set 0
ITAG0–ITAG15 (0x0200–0x020F)
0
1
2
3
.
4
0
0
1
0
0
2
0
3
0
.
0
4
0
0
0
0
0
22-Bit Cache Tag Address
1
P
2
3
P
3
.
4
P
2
0
0
P
1
0
Sub-Block
DTAG0–DTAG15 (0x0400–0x040F)
0
1
2
3
.
4
0
0
1
0
0
2
0
3
0
.
0
4
0
0
0
0
22-Bit Cache Tag Address
0
1
P
3
2
D
P
2
3
.
D
P
4
D
P
1
Sub-Block
MRU
NMRU
NLRU
Most-recently-used
Next most-recently-used
Next least-recently-used
LRU
P
D
Least-recently-used
Sub-block present
Sub-block dirty
mru, nmru, nlru, and lru have the value 0, 1, 2, or 3 representing the block number and are mutually exclusive for each set.
Figure 17. Cache Registers
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
D
0
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP cache architecture
The MP contains two four-way set-associative, 4K caches for instructions and data. Each cache is divided into
four sets with four blocks in each set. Each block represents 256 bytes of contiguous instructions or data and
is aligned to a 256-byte address boundary. Each block is partitioned into four sub-blocks that each contain
sixteen 32-bit words and are aligned to 64-byte boundaries within the block. Cache misses cause one sub-block
to be loaded into cache. Figure 18 shows the cache architecture for one of the four sets in each cache. Figure 19
shows how addresses map into the cache using the cache tags and address bits.
Block 0
Tag Reg 0 (Block 0)
Block 1
Tag Reg 1 (Block 1)
LRU in SET 0
Sub-Blocks
NLRU in SET 0
NMRU in SET 0
Set 0
Block 2
Tag Reg 2 (Block 2)
Block 3
Tag Reg 3 (Block 3)
MRU in SET 0
LRU Stack for SET 0
LRU
NLRU
NMRU
MRU
Least-recently-used
Next least-recently-used
Next most-recently-used
Most-recently-used
Figure 18. MP Cache Architecture (x4 Sets)
32-Bit Logical Address
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
2
1
0
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
S
S
s
s
W W W W
B
B
4
3
On-Chip MP 4K Cache RAMS
Bank 0
Bank 1
Set 0
Set 2
Set 1
Set 3
11 10 9 8 7 6 5 4 3 2 1 0
S S A A s s W W W W B B
Address in On-Chip
Cache Bank
T – Tag Address Bits
s – Sub-Block (within block) Select (0–3)
B – Byte (within word) Select (0–3)
S – Set Select Bits (0–3)
W – Word (within sub-block) Select (0–15)
A – Block Select (which tag matched) (0–3)
Figure 19. MP Cache Addressing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP parameter RAM
The parameter RAM is a noncachable, 2K-byte, on-chip RAM that contains MP interrupt vectors, MP-requested
TC task buffers, and a general-purpose area. Figure 20 shows the parameter RAM address map.
0x001010000–0x0101007F
Suspended PT Parameters
(128 Bytes)
0x001010800–0x010100DF
Reserved
(64 Bytes)
0x0010100E0–0x010100FB
XPT Linked List Start Addresses
(60 Bytes)
0x0010100FC–0x010100FF
MP Linked List Start Address
0x001010100–0x0101017F
Off-Chip to Off-Chip PT Buffer
(128 Bytes)
0x001010180–0x0101021F
Interrupt and Trap Vectors
(160 Bytes)
0x001010220–0x0101029F
0x0010102A0–0x010107FF
XPTf Linked List Start Add.
XPTe Linked List Start Add.
XPTd Linked List Start Add.
XPTc Linked List Start Add.
XPTb Linked List Start Add.
XPTa Linked List Start Add.
XPT9 Linked List Start Add.
XPT8 Linked List Start Add.
XPT7 Linked List Start Add.
0x010100E0
XPT6 Linked List Start Add.
0x010100E4
XPT Off-Chip to Off-Chip PT Buffer
(128 Bytes)
XPT5 Linked List Start Add.
0x010100E8
XPT4 Linked List Start Add.
0x010100EC
General-Purpose RAM
(3472 Bytes)
XPT3 Linked List Start Add.
0x010100F0
XPT2 Linked List Start Add.
0x010100F4
XPT1 Linked List Start Add.
0x010100F8
Figure 20. MP Parameter RAM
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP interrupt vectors
Table 2 and Table 3 show the MP interrupts and traps and their vector addresses.
Table 2. Maskable Interrupts
IE BIT
(TRAP#)
NAME
VECTOR
ADDRESS
0
ie
0x01010180
2
fi
0x01010188
Floating-point invalid
3
fz
0x0101018C
Floating-point divide-by-zero
5
fo
0x01010194
Floating-point overflow
6
fu
0x01010198
Floating-point underflow
7
fx
0x0101019C
Floating-point inexact
8
f0
0x010101A0
Reserved
9
f1
0x010101A4
Reserved
MASKABLE INTERRUPT
10
ti
0x010101A8
MP timer interrupt
11
x1
0x010101AC
External interrupt 1 (EINT1)
12
x2
0x010101B0
External interrupt 2 (EINT2)
14
mf
0x010101B8
Memory fault
15
io
0x010101BC
Integer overflow
16
p0
0x010101C0
PP0 message interrupt
17
p1
0x010101C4
PP1 message interrupt
18
p2
0x010101C8
Reserved
19
p3
0x010101CC
Reserved
25
mi
0x010101E4
MP message interrupt
26
pc
0x010101E8
Packet-transfer complete
27
pb
0x010101EC
Packet-transfer busy
28
bp
0x010101F0
Bad packet transfer
29
x3
0x010101F4
External interrupt 3 (EINT3)
30
x4
0x010101F8
External interrupt 4 (LINT4)
31
pe
0x010101FC
PP error
Table 3. Nonmaskable Traps
TRAP
NUMBER
NAME
VECTOR
ADDRESS
32
e1
0x01010200
Emulator trap1 (reserved)
33
e2
0x01010204
Emulator trap2 (reserved)
34
e3
0x01010208
Emulator trap3 (reserved)
35
e4
0x0101020C
Emulator trap4 (reserved)
36
fe
0x01010210
Floating-point error
0x01010214
Reserved
0x01010218
Illegal MP instruction
39
0x0101021C
Reserved
72
to
415
0x010102A0 to
0x010107FC
37
38
er
POST OFFICE BOX 1443
NONMASKABLE TRAP
System- or user-defined
• HOUSTON, TEXAS 77251–1443
29
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode formats
The three basic classes of MP instruction opcodes are: short immediate, three register, and long immediate.
Figure 21 shows the opcode structure for each class of instruction.
31
Short
Immediate
27 26
Dest
31
Three
Register
Dest
Source 2
1
1
15-Bit Immediate
13 12 11
1
Opcode
22 21 20 19
Source 2
0
Opcode
22 21 20 19
27 26
Dest
15 14
Source 2
27 26
31
Long
Immediate
22 21
0
5 4
Options
13 12 11
1
Opcode
1
0
Source 1
5 4
Options
0
Source 1
32-Bit Long Immediate
Figure 21. MP Opcode Formats
MP opcode summary
Table 4 through Table 6 show the opcode formats for the MP. Table 7 summarizes the master processor
instruction set.
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 4. Short-Immediate Opcodes
3
1
3
0
trap
–
–
cmnd
–
–
illop0
2
9
2
8
2
7
2
6
2
5
–
–
E
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Dest
swcr
Dest
brcr
–
–
–
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
0
0
0
0
0
0
0
Unsigned Immediate
0
0
0
0
0
0
1
Unsigned Trap Number
–
0
0
0
0
0
1
0
Unsigned Immediate
–
0
0
0
0
1
0
0
Unsigned Control Register Number
0
0
0
0
1
0
1
Unsigned Control Register Number
Source
Dest
rdcr
2
4
Source
–
–
–
–
–
–
–
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
0
0
0
1
1
0
shift.dz
Dest
Source
0
0
0
1
0
0
0
–
–
–
i
n
Endmask
Rotate
shift.dm
Dest
Source
0
0
0
1
0
0
1
–
–
–
i
n
Endmask
Rotate
shift.ds
Dest
Source
0
0
0
1
0
1
0
–
–
–
i
n
Endmask
Rotate
shift.ez
Dest
Source
0
0
0
1
0
1
1
–
–
–
i
n
Endmask
Rotate
shift.em
Dest
Source
0
0
0
1
1
0
0
–
–
–
i
n
Endmask
Rotate
shift.es
Dest
Source
0
0
0
1
1
0
1
–
–
–
i
n
Endmask
Rotate
shift.iz
Dest
Source
0
0
0
1
1
1
0
–
–
–
i
n
Endmask
Rotate
–
–
–
i
n
Endmask
Rotate
Dest
Source
0
0
0
1
1
1
1
and.tt
Dest
Source2
0
0
1
0
0
0
1
Unsigned Immediate
and.tf
Dest
Source2
0
0
1
0
0
1
0
Unsigned Immediate
and.ft
Dest
Source2
0
0
1
0
1
0
0
Unsigned Immediate
xor
Dest
Source2
0
0
1
0
1
1
0
Unsigned Immediate
or.tt
Dest
Source2
0
0
1
0
1
1
1
Unsigned Immediate
and.ff
Dest
Source2
0
0
1
1
0
0
0
Unsigned Immediate
xnor
Dest
Source2
0
0
1
1
0
0
1
Unsigned Immediate
or.tf
Dest
Source2
0
0
1
1
0
1
1
Unsigned Immediate
or.ft
Dest
Source2
0
0
1
1
1
0
1
Unsigned Immediate
or.ff
Dest
Source2
0
0
1
1
1
1
0
Unsigned Immediate
ld
Dest
Base
0
1
0
0
M
SZ
Signed Offset
ld.u
Dest
Base
0
1
0
1
M
SZ
Signed Offset
Base
0
1
1
0
M
SZ
Signed Offset
Source2
0
1
1
1
M
st
–
A
E
F
i
Source
–
–
–
–
F
–
–
–
–
–
0
0
Signed Offset
bsr
Link
1
0
0
0
0
0
A
Signed Offset
jsr
Link
Base
1
0
0
0
1
0
A
Signed Offset
bbz
BITNUM
Source
1
0
0
1
0
0
A
Signed Offset
bbo
BITNUM
Source
1
0
0
1
0
1
A
Signed Offset
bcnd
Cond
Source
1
0
0
1
1
0
A
Signed Offset
cmp
Dest
Source2
1
0
1
1
0
0
0
Signed Immediate
add
Dest
Source2
1
0
1
1
0
0
U
Signed Immediate
sub
Dest
Source2
1
0
1
1
0
1
U
Signed Immediate
Reserved bit (code as 0)
Annul delay slot instruction if branch taken
Emulation trap bit
Clear present flags
Invert endmask
POST OFFICE BOX 1443
0
0
Unsigned Control Register Number
shift.im
dcache
0
1
M
n
SZ
U
Modify, write modified address back to register
Rotate sense for shifting
Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword)
Unsigned form
• HOUSTON, TEXAS 77251–1443
31
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 5. Long-Immediate and Three-Register Opcodes
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
trap
–
–
–
–
E
–
–
–
–
–
1
1
0
0
0
0
0
0
1
I
–
–
–
–
–
–
–
IND TR
cmnd
–
–
–
–
–
–
–
–
–
–
1
1
0
0
0
0
0
1
0
I
–
–
–
–
–
–
–
Source1
–
–
–
–
–
1
1
0
0
0
0
1
0
0
I
–
–
–
–
–
–
–
IND CR
1
1
0
0
0
0
1
0
1
I
–
–
–
–
–
–
–
IND CR
1
1
0
0
0
0
1
1
0
I
–
–
–
–
–
–
–
IND CR
rdcr
Dest
swcr
Dest
brcr
–
–
–
Source
–
–
–
–
–
–
–
0
4
0
3
0
2
0
1
shift.dz
Dest
Source
1
1
0
0
0
1
0
0
0
I
i
n
Endmask
Rotate
shift.dm
Dest
Source
1
1
0
0
0
1
0
0
1
I
i
n
Endmask
Rotate
shift.ds
Dest
Source
1
1
0
0
0
1
0
1
0
I
i
n
Endmask
Rotate
shift.ez
Dest
Source
1
1
0
0
0
1
0
1
1
I
i
n
Endmask
Rotate
shift.em
Dest
Source
1
1
0
0
0
1
1
0
0
I
i
n
Endmask
Rotate
shift.es
Dest
Source
1
1
0
0
0
1
1
0
1
I
i
n
Endmask
Rotate
shift.iz
Dest
Source
1
1
0
0
0
1
1
1
0
I
i
n
Endmask
Rotate
shift.im
Dest
Source
1
1
0
0
0
1
1
1
1
I
i
n
Endmask
Rotate
and.tt
Dest
Source2
1
1
0
0
1
0
0
0
1
I
–
–
–
–
–
–
–
Source1
and.tf
Dest
Source2
1
1
0
0
1
0
0
1
0
I
–
–
–
–
–
–
–
Source1
and.ft
Dest
Source2
1
1
0
0
1
0
1
0
0
I
–
–
–
–
–
–
–
Source1
xor
Dest
Source2
1
1
0
0
1
0
1
1
0
I
–
–
–
–
–
–
–
Source1
or.tt
Dest
Source2
1
1
0
0
1
0
1
1
1
I
–
–
–
–
–
–
–
Source1
and.ff
Dest
Source2
1
1
0
0
1
1
0
0
0
I
–
–
–
–
–
–
–
Source1
xnor
Dest
Source2
1
1
0
0
1
1
0
0
1
I
–
–
–
–
–
–
–
Source1
or.tf
Dest
Source2
1
1
0
0
1
1
0
1
1
I
–
–
–
–
–
–
–
Source1
or.ft
Dest
Source2
1
1
0
0
1
1
1
0
1
I
–
–
–
–
–
–
–
Source1
or.ff
Dest
Source2
1
1
0
0
1
1
1
1
0
I
–
–
–
–
–
–
–
Source1
ld
Dest
Base
1
1
0
1
0
0
M
SZ
I
S
D
–
–
–
–
–
Offset
ld.u
Dest
Base
1
1
0
1
0
1
M
SZ
I
S
D
–
–
–
–
–
Offset
Source
Base
1
1
0
1
1
0
M
SZ
I
S
D
–
–
–
–
–
Offset
1
1
0
1
1
1
M
0
0
I
0
0
–
–
–
–
–
Source
1
1
1
0
0
0
0
0
A
I
–
–
–
–
–
–
–
Offset
st
dcache
bsr
–
D
E
F
i
32
–
–
–
–
F
Link
Source2
–
–
–
–
–
jsr
Link
Base
1
1
1
0
0
0
1
0
A
I
–
–
–
–
–
–
–
Offset
bbz
BITNUM
Source
1
1
1
0
0
1
0
0
A
I
–
–
–
–
–
–
–
Target
bbo
BITNUM
Source
1
1
1
0
0
1
0
1
A
I
–
–
–
–
–
–
–
Target
bcnd
Cond
Source
1
1
1
0
0
1
1
0
A
I
–
–
–
–
–
–
–
Target
cmp
Dest
Source2
1
1
1
0
1
0
0
0
0
I
–
–
–
–
–
–
–
Source1
add
Dest
Source2
1
1
1
0
1
1
0
0
U
I
–
–
–
–
–
–
–
Source1
sub
Dest
Source2
1
1
1
0
1
1
0
1
U
I
–
–
–
–
–
–
–
Source1
Reserved bit (code as 0)
Direct external access bit
Emulation trap bit
Clear present flags
Invert endmask
l
M
n
S
SZ
POST OFFICE BOX 1443
0
0
Long immediate
Modify, write modified address back to register
Rotate sense for shifting
Scale offset by data size
Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 6. Miscellaneous Instruction Opcodes
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
vadd
Mem Src/Dst
Source2/Dest
1
1
1
1
0
–
0
0
0
I
–
m P
–
d
m
s
Source1
vsub
Mem Src/Dst
Source2/Dest
1
1
1
1
0
–
0
0
1
I
–
m P
–
d
m
s
Source1
vmpy
Mem Src/Dst
Source2/Dest
1
1
1
1
0
–
0
1
0
I
–
m P
–
d
m
s
Source1
vmsub
Mem Src/Dst
Dest
1
1
1
1
0
a
0
1
1
I
a
m P
Z
–
m
–
Source1
vrnd(FP)
Mem Src/Dst
Dest
1
1
1
1
0
a
1
0
0
I
a
m P
m
s
Source1
vrnd(Int)
Mem Src/Dst
Dest
1
1
1
1
0
–
1
0
1
I
–
m P
–
d
m
s
Source1
vmac
Mem Src/Dst
Source2
1
1
1
1
0
a
1
1
0
I
a
m P
Z
–
m
–
Source1
vmac
Mem Src/Dst
Source2
1
1
1
1
0
a
1
1
1
I
a
m P
Z
–
m
–
Source1
fadd
Dest
Source2
1
1
1
1
1
0
0
0
0
I
–
PD
P2
P1
Source1
fsub
Dest
Source2
1
1
1
1
1
0
0
0
1
I
–
PD
P2
P1
Source1
fmpy
Dest
Source2
1
1
1
1
1
0
0
1
0
I
–
PD
P2
P1
Source1
fdiv
Dest
Source2
1
1
1
1
1
0
0
1
1
I
–
PD
P2
P1
Source1
frndx
Dest
–
1
1
1
1
1
0
1
0
0
I
–
PD
RM
P1
Source1
1
1
1
1
1
0
1
0
1
I
–
–
P2
P1
Source1
–
1
1
1
1
1
0
1
1
1
I
–
PD
P1
Source1
–
–
–
–
–
–
Source2
PD
0
0
fcmp
Dest
fsqrt
Dest
lmo
Dest
Source
1
1
1
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
rmo
Dest
Source
1
1
1
1
1
1
0
0
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
estop
–
–
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
illopF
–
–
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
C
–
–
–
–
–
–
–
–
–
–
–
–
–
a
C
d
l
m
Mem Src/Dst
Dest
Reserved bit (code as 0)
Floating-point accumulator select
Constant operands rather than register
Destination precision for vector (0 = sp, 1 = dp)
Long immediate 32-bit data
Parallel memory operation specifier
Vector store or load source/dst register
Destination register
POST OFFICE BOX 1443
P
P1
P2
PD
RM
S
Z
Destination precision for parallel load/store (0 = single, 1 = double)
Precision of source1 operand
Precision of source2 operand
Precision of destination result
Rounding Mode (0 = N, 1 = Z, 2 = P, 3 = M)
Scale offset by data size
Use 0 rather than accumulator
• HOUSTON, TEXAS 77251–1443
33
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 7. Summary of MP Opcodes
INSTRUCTION
add
INSTRUCTION
DESCRIPTION
Signed integer add
or.ff
Bitwise OR with 1s complement
and.tt
Bitwise AND
or.ft
Bitwise OR with 1s complement
and.ff
Bitwise AND with 1s complement
or.tf
Bitwise OR with 1s complement
and.ft
Bitwise AND with 1s complement
rdcr
Read control register
and.tf
Bitwise AND with 1s complement
rmo
Rightmost one
bbo
Branch bit one
shift.dz
Shift, disable mask, zero extend
bbz
Branch bit zero
shift.dm
Shift, disable mask, merge
bcnd
Branch conditional
shift.ds
Shift, disable mask, sign extend
Branch always
shift.ez
Shift, enable mask, zero extend
brcr
Branch control register
shift.em
Shift, enable mask, merge
bsr
br
Branch and save return
shift.es
Shift, enable mask, sign extend
cmnd
Send command
shift.iz
Shift, invert mask, zero extend
cmp
Integer compare
shift.im
Shift, invert mask, merge
dcache
Flush data cache sub-block
st
Store register into memory
estop
Emulation stop
sub
Signed integer subtract
fadd
Floating-point add
swcr
Swap control register
fcmp
Floating-point compare
trap
Trap
Floating-point divide
vadd
Vector floating-point add
fmpy
Floating-point multiply
vmac
Vector floating-point multiply and add to
accumulator
frndx
Floating-point convert/round
vmpy
Vector floating-point multiply
fsqrt
Floating-point square root
vmsc
Vector floating-point multiply and subtract
from accumulator
fsub
Floating-point subtract
vmsub
Vector floating-point subtract accumulator
from source
illop
Illegal operation
vrnd(FP)
Vector round with floating-point input
jsr
Jump and save return
vrnd(Int)
Vector round with integer input
ld
Load signed into register
vsub
Vector floating-point subtract
ld.u
Load unsigned into register
xnor
Bitwise exclusive NOR
lmo
Leftmost one
xor
Bitwise exclusive OR
or.tt
Bitwise OR
fdiv
34
DESCRIPTION
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP architecture
The parallel processor (PP) is a 32-bit integer DSP optimized for imaging and graphics applications. Each PP
can execute in parallel: a multiply, ALU operation, and two memory accesses within a single instruction. This
internal parallelism allows a single PP to achieve over 500 million operations per second for certain algorithms.
The PP has a three-input ALU that supports all 256 three input Boolean combinations and many combinations
of arithmetic and Boolean functions. Data-merging and bit-to-byte, bit-to-word, and bit-to-halfword translations
are supported by hardware in the input data path to the ALU. Typical tasks performed by a PP include:
D Pixel-intensive processing
–
Motion estimation
–
Convolution
–
PixBLTs
–
Warp
–
Histogram
–
Mean square error
D Domain transforms
–
Discrete Cosine Transform (DCT)
–
Fast Fourier Transform (FFT)
–
Hough
D Core graphics functions
–
Line
–
Circle
–
Shaded fills
–
Fonts
D Image analysis
–
Segmentation
–
Feature extraction
D Bit-stream encoding/decoding
–
Data merging
–
Table look-ups
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP functional block diagram
Figure 22 shows a block diagram of a parallel processor. Key features of the PP include:
D 64-bit instruction word (supports multiple parallel operations)
D Three-stage pipeline for fast instruction cycle
D Numerous registers
–
8 data, 10 address, 6 index registers
–
20 other user-visible registers
D Data Unit
–
16 x 16 integer multiplier (optional dual 8 x 8)
–
Splittable 3-input ALU
–
32-bit barrel rotator
–
Mask generator
–
Multiple status flag expander for translations to/from 1 bit-per-pixel space.
–
Conditional assignment of data unit results
–
Conditional source selection
–
Special processing hardware
Leftmost one/rightmost one
Leftmost bit change/rightmost bit change
D Memory addressing
–
Two address units (global and local) provide up to two 32-bit accesses in parallel with data unit
operation.
–
12 addressing modes (immediate and indexed)
–
Byte, halfword, and word addressability
–
Scaled indexed addressing
–
Conditional assignment for loads
–
Conditional source selection for stores
D Program flow
–
Three hardware loop controllers
Zero overhead looping/branching
Nested loops
Multiple loop endpoints
–
Instruction cache management
–
PC mapped to register file
–
Interrupts for messages and context switching
D Algebraic assembly language
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP functional block diagram (continued)
Data Unit
d0–d7
Multiplier
Data Path
ALU Data Path
Expander
Mask Generator
Barrel Rotator
Three-Input ALU
mf and sr
Registers
Figure 22. PP Block Diagram
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
37
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP registers
The PP contains many general-purpose registers, status registers, and configuration registers. All PP registers
are 32-bit registers. Figure 23 shows the accessible registers of the PP blocks.
Data-Unit Registers
Data Registers
Multiple Flags
Status
d0/EALU Operation
mf
sr
d1
d2
d3
d4
d5
d6
d7
Address-Unit Registers
Global-Address Unit
Address Registers
Index Flags
Local-Address Unit
Address Registers
Index Flags
a8
x8
a0
x0
a9
x9
a1
x1
a10
x10
a2
x2
a11
a3
a12
a14/sp
a15 = 0
a4
Stack Pointer
Same Physical
Register
Program Flow Control (PFC) Unit Registers
PC-Related Registers
Loop Addresses
a6/sp
a7 = 0
Loop Counts
Communications
pc (br, call)
ls0
lr0
comm
iprs
ls1
lr1
Interrupts
ipa (read only)
ls2
lr2
lntflg
ipe (read only)
le0
lc0
inten
Cache Tags
le1
lc1
tag0 (read only)
le2
lc2
tag1 (read only)
tag2 (read only)
Loop Control
tag3 (read only)
lctl
Figure 23. PP Registers
38
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP data-unit registers
The data unit contains eight 32-bit general-purpose data registers (d0–d7) referred to as the D registers. The
d0 register also acts as the control register for extended ALU (EALU) operations.
d0 register
Figure 24 shows the format when d0 is used as the EALU control register.
31
30
29
28
FMOD
FMOD
A
C
I
S
N
27
26
A
25
24
23
22
21
20
19
EALU Function Code
18
17
16
15
14
13
12
11
10
9
C
I
S
N
E
F
T
–
–
DMS
E
F
DMS
M
R
DBR
Function modifiers
Arithmetic enable
EALU carry-In
Invert-carry-In
Sign extend
Nonmultiple mask
8
7
6
5
4
3
M R U
2
1
0
DBR
Explicit multiple carry-in
Expanded multiple flags
Default multiply shift amount
Split multiply
Rounded multiply
Default barrel rotate amount
Figure 24. d0 Format for EALU Operations
multiple flags (mf) register
The mf register records status information from each split ALU segment for multiple arithmetic operations. The
mf register can be expanded to generate a mask for the ALU. Figure 25 shows the mf register format.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
7
6
5
6
5
4
3
2
4
3
2
1
0
1
0
Figure 25. mf Register Format
status register (sr)
The sr contains status and control bits for the PP ALU. See Figure 26.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
N C
V
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MSS
N
C
V
Z
R
Negative status bit
Carry status bit
Overflow status bit
Zero status bit
Rotation bit
MSS
Msize
Asize
R
Msize
Asize
mf status selection
00 – set by zero 10 – set by extended result
01 – set by sign 11 – reserved
Expander data size
Split ALU data size
Figure 26. sr Format
PP address-unit registers
address registers
The address unit contains ten 32-bit address registers which contain the base address for address
computations or which can be used for general-purpose data. The registers a0 – a4 are used for local-address
computations and registers a8–a12 are used for global-address computations.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
index registers
The six 32-bit index registers contain index values for use with the address registers in address computations
or they can be used for general-purpose data. Registers x0–x3 are used by the local-address unit and registers
x8–x9 are used by the global-address unit.
stack pointer (sp)
The sp contains the address of the top of the PP’s system stack. The stack pointer is addressed as a6 by the
local-address unit and as a14 by the global-address unit. Figure 27 shows the sp register format.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Word-Aligned Address
1
0
0
0
Figure 27. sp Register Format
zero registers
The zero registers are read-as-zero address registers for the local address unit (a7) and global-address unit
(a15). Writes to the registers are ignored and can be specified when operational results are to be discarded.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 28. Zero Registers
PP program flow control (PFC) unit registers
loop registers
The loop registers control three levels of zero-overhead loops. The 32-bit loop-start registers (ls0 – ls2) and
loop-end registers (le0 – le2) contain the starting and ending addresses for the loops. The loop-counter registers
(lc0 – lc2) contain the number of repetitions remaining in their associated loops. The lr0 – lr2 registers are loop
reload registers used to support nested loops. The format for the loop-control (lctl) register is shown in Figure 29.
There are also six special write-only mappings of the loop-reload registers. The lrs0 – lrs2 codes are used for
fast initialization of lsn, lrn, and lcn registers for multi-instruction loops while the lrse0 – lrse2 codes are used
for single instruction-loop fast initialization.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
E
E
LCDn
Loop-end enable
Loop-counter designator
000 – None
010 – lc1
001 – lc0
011 – lc2
1xx – reserved
10
9
LCD2
le2
8
7
E
6
5
LCD1
le1
4
3
E
2
1
0
LCD0
le0
Figure 29. lctl Register
pipeline registers
The PFC unit contains a pointer to each stage of the PP pipeline. The pc contains the program counter which
points to the instruction being fetched. The ipa points to the instruction in the address stage of the pipeline and
the ipe points to the instruction in the execute stage of the pipeline. The instruction pointer
return-from-subroutine (iprs) register contains the return address for a subroutine call.
40
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
pipeline registers (continued)
31
30
29
28
27
26
25
24
23
22
21
pc
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
PC (29-Bit Doubleword Address)
G – Global Interrupt Enable
31
30
29
28
27
26
25
24
23
22
21
ipa
20
19
2
1
0
– G L
L – Loop Inhibit
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
32-Bit Copy of the Previous pc Register Value
31
30
29
28
27
26
25
24
23
22
ipe
21
20
19
18
17
16
15
14
13
12
11
10
32-Bit Copy of the Previous ipa Register Value
31
30
29
28
27
26
25
24
23
22
21
iprs
20
19
18
17
16
15
14
13
12
11
10
29-Bit Doubleword Return Address
2
1
0
–
–
–
Figure 30. Pipeline Registers
interrupt registers
The interrupt-enable (inten) register allows individual interrupts to be enabled and configures the interrupt flag
(intflg) register operation. The intflg register contains the interrupt flag bits. Interrupt priority increases moving
from left to right on intflg.
inten
intflg
31
30
29
28
r
r
r
r
27
24
23
22
21
20
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
E E E E
26
25
–
–
–
E E E E
–
–
E
–
–
–
–
–
–
–
–
–
–
–
–
– W
P P
P P
3 2
M M
S S
G G
P
P
1
M
S
G
P
P
0
M
S
G
19
18
M
P
M
S
G
P
T
E
N
D
P
T
E
R
R
P
T
Q
0
T
A
S
K
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
I
I
I
I
–
–
–
I
I
I
I
–
–
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
r
E
W
PPnMSG
Reserved (write as 0)
Enable interrupt
Write mode
0 – writing 1 clears intflg
1 – writing 1 sets intflg
PPn message interrupt
MPMSG
PTEND
PTERR
PTQ
TASK
MP message interrupt
Packet transfer complete
Packet-transfer error
Packet transfer queued
MP task interrupt
Figure 31. PP-Interrupt Registers
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
41
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
communication (comm) register
The comm register contains the packet-transfer handshake bits and PP indicator bits.
31
30
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
H
S Q P
29
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
H
S
Q
P
PP#
High-priority packet transfer
Packet-transfer suspend
Packet transfer queued
Submit packet transfer request
2
1
0
PP#
PP Number (read only)
000 – PP0 010 – PP2
001 – PP1 011 – PP3
1xx – Not implemented
Figure 32. comm Register
cache-tag registers
The tag0 – tag3 registers contain the tag address and sub-block present bits for each cache block.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
23-Bit Tag Address
P
LRU
8
7
6
5
4
3
2
1
P
P
P
P
–
–
–
LRU
3
2
1
0
Sub-Block #
Present bit
Least-recently-used code
00 – Most-recently-used (MRU)
10 – next LRU
01 – next MRU (NMRU)
11 – LRU
0
Figure 33. Cache-Tag Registers
PP cache architecture
Each PP has its own 2K-byte instruction cache. Each cache is divided into four blocks and each block is divided
into four sub-blocks containing 16 64-bit instructions each. Cache misses cause one sub-block to be loaded
into cache. Figure 34 shows the cache architecture for one of the four sets in each cache. Figure 35 shows how
addresses map into the cache using the cache tags and address bits.
Block 0
Tag 0 (Block 0)
Block 1
Tag 1 (Block 1)
Block 2
Tag 2 (Block 2)
Block 3
Tag 3 (Block 3)
LRU
Sub-Blocks
NLRU
NMRU
MRU
LRU Stack
Figure 34. PP Cache Architecture
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
23-Bit Tag Value
7
sub
6
5
4
instruction
sub – sub-block
Figure 35. PP Register Cache-Address Mapping
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3
2
1
0
ignored
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP parameter RAM
The parameter RAM is a 2K-byte, on-chip RAM which contains PP-interrupt vectors, PP-requested TC task
buffers, and a general-purpose area. The parameter RAM does not use the cache memory. Figure 35 shows
the parameter RAM address map.
Suspended PT Parameters
(128 Bytes)
0x0100#000–0x0100#07F
Reserved
(120 Bytes)
0x0100#080–0x0100#0F7
DEA / Cache Fault Address
0x0100#0F8–0x0100#0FB
PP Linked-List Start Address
0x0100#0FC–0x0100#0FF
Off-Chip to Off-Chip PT Buffer
(128 Bytes)
0x0100#100–0x0100#17F
Interrupt Vectors
(128 Bytes)
0x0100#180–0x0100#1FF
General-Purpose RAM
(3572 Bytes Less Stack Size)
0x0100#200
Application-Dependent Boundary
Stack
0x0100#FF7
Stack State Information After Reset
(12 Bytes)
Stack Pointer After Reset
0x0100#FF4–0x0100#FFF
# – PP Number
Figure 36. PP Parameter RAM Address Map
PP-interrupt vectors
The PP interrupts and their vector addresses are shown in Table 8.
Table 8. PP-Interrupt Vectors
NAME
VECTOR
ADDRESS
INTERRUPT
TASK
0x0100#1B8
Task Interrupt
PTQ
0x0100#1C4
Packet Transfer Queued
PTERR
0x0100#1C8
Packet-Transfer Error
PTEND
0x0100#1CC
Packet Transfer End
MPMSG
0x0100#1D0
MP Message
PP0MSG
0x0100#1E0
PP0 Message
PP1MSG
0x0101#1E4
PP1 Message
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PP data-unit architecture
The data unit has independent data paths for the ALU and the multiplier, each with its own set of hardware
functions. The multiplier data path includes a 16 × 16 multiplier, a halfword swapper, and rounding hardware.
The ALU data path includes a 32-bit three-input ALU, a barrel rotator, mask generator, multiple flag (mf)
expander, left/rightmost one and left/rightmost bit-change logic, and several multiplexers. Figure 37 shows the
data-unit block diagram.
src1/src2/dstc/0
dst2
src3
src4
src4/src2
0
src1/0x1
d0
Rotate Amount
Multiplexer
mf
Mask Generator
Multiplexer
Expander
LMO, RMO,
LMBC, RMBC
Barrel Rotator
Mask
Generator
C Port
Multiplexer
Multiplier
(Splittable)
Barrel
Rotator Input
Sign Bit
Scale
Round
A
B
Three-Input ALU (Splittable)
Swap/Merge
C
ALU
Function
Code Logic
N, C, V, Z, LV mf
src1
scr2
scr3
scr4
dst/dst1
Any register, D reg only for left/right most one (LMO/RMO), left/right most bit change (LMBC/RMBC) hardware
D reg or sometimes 5/32-bit immediate
dst2 D reg only
D reg only
dstc D reg only (destination companion reg source)
D reg only
0x1 Constant
Any register
0
Constant
d0
5 LSBs of d0
Figure 37. Data-Unit Block Diagram
44
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dst/dst1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP data-unit architecture (continued)
The PP’s ALU can be split into one 32-bit ALU, two 16-bit ALUs, or four 8-bit ALUs. Figure 38 shows the multiple
arithmetic data flow for the case of a four 8-bit split of the ALU (called multiple-byte arithmetic). The ALU
operates as independent parallel ALUs where each ALU receives the same function code.
32
Rotate
Clear
mf Register
4
Expander (Replicate)
8
A
B
C
C-Out
C-IN
8
8
A
B
C
C-Out
C-IN
C-IN
Logic
8
A
B
C
C-Out
C-IN
C-IN
Logic
8
C, Z,
S, or
E
8
A
B
C
C-Out
C-IN
C-IN
Logic
8
C, Z,
S, or
E
sr(C)
C-IN
Logic
8
C, Z,
S, or
E
C, Z,
S, or
E
Figure 38. Multiple-Byte Arithmetic Data Flow
PP multiplier
The PP’s hardware multiplier can perform one 16x16 multiply with a 32-bit result or two 8x8 multiplies with two
16-bit results in a single cycle. A 16x16 multiply can use signed or unsigned operands as shown in Figure 39.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
S
S
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Signed Input
14
13
12
11
10
11
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
Signed × Signed Result
15
14
13
12
Unsigned Input
15
14
13
12
11
10
9
8
7
6
Unsigned × Unsigned Result
Figure 39. 16 x 16 Multiplier Data Formats
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PP multiplier (continued)
When performing two simultaneous 8x8 split multiplies, the first input word contains unsigned byte operands
and the second input word contains signed or unsigned byte operands. These formats are shown in Figure 40
and Figure 41.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1b × 2b Signed Result
S
15
14
13
12
11
10
9
8
7
6
Unsigned Input 1b
14
13
12
11
10
9
8
Signed Input 2b
14
13
12
11
10
9
5
4
3
2
1
0
Unsigned Input 1a
7
6
S
8
7
5
4
3
2
1
0
Signed Input 2a
6
5
4
3
2
1
0
4
3
2
1
0
1a × 2a Signed Result
S
Figure 40. Signed Split Multiply Data Formats
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
Unsigned Input 1b
15
14
13
12
11
10
9
8
7
6
Unsigned Input 2b
15
14
13
12
11
1b × 2b Unsigned Result
10
9
5
Unsigned Input 1a
5
4
3
2
1
0
Unsigned Input 2a
8
7
6
5
4
3
2
1
0
1a × 2a Unsigned Result
Figure 41. Unsigned Split Multiply Data Formats
PP program-flow-control unit architecture
The program-flow-control (pfc) unit performs instruction fetching and decoding, loop control, and handshaking
with the transfer controller. The pfc unit architecture is shown in Figure 43.
The PP has a three-stage fetch, address, execute (FAE) pipeline as shown in Figure 42. The pc, ipa, and ipe
registers point to the address of the instruction in each stage of the pipeline. On each cycle in which the pipeline
advances, ipa is copied into ipe, pc is copied into ipa, and the pc is incremented by one instruction (8 bytes).
pc
Instruction
One
Two
Three
T1
T2
T3
T4
Fetch
Address
Execute
Fetch
Address
Execute
Fetch
Address
T5
ipa
Execute
ipe
Figure 42. FAE-Instruction Pipeline
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PP program-flow-control unit architecture (continued)
pc
lprs
incrementer
Cache Controller
ipa
Tag Comparators
ipe
Tag Registers
Present Bits
LRU Stack
Loop Controller 0
ls0
le0
Figure 43. Program-Flow-Control Unit Block Diagram
Comparator
lctl
Instruction Decode
lr0
FAE Pipeline Control
decr.
Control Signal Generation
lc0
zero
Loop Control
Loop Controller 1
Instruction
Control
Signal
Instruction
Address
Loop Controller 2
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PP address-unit architecture
The PP has both a local- and global-address unit which operate independently of each other. The address units
support twelve different addressing modes. In place of performing a memory access, either or both of the
address units can perform an address computation that is written directly to a PP register instead of being used
for a memory access. This address unit arithmetic provides additional arithmetic operation to supplement the
data unit during compute-intensive algorithms.
From Global
Destination Bus
Offset
To Global
Source Bus
From Global
Destination Bus
Offset
To Global
Source Bus
sp = a6 (local)
sp = a14 (global)
a0–a4
(a7 = 0)
a8–a12
(a15 = 0)
x0–x2
pba dba
PP-Relative
Multiplexer
pba, dba
Index Multiplexer
Index Scaler
Scale
Data Size
32-Bit Adder/Subtracter Unit
Preindex/Postindex
Multiplexer
x8–x10
Preindex/Postindex
PP-Relative
Multiplexer
Preindex/Postindex
Multiplexer
Figure 44. Address-Unit Architecture
48
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Index Scaler
Scale
Data Size
32-Bit Adder/Subtracter Unit
Global-Address Port
Local-Address Port
Index Multiplexer
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Preindex/Postindex
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP instruction set
PP instructions are represented by algebraic expressions for the operations performed in parallel by the
multiplier, ALU, global-address unit, and local-address unit. The expressions use the || symbol to indicate
operations that are to be performed in parallel. The PP ALU operator syntax is shown in Table 9. The data unit
operations (multiplier and ALU) are summarized in Table 10 and the parallel transfers (global and local) are
summarized in Table 11.
Table 9. PP Operators by Precedence
OPERATOR
FUNCTION
src1 [n] src1–1
Select odd (n=true) or even (n=false) register of D register pair
based on negative condition code
()
Subexpression delimiters
@mf
Expander operator
%
Mask generator
%%
Nonmultiple mask generator (EALU only)
%!
Modified mask generator (0xFFFFFFFF output for 0 input)
%%!
Nonmultiple shift right mask generator (EALU only)
\\
Rotate left
<<
Shift left (pseudo-op for rotate and mask)
>>u
Unsigned shift right
>> or >>s
Signed shift right
&
Bitwise AND
^
Bitwise XOR
|
Bitwise OR
+
Addition
–
Subtraction
=[cond]
Conditional assignment
=[cond.pro]
Conditional assignment with status protection
=
Equate
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PP instruction set (continued)
Table 10. Summary of Data-Unit Operations
Operation
Base set ALUs
Description
Perform an ALU operation specifying ALU function, 2 src and 1 dest operand, and operand routing. ALU function is one of
256 three-input Boolean operations or one of 16 arithmetic operations combined with one of 16 function modifiers.
Syntax
dst = [fmod] [ [[cond [.pro] ]] ] ALU_EXPRESSION
Examples
d6 = (d6 ^ d4) & d2
d3 = [nn.nv] d1 –1
Operation
EALU || ROTATE
Description
Perform an extended ALU (EALU) operation (specified in d0) with one of two data routings to the ALU and optionally write
the barrel rotator output to a second dest register. ALU function is one of 256 Boolean or 256 arithmetic.
Syntax
dst1 = [ [[cond [.pro] ]] ] ealu (src2, [dst2 = ] [ [[cond]] src1 [[[n]] src1–1] \\ src3, [%] src4)
dst1 = [fmod] [ [[cond [.pro] ]] ] ealu (label:EALU_EXPRESSION [ || dst2 = [[cond]] src1 [ [[n]] src1–1] \\ src3])
Examples
d7 = [nn] ealu(d2, d6 = [nn] d3\\d1, %d4)
d3 = mzc ealu(mylabel: d4 + (d5\\d6 & %d7) || d1 = d5\\d6)
Operation
MPY || ADD
Description
Perform a 16x16 multiply with optional parallel add or subtract. Condition code applies to both multiply and add.
Syntax
dst2 = [sign] [ [[cond]] ] src3 * src4 [ || dst = [ [[cond[.pro] ]] ] src2 + src1 [ [[n]] src1 –1] ]
dst2 = [sign] [ [[cond]] ] src3 * src4 [ || dst = [ [[cond[.pro] ]] ] src2 – src1 [ [[n]] src1 –1] ]
Example
d7 = u d6 * d5 || d5 = d4 – d1
Operation
MPY || SADD
Description
Perform a 16x16 multiply with a parallel right-shift and add or subtract. Condition code applies to multiply, shift, and add.
Syntax
dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[ cond [.pro] ]] ] src2 + src1 [ [[n]] src1 –1] >> –d0
dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[ cond [.pro] ]] ] src2 – src1 [ [[n]] src1 –1] >> –d0
Examples
d7 = u d6 * d5 || d5 = d4 – d1 >> –d0
Operation
MPY || EALU
Description
Perform a multiply and an optional parallel EALU. Multiply can use rounding, scaling, or splitting features.
Syntax
Generic Form:
dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[cond [.pro] ]] ] ealu[f] (src2, src1 [ [[n]] src1 –1] \\ d0, %d0)
dst2 = [sign] [ [[cond]] ] src3 * src4 || ealu()
Explicit Form:
dst2 = [sign] [opt] [ [[cond]] ] src3 * src4 [<<dms] || dst1 = [fmod] [ [[cond [.pro] ]] ] ealu (label: EALU_EXPRESSION)
dst2 = [sign] [opt] [ [[cond]] ] src3 * src4 [<<dms] || ealu (label)
Examples
d7 = [p] d5 * d3 || d2 = [p] ealu(d1, d6\\d0, %d0)
d2 = m d4 * d7 || d3 = ealu (mylabel: d3 + d2 >> 9)
Operation
divi
Description
Perform one iteration of unsigned divide algorithm. Generates one quotient bit per execution using iterative subtraction.
Syntax
dst1 = [ [[cond [.pro] ]] ] divi (src2, dst2 = [[cond]] src1 [ [[n]] src1 –1])
Examples
d3 = divi (d1, d2 = d2)
d3 = divi (d1, d2 = d3[n]d2)
Misc. Operations
dint; eint; nop
Description
Globally disable interrupts; globally enable interrupts; do nothing in the data unit
Syntax
dint
eint
nop
Legend:
[]
[[ ]]
pro
f
50
Optional parameter extension
Square brackets ([ ]) must be used
Protect status bits
Use 1s complement of d0
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cond
fmod
dms
sign
; generic form
; explicit form
Condition code
Function modifier
Default multiply shift amount
u = unsigned, s = signed
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP instruction set (continued)
Table 11. Summary of Parallel Transfers
Operation
Load
Description
Transfer from memory into PP register
Syntax
dst = [sign] [size] [ [[cond]] ]* addrexp
dst = [sign] [size] [ [[cond]] ]* an.element
Examples
d3 = uh[n]* (a9++=[2])
d1 = * a2.sMY_ELEMENT
Operation
Store
Description
Transfer from PP register into memory
Syntax
* addrexp = [size] src [ [[n]] src–1]
* an.element = [size] src [ [[n]] src–1]
Examples
*––a2 = d3
*a9.sMY_ELEMENT = a3
Operation
Address unit arithmetic
Description
Compute address and store in PP register
Syntax
dst = [size] [ [[cond]] ] & * addrexp
dst = [size] [ [[cond]] ] & * an.element
Examples
d2 = &*(a3 + x0)
a1 = &*a9.sMY_ELEMENT
Operation
Move
Description
Transfer from PP register to PP register
Syntax
dst = [g] [ [[cond]] ] src
Examples
x2 = mf
d1 = g d3
Operation
Field extract move
Description
Transfer from PP register to PP register extracting and right-aligning one byte or halfword
Syntax
dst = [sign] [size item]
Example
d3 = ub2 d1
Operation
Field replicate move
Description
Transfer from PP register to PP register replicating the least significant byte or least significant halfword to 32 bits
Syntax
dst = r [size] [[cond]] src
Example
d7 = rh d3
Legend:
[]
[[ ]]
g
item
Optional parameter extension
Square brackets ([ ]) must be used
Use global unit
0 = byte0/halfword0, 1 = byte1/halfword1, 2 = byte2, 3 = byte3
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cond
sign
size
Condition code
u = unsigned, s = signed
b = byte, h = halfword, w = word (default)
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP opcode formats
A PP instruction uses a 64-bit opcode. The opcode is divided essentially into a data unit portion and a parallel
transfer portion. There are five data unit opcode formats comprising bits 38–63 of the opcode. Bits 0–38 of the
opcode specify one of 10 parallel transfer formats. An alphabetical list of the mnemonics used in Figure 45 for
the data unit and parallel transfer portions of the opcode are shown in Table 12 and Table 13, respectively.
Data Unit Formats
6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9
0 1 1
dst1
src1
1 class
oper
A
ALU Operation
src3
dst2
dst
src1
0
src4
1 class
A
ALU Operation
dst
src1
1 0 –
1 class
A
ALU Operation
dst
src1
1 1 dstbank
1 0 0 0 1 – 0 – 0 – 0 – 0 – – – – – – 0
0 0
3 2 1 0
src2
Parallel Transfers
A. Six-Operand (MPYIIADD, etc.)
imm. src2
Parallel Transfers
B. Base Set ALU (5-Bit Immediate)
Parallel Transfers
C. Base Set ALU (Register src2)
src2
s1bnk
Operation
cond
32-Bit Immediate
Parallel Transfers
D. Base Set ALU (32-Bit Immediate)
E. Miscellaneous
Reserved
0 1 0
Reserved
Transfer Formats
3 3 3 3 3 3 3 3 3
8 7 6 5 4 3 2 1 0
2 2 2 2 2 2 2
9 8 7 6 5 4 3
2 2
2 1
2 1 1 1 1 1 1 1 1 1 1
9 8
0 9 8 7 6 5 4 3 2 1 0
Lmode
d
e size
s
La
Gim/X
Lmode
d
e size
s
La
0 Lrm
Lmode
d
e size
s
La
0 Lrm
Lmode
reg
e size
s
La
1 Lrm
bank
L 0 0
bank
L Gmode
0 0
Lmode
L
Global Long Offset /X
d
e size
s
La
0 Lrm
0 0 –
cond
c r
g N C V Z 0 –
0 0 –
cond
c r
0 0 –
cond
c r
0 0 –
cond
c r
– N C V Z 0 –
–
0bank
L Gmode
reg
dstbank
L 0 0 0 0
src
dstbank
L 0 0 0 1
src
Adstbank
7 6 5 4 3 2 1
e size
srcbank
e size
D
Ga
Lim/X
1. Double Parallel
dst
Lim/X
2. Move II Local
dst
Lim/X
3. Field Move II Local
Local Long Offset / X
reg
e size
s
L 0 0 1 – – – – As1bank
dstbank
– 0 0 0 0
g N C V Z 0 itm
dstbank
– 0 0 0 1
src
e size
g N C V Z Gim/X
bank
L Gmode
reg
e size
– Adstbank
s
src
srcbank
– 0 0 1 – – – – As1bank
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4. Local (Long Offset)
Ga
0 Grm
– – –
Lim/X
5. Global (Long Offset)
6. Non-D DU II Local
dst
– –
– 7. Conditional DU II Conditional Mode
D
dst
– –
– 8. Conditional DU II Conditional Field Move
s
Ga
1 Grm
– – – – –
Figure 45. PP Opcode Formats
52
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• HOUSTON, TEXAS 77251–1443
9. Conditional DU II Conditional Global
– 10. Conditional Non-D DU
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP opcode formats (continued)
Table 12. Data Unit Mnemonics
MNEMONIC
FUNCTION
A
A = 1 selects arithmetic operations, A = 0 selects Boolean operations
ALU Operation
For Boolean operation (A = 0), select the eight ALU function signals. For arithmetic operation (A = 1), odd bits specify the
ALU function and even bits define the ALU function modifiers.
class
Operation class: determines routing of ALU operands
cond
condition code
dst
D register destination or lower 3 bits of non-D register code
dst1
ALU dest. for MPY||ADD, MPY||EALU, or EALU||ROTATE operation. D register or lower 3 bits of non-D register code
dst2
Multiply dest. for MPY||ADD or MPY||EALU operation, or rotate dest. for EALU||ROTATE operation. D register
dstbank
ALU register bank
imm.src2
5-bit immediate for src2 of ALU operation
32-Bit Immediate
32-bit immediate for src2 of ALU operation
oper
Six-operand data unit operation (MPY||ADD, MPY||SADD, MPY||EALU, EALU||ROTATE, divi)
Operation
Miscellaneous operation
src1
ALU source 1 register code (D register unless srcbank or s1bnk is used)
src2
D register used as ALU source 2
src3
D register for multiplier source (MPY||ADD or MPY||EALU) or rotate amount (EALU||ROTATE)
src4
D reg. for ALU C port operand or EALU||ROTATE mask generator input or multiplier source 2 for MPY||ADD, MPY||EALU
s1bnk
Bits 5-3 of src1 register code (bit 6 assumed to be 0)
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PP opcode formats (continued)
Table 13. Parallel Transfer Mnemonics
MNEMONIC
FUNCTION
0bank
Bits 5–3 of global transfer source/destination register code (bit 6 assumed to be 0)
Adstbank
Bits 6–3 of ALU destination register code
As1bank
Bits 6–3 of ALU source 1 register code
bank
Bits 6–3 of global (or local) store source or load destination
c
Conditional choice of D register for src1 operand of the ALU
C
Protect status register’s carry bit
cond
Condition code
d
D register or lower 3 bits of register code for local transfer source/destination
D
Duplicate least significant data during moves
dst
The three lowest bits of the register code for move or field-move destination
dstbank
Bits 6–3 of move destination register code
e
Sign-extend local (bit 31), sign-extend global (bit 9)
g
Conditional global transfer
Ga
Global address register for load, store, or address unit arithmetic
Gim / X
Global address unit immediate offset or index register
Gmode
Global unit addressing mode
Grm
Global PP-relative addressing mode
itm
Number of items selected for field-extract move
L
L = 1 selects load operation, L = 0 selects store/address unit arithmetic operation
La
Local address register for load, store, or address unit arithmetic
Lim / X
Local address unit immediate offset or index register
Lmode
Local unit addressing mode
Lrm
Local PP-relative addressing mode
N
Protect status register’s negative bit
r
Conditional write of ALU result
reg
Register number used with bank or 0bank for global load, store, or address unit arithmetic
s
Enable index scaling. Additional index bit for byte accesses or arithmetic operations (bit 28, local; bit 6, global)
size
Size of data transfer (bits 30–29, local; bits 8–7, global)
src
Three lowest bits of register code for register-register move source or non-field moves. D register source for field move
srcbank
Bits 6–3 of register code for register-register move source
V
Protect status register’s overflow bit
Z
Protect status register’s zero bit
–
Unused bit (fill with 0)
54
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PP opcode formats (continued)
Table 14 summarizes the supported parallel-transfer formats and indicates whether the transfers are local or
global. It also lists the allowed ALU operations and states whether conditions and status protection are
supported.
Table 14. Parallel-Transfer Format Summary
FORMAT
ALU
OPERANDS
GLOBAL TRANSFER
Cond
Move
LOCAL TRANSFER
Load/Store/AUA
Load/Store/AUA
src → dst
s/d
Index
Rel
s/d
Index
No
—
Lower
X/short
No
D
No
Any³Any
—
—
—
D
No
No
D³Any
—
—
—
No
No
—
Any
X/long
Yes
No
No
—
—
—
—
No
—
—
—
Yes
Any³Any
—
—
Yes
D³Any
—
dst1
src1
Double parallel
D
D
No
Move || Local
D
D
No
Field move || Local
D
D
Global (long offset)
D
D
Local (long offset)
D
D
Non-D DU || Local
Any
Any
No
Conditional move
D
D
Yes
Conditional field move
D
D
Yes
Conditional global
Status
St
t
Protection
Rel
Port
X/short
No
Local
X/short
Yes
Local
D
X/short
No
Local
—
—
—
—
Any
X/long
Yes
Global
—
D
X/short
Yes
Global
—
—
—
—
—
—
—
—
—
—
—
D
D
Yes
Yes
—
Any
X/short
Yes
—
—
—
—
Conditional non-D DU
Any
Any
Yes
Yes
—
—
—
—
—
—
—
—
32-bit imm. base ALU
Any
Lower
Yes
No
Legend:
DU
AUA
s/d
Rel
—
Data unit
Address unit arithmetic
Source/destination register
Relative addressing support
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PP opcode formats (continued)
Table 15 shows the encoding used in the opcodes to specify particular PP registers. A 3-bit register field
contains the three least significant bits (LSBs). The register codes are used for the src, src1, src2, src3, src4,
dst, dst1, dst2, d, reg, Ga, La, Gim/X, and Lim/X opcode fields. The four most significant bits (MSBs) specify
the register bank which is concatenated to the register field for the full 7-bit code. The register bank codes are
used for the dstbank, s1bnk, srcbank, 0bank, bank, Adstbank, and As1bank opcode fields. When no associated
bank is specified for a register field in the opcode, the D register bank is assumed. When the MSB of the bank
code is not specified in the opcode (as in 0bank and s1bnk), it is assumed to be 0, indicating a lower register.
Table 15. PP Register Codes
LOWER REGISTERS (MSB OF BANK = 0)
CODING
BANK
REG
0000
000
0000
0000
UPPER REGISTERS (MSB OF BANK = 1)
CODING
REGISTER
BANK
REG
a0
0100
000
001
a1
0100
010
a2
0100
0000
011
a3
0000
100
a4
0000
101
0000
0000
CODING
REGISTER
BANK
REG
d0
1000
000
001
d1
1000
010
d2
1000
0100
011
d3
0100
100
d4
reserved
0100
101
110
a6 (sp)
0100
111
a7 (zero)
0100
0001
000
a8
0001
001
a9
0001
010
REGISTER
BANK
REG
reserved
1100
000
lc0
001
reserved
1100
001
lc1
010
reserved
1100
010
lc2
1000
011
reserved
1100
011
reserved
1000
100
reserved
1100
100
lr0
d5
1000
101
reserved
1100
101
lr1
110
d6
1000
110
reserved
1100
110
lr2
111
d7
1000
111
reserved
1100
111
reserved
0101
000
reserved
1001
000
reserved
1101
000
lrse0
0101
001
sr
1001
001
reserved
1101
001
lrse1
a10
0101
010
mf
1001
010
reserved
1101
010
lrse2
0001
011
a11
0101
011
reserved
1001
011
reserved
1101
011
reserved
0001
100
a12
0101
100
reserved
1001
100
reserved
1101
100
lrs0
0001
101
reserved
0101
101
reserved
1001
101
reserved
1101
101
lrs1
0001
110
a14 (sp)
0101
110
reserved
1001
110
reserved
1101
110
lrs2
0001
111
a15 (zero)
0101
111
reserved
1001
111
reserved
1101
111
reserved
0010
000
x0
0110
000
reserved
1010
000
reserved
1110
000
ls0
0010
001
x1
0110
001
reserved
1010
001
reserved
1110
001
ls1
0010
010
x2
0110
010
reserved
1010
010
reserved
1110
010
ls2
0010
011
reserved
0110
011
reserved
1010
011
reserved
1110
011
reserved
0010
100
reserved
0110
100
reserved
1010
100
reserved
1110
100
le0
0010
101
reserved
0110
101
reserved
1010
101
reserved
1110
101
le1
0010
110
reserved
0110
110
reserved
1010
110
reserved
1110
110
le2
0010
111
reserved
0110
111
reserved
1010
111
reserved
1110
111
reserved
0011
000
x8
0111
000
pc/call
1011
000
reserved
1111
000
reserved
0011
001
x9
0111
001
1011
001
reserved
1111
001
reserved
0011
010
x10
0111
010
ipa/br
ipe †
1011
010
reserved
1111
010
reserved
0011
011
reserved
0111
011
iprs
1011
011
reserved
1111
011
0011
100
reserved
0111
100
inten
1011
100
reserved
1111
100
reserved
tag0 †
0011
101
reserved
0111
101
intflg
1011
101
reserved
1111
101
0011
110
reserved
0111
110
comm
1011
110
reserved
1111
110
tag1 †
tag2 †
0011
111
reserved
0111
111
lctl
1011
111
reserved
1111
111
tag3 †
† Read only
56
CODING
REGISTER
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data unit operation code
For data unit opcode format A, a 4-bit operation code specifies one of 16 six-operand operations and an
associated data path. See Figure 45.
Table 16. Six-Operand Format Operation Codes
oper FIELD BIT
OPERATION TYPE
60
59
58
57
0
u
0
s
MPY || ADD
0
u
1
f
MPYU || EALU
1
0
f
k
EALU || ROTATE
1
0
1
0
divi
1
1
u
s
SPY || SADD
Legend:
u
Unsigned
f
1s complement EALU function code
s
Subtract
k
Use mask or mf expander
operation class code
The base set ALU opcodes (formats B, C, D) use an operation-class code to specify one of eight different
routings to the A, B, and C ports of the ALU. See Figure 45.
Table 17. Base Set ALU Class Summary
CLASS
DESTINATION
A PORT
000
dst
src2
src1
001
dst
dstc
src1
010
dst
dstc
src1
\\
011
dst
dstc
src1
\\
src2
100
dst
src2
src1
\\
d0
%d0
101
dst
src2
src1
\\
d0
@mf
110
dst
dstc
src1
111
dst
src1
1
Legend:
\\
@mf
%
dstc
dst
src2
srd1
B PORT
C PORT
\\
@mf
d0
src2
%src2
%src2
src2
\\
src2
src2
Rotate left
Expand function
Mask generation
Companion D register
Destination D register or any register if dstbank or Adstbank is used with destination.
Source D register or immediate
Source D register or any register if As1bank is used or any lower register if s1bnk is used
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ALU operation code
For base set ALU Boolean opcodes (A=0), the ALU function is formed by a sum of Boolean products selected
by the ALU operation opcode bits as shown in Table 18. For base set arithmetic opcodes (A=1), the four odd
ALU operation bits specify an arithmetic operation as described in Table 19 while the four even bits specify one
of the ALU function modifiers as shown in Table 20. See Table 9 for a list of PP operators and Figure 45 for PP
opcode formats.
Table 18. Base-Set ALU Boolean Function Codes
OPCODE BIT
PRODUCT TERM
58
A&B&C
57
~A & B & C
56
A & ~B & C
55
~A & ~B & C
54
A & B & ~C
53
~A & B & ~C
52
A & ~B & ~C
51
~A & ~B & ~C
Table 19. Base Set Arithmetics
OPCODE BITS
CARRY
IN
ALGEBRAIC DESCRIPTION
NATURAL
FUNCTION
MODIFIED FUNCTION
(IF DIFFERENT FROM
NATURAL FUNCTION)
57
55
53
51
0
0
0
0
x
0
0
0
1
1
A – (B | C)
A – B <1<
0
0
1
0
0
A + (B & ~C)
A + B <0<
0
0
1
1
1
A–C
A–C
0
1
0
0
1
A – (B | ~C)
A – B >1>
0
1
0
1
1
A–B
A–B
0
1
1
0
C(n)
A – (B & @mf | –B & [email protected])
A+B/A–B
if class 0 or 5
1/0
A + |B|
A+B/A–B
if class 1–4 or 6–7, A–B if sign=1
(A – (B & C)) if sign=0
0
1
1
1
1
A – (B & C)
A – B>0>
1
0
0
0
0
A + (B & C)
A + B>0>
1
0
0
1
~C(n)
A + (B & @mf | –B & [email protected])
A–B/A+B
if class 0 or 5
0/1
A – |B|
A–B/A+B
if class 1–4 or 6–7, A+B if sign=1
1
0
1
0
0
A+B
A+B
1
0
1
1
0
A + (B | ~C)
A + B >1>
1
1
0
0
0
A+C
A+C
1
1
0
1
1
A – (B & ~C)
A – B <0<
1
1
1
0
0
A + (B | C)
A + B <1<
1
1
1
1
0
(A & C) + (B & C)
field A + B
Legend:
C(n)
>0>
<0<
>1>
<1<
58
LSB of each part of C port register
Zero-extend shift right
Zero-extend shift left
One-extend shift right
One-extend shift left
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
ALU-operation code (continued)
Table 20. Function Modifier Codes
FUNCTION
MODIFIER BITS
MODIFICATION PERFORMED
58
56
54
0
0
0
0
Normal operation
0
0
0
1
cin
0
0
1
0
%! if maskgen instruction, lmo if not maskgen
0
0
1
1
%! and cin if maskgen instruction, rmo if not maskgen
0
1
0
0
A port = 0
0
1
0
1
A port = 0 and cin
0
1
1
0
A port = 0 and %! if maskgen, lmbc if not maskgen
0
1
1
1
A port = 0, %! and cin if maskgen, rmbc if not maskgen
1
0
0
0
mf bit(s) set by carry out(s). (mc)
1
0
0
1
mf bit(s) set based on status register MSS field. (me)
1
0
1
0
Rotate mf by Asize, mf bit(s) set by carry out(s). (mrc)
1
0
1
1
Rotate mf by Asize, mf bit(s) set based on status register MSS field. (mre)
1
1
0
0
Clear mf, mf bit(s) set by carry out(s). (mzc)
1
1
0
1
Clear mf, mf bit(s) set based on status register MSS field. (mze)
1
1
1
0
No setting of bits in mf register. (mx)
1
1
1
1
Reserved
Legend:
cin
lmbc
lmo
52
Carry in from sr(C)
Leftmost-bit change
Leftmost one
%!
rmbc
rmo
Modified mask generator
Rightmost-bit change
Rightmost one
miscellaneous operation code
For data-unit opcode format E, the operation field selects one of the miscellaneous operations.
Table 21. Miscellaneous Operation Codes
OPCODE BITS
MNEMONIC
OPERATION
0
nop
No data-unit operation. Status not modified
0
1
reserved
1
0
eint
Global-interrupt enable
0
1
1
dint
Global-interrupt disable
1
x
x
reserved
1
x
x
x
reserved
x
x
x
x
reserved
43
42
41
40
39
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
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addressing mode codes
The Lmode (bits 35–38) and Gmode (bits 13–16) of the opcode specify the local and global transfer for various
parallel transfer opcode formats (Lmode in formats 1, 2, 3, 4, and 6 and Gmode in formats 1, 5, and 9). See
Figure 45 for PP opcode formats. Table 22 shows the coding for the addressing mode fields.
Table 22. Addressing Mode Codes
CODING
EXPRESSION
DESCRIPTION
00xx
Nop (nonaddressing mode operation)
0100
*(an ++= xm)
Postaddition of index register, with modify
0101
*(an – –= xm)
Postsubtraction of index register, with modify
0110
*(an ++= imm)
Postaddition of immediate, with modify
0111
*(an – –= imm)
Postsubtraction of immediate, with modify
1000
*(an + xm)
Preaddition of index register
1001
*(an – xm)
Presubtraction of index register
1010
*(an + imm)
Preaddition of immediate
1011
*(an – imm)
Presubtraction of immediate
1100
*(an += xm)
Preaddition of index register, with modify
1101
*(an –= xm)
Presubtraction of index register, with modify
1110
*(an += imm)
Preaddition of immediate, with modify
1111
*(an –= imm)
Presubtraction of immediate, with modify
Legend:
an
imm
xm
Address register in local/global (l/g) address unit
Immediate offset
Index register in same unit as an register
L, e codes
The L and e bits combine to specify the type of parallel transfer performed. For the local transfer, L and e are
bits 21 and 31, respectively. For the global transfer, L and e are bits 17 and 9, respectively. See Figure 45 for
PP opcode formats.
Table 23. Parallel Transfer Type
L
e
0
0
Store
PARALLEL TRANSFER
0
1
Address unit arithmetic
1
0
Zero-extend load
1
1
Sign-extend load
size codes
The size code specifies the data transfer size. For field moves (parallel transfer format 3), only byte and halfword
data sizes are valid.
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
Table 24. Transfer Data Size
CODING
60
DATA SIZE
00
Byte (8 bits)
01
Halfword (16 bits)
10
Word (32 bits)
11
Reserved
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relative-addressing mode codes
The Lrm and Grm opcode fields allow the local-address or global-address units, respectively, to select
PP-relative addressing as shown in Table 25.
Table 25. Relative-Addressing Mode Codes
CODING
RELATIVE-ADDRESSING
MODE
00
Normal (absolute addressing)
01
Reserved
10
PP-relative dba
11
PP-relative pba
Legend:
dba – Data RAM 0 base is base address
pba – Paramater RAM base is base address
condition codes
In the four conditional parallel transfer opcodes (formats 7–10), the condition code field specifies one of
16 condition codes to be applied to the data unit operation source, data unit result, or global transfer based on
the settings of the c, r, and g bits, respectively. Table 26 shows the condition codes. For the 32-bit immediate
data unit opcode (format D), the condition applies to the data unit result only. See Figure 45 for PP opcode
formats.
Table 26. Condition Codes
CONDITION
BITS
MNEMONIC
DESCRIPTION
STATUS BIT COMBINATION
35
34
33
32
0
0
0
0
u
Unconditional (default)
None
0
0
0
1
p
Positive
~N & ~Z
0
0
1
0
ls
Lower than or same
~C | Z
0
0
1
1
hi
Higher than
C & ~Z
0
1
0
0
lt
Less than
(N & ~V) | (~N & V)
0
1
0
1
le
Less than or equal
(N & ~V) | (~N & V) | Z
0
1
1
0
ge
Greater than or equal
(N & V) | (~N & ~V)
0
1
1
1
gt
Greater than
(N & V & ~Z) | (~N & ~V & ~Z)
1
0
0
0
hs, c
Higher than or same, carry
C
1
0
0
1
lo, nc
Lower than, no carry
~C
1
0
1
0
eq, z
Equal, zero
Z
1
0
1
1
ne, nz
Not equal, not zero
~Z
1
1
0
0
v
Overflow
V
1
1
0
1
nv
No overflow
~V
1
1
1
0
n
Negative
N
1
1
1
1
nn
Nonnegative
~N
EALU operations
Extended ALU (EALU) operations allow the execution of more advanced ALU functions than those specified
in the base set ALU opcodes. The opcode for EALU instructions contains the operands for the operation while
the d0 register extends the opcode by specifying the EALU operation to be performed. The format of d0 for EALU
operations is shown in Figure 24.
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EALU Boolean functions
EALU operations support all 256 Boolean ALU functions plus the flexibility to add 1 or a carry-in to Boolean sum.
The Boolean function performed by the ALU is:
(F0 & (~A & ~B & ~C)) | (F1 & (A & ~B & ~C)) | (F2 & (~A & B & ~C)) | (F3 & (A & B &
~C)) | (F4 & (~A & ~B & C)) | (F5 & (A & ~B & C)) | (F6 & (~A & B & C)) | (F7 & (A & B
& C)) [+1 | +cin]
Table 27. EALU Boolean Function Codes
d0 BIT
ALU FUNCTION SIGNAL
PRODUCT TERM
26
F7
A&B&C
25
F6
~A & B & C
24
F5
A & ~B & C
23
F4
~A & ~B & C
22
F3
A & B & ~C
21
F2
~A & B & ~C
20
F1
A & ~B & ~C
19
F0
~A & ~B & ~C
EALU arithmetic functions
EALU operations support all 256 arithmetic functions provided by the three-input ALU plus the flexibility to add
1 or a carry-in to the result. The arithmetic function performed by the ALU is:
f(A,B,C) = A & f1(B,C) + f2(B,C) [+1 | cin]
f1(B,C) and f2(B,C) are independent Boolean combinations of the B and C ALU inputs. The ALU function is
specified by selecting the desired f1 and f2 subfunction and then XORing the f1 and f2 code from Table 28 to
create the ALU function code for bits 19–26 of d0. Additional operations such as absolute values and signed
shifts can be performed using d0 bits which control the ALU function based on the sign of one of the inputs.
Table 28. ALU f1(B,C) and f2(B,C) Subfunctions
f1
CODE
62
f2
CODE
SUBFUNCTION
COMMON USAGE
00
00
0
Zero the term
AA
FF
–1
–1 (All 1s)
88
CC
B
B
22
33
–B –1
Negate B
A0
F0
C
C
0A
0F
–C –1
Negate C
80
C0
B&C
Force bits in B to 0 where bits in C are 0
2A
3F
–(B & C) – 1
Force bits in B to 0 where bits in C are 0 and negate
A8
FC
B|C
Force bits in B to 1 where bits in C are 1
02
03
–(B | C) – 1
Force bits in B to 1 where bits in C are 1 and negate
08
0C
B & ~C
Force bits in B to 0 where bits in C are 1
A2
F3
–(B & ~C) –1
Force bits in B to 0 where bits in C are 1 and negate
8A
CF
B | ~C
Force bits in B to 1 where bits in C are 0
20
30
–(B | ~C) –1
Force bits in B to 1 where bits in C are 0 and negate
28
3C
(B & ~C) | ((–B – 1) & C)
Choose B if C = all 0s and –B if C = all 1s
82
C3
(B & C) | ((–B – 1) & ~C)
Choose B if C = all 1s and –B if C = all 0s
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TC architecture
The transfer controller (TC) is a combined memory controller and DMA (direct memory access) machine. It
handles the movement of data within the ’C80 system as requested by the master processor, parallel
processors, and external devices. The transfer controller performs the following data movement and memory
control functions:
D
D
D
D
D
D
D
D
MP and PP instruction cache fills
MP data-cache fills and dirty block write-back
MP and PP direct external accesses (DEAs)
MP and PP packet transfers
Externally initiated packet transfers (XPTs)
Shift register transfer (SRT) packet transfers for updating VRAM-based frame buffers
DRAM refresh
Host bus request
TC functional block diagram
Figure 46 shows a functional block diagram of the transfer controller. Key features of the TC include:
D Crossbar interface
–
64-bit data path
–
Single-cycle access
D External memory interface
–
4G-Byte address range
–
Programmable:
bus size: 8-, 16-, 32-, or 64-bits
page size
bank size
address multiplexing
cycle timing
block-write mode
bank priority
–
Big- or little-endian operation
D Cache, VRAM, refresh controller
–
Programmable refresh rate
–
VRAM block-write support
D Independent Src and Dst addressing
–
Autonomous addressing based on packet-transfer parameters
–
Data read and write at different rates
–
Numerous data merging and alignment functions performed during transfer
D Intelligent request prioritization
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
TC functional block diagram (continued)
Packet Transfer
FIFO
Src MUX and
Alignment
Dst MUX and
Alignment
Cache Buffer
64
Crossbar
Interface
External
Memory
Interface
64
64
Src
Controller
64
Dst
Controller
Cache, VRAM, and
Refresh Controller
Src Control
Registers
Memory
Configuration
Cache
Dst Control
Registers
Request Queuing and Prioritization
Figure 46. TC Block Diagram
TC registers
The TC contains four on-chip memory-mapped registers accessible by the MP.
refresh control (REFCNTL) register (0x01820000)
The REFCNTL register controls refresh cycles.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
RPARLD
RPARLD
8
7
6
5
4
3
2
1
0
REFRATE
Refresh Pseudo-Address Reload Value
REFRATE
Refresh Interval (in clock cycles)
Figure 47. REFCNTL Register
packet-transfer minimum (PTMIN) register (0x01820004)
The PTMIN register determines the minimum number of cycles that a packet transfer executes before being
suspended by a higher priority packet transfer.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
PTMIN
Figure 48. PTMIN Register
64
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10
9
8
7
6
5
4
3
2
1
0
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PT maximum (PTMAX) register (0x01820008)
The PTMAX register determines the maximum number of cycles after PTMIN has elapsed that a packet transfer
executes before timing out.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PTMAX
Figure 49. PTMAX Register
fault status (FLTSTS) register (0x0182000C)
The FLTSTS register indicates the cause of a memory access fault. Fault status bits are cleared by writing a
1 to the appropriate bit.
31
30
29
28
PP #
PC
PP
27
26
25
24
P
C
P
C
P
C
P
C
3
2
1
0
23
22
21
20
PP#
19
18
17
16
P
P
P
P
P
P
P
P
3
2
1
0
PPx Cache / DEA Fault
PPx Packet-Transfer Fault
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
XPT
XPT
M
0
M
Faulting XPT
MP Packet-Transfer Fault
Figure 50. FLTSTS Register
packet-transfer parameters
The most efficient method for data movement in a SMJ320C80 system is through the use of packet transfers
(PTs). Packet transfers allow the TC to move blocks of data autonomously between a specified src and dst
memory region. Requests for the TC to execute a packet transfer may be made by the MP, PPs, or external
devices. A packet-transfer parameter table describing the data packet and how it is to be transferred must be
programmed in on-chip memory before the transfer is requested. The TC on the SMJ320C80 supports shortand long-form packet transfers. The PT parameter table format is shown in Figure 51.
31
0
Next Entry Address
31
0
PT
Src B Pitch
PT + 32
PT Options
PT + 4
Dst B Pitch
PT + 36
Src Start/Base Address
PT + 8
Src C Pitch/Guide Table Pointer
PT + 40
Dst Start/Base Address
PT + 12
Dst C Pitch/Guide Table Pointer
Src B Count
Src A Count
PT + 16
Transparency/Color Word 0
PT + 44
PT + 48†
Dst B Count
Dst A Count
PT + 20
Transparency/Color Word 1
PT + 52†
Src C Count/# of Entries
PT + 24
Reserved
PT + 56
Dst C Count/# of Entries
PT + 28
Reserved
PT + 60
PT – 64-byte aligned on-chip starting address of
parameter table
† Words are swapped in big-endian mode
Figure 51. Packet-Transfer Parameter Table
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PT-options field
The PT-options field of the parameter table controls the type of src and dst transfer that the TC performs. The
format of the options field is shown in Figure 52.
31
S
30
29
PTS
S
PTS
I
RDC
RDB
RA
RSC
RSB
X
28
I
27
26
25
24
R
C
D
R
D
B
23
22
21
R
A
R
S
C
R
S
B
20
19
18
X
17
16
PAM
Stop bit
PT status
00 – Active
10 – Fault on src
01 – Suspended
11 – Fault on dst
Interrupt when complete
Reverse dst C addressing
Reverse dst B addressing
Reverse A addressing
Reverse src C addressing
Reverse src B addressing
Exchange src and dst parameters
15
14
13
12
11
STM
PAM
STM/DTM
SUM/DUM
8
7
PT Access Mode
000 – Normal
001 – PDT
010 – Block Write
011 – SRT
src/dst Transfer Mode
000 – Dimensioned
001 – Fill†
010 – Reserved
011 – LUT†
src/dst update mode
00 – None
01 – Add B Pitch
Figure 52. PT-Options Field
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9
SUM
† Valid for src only.
66
10
• HOUSTON, TEXAS 77251–1443
6
5
4
3
2
DTM
1
0
DUM
100 – 8 Bit Transfer
101 – 16 Bit Transfer
110 – 32 bit Transfer
111 – 64 Bit Transfer
100 – Var Delta-Guided
101 – Var Offset-Guided
110 – Fixed Delta-Guided
111 – Fixed Offset-Guided
01 – Add C Pitch
11 – Add C Pitch/Reverse
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
local memory interface
status codes
Status codes are output on STATUS[5:0] to describe the cycle being performed. During row time, STATUS[5:0]
pins indicate the type of cycle being performed. The cycle type can be latched using RL or RAS and used by
external logic to perform memory bank decoding or to enable special hardware features. During column time,
the STATUS[5:0] pins indicate the requesting processor or special column information.
Table 29. Row-Time Status Codes
STATUS[5:0]
CYCLE TYPE
STATUS[5:0]
CYCLE TYPE
0 0 0 0 0 0
Normal Read
1 0 0 0 0 0
Reserved
0 0 0 0 0 1
Normal Write
1 0 0 0 0 1
Reserved
0 0 0 0 1 0
Refresh
1 0 0 0 1 0
Reserved
0 0 0 0 1 1
SDRAM DCAB
1 0 0 0 1 1
Reserved
0 0 0 1 0 0
Peripheral Device PT Read
1 0 0 1 0 0
XPT1 Read
0 0 0 1 0 1
Peripheral Device PT Write
1 0 0 1 0 1
XPT1 Write
0 0 0 1 1 0
Reserved
1 0 0 1 1 0
XPT1 PDPT Read
0 0 0 1 1 1
Reserved
1 0 0 1 1 1
XPT1 PDPT Write
0 0 1 0 0 0
Reserved
1 0 1 0 0 0
XPT2 Read
0 0 1 0 0 1
Block-Write PT
1 0 1 0 0 1
XPT2 Write
0 0 1 0 1 0
Reserved
1 0 1 0 1 0
XPT2 PDPT Read
0 0 1 0 1 1
Reserved
1 0 1 0 1 1
XPT2 PDPT Write
0 0 1 1 0 0
SDRAM MRS
1 0 1 1 0 0
XPT3 Read
0 0 1 1 0 1
Load Color Register
1 0 1 1 0 1
XPT3 Write
0 0 1 1 1 0
Reserved
1 0 1 1 1 0
XPT3 PDPT Read
0 0 1 1 1 1
Reserved
1 0 1 1 1 1
XPT3 PDPT Write
0 1 0 0 0 0
Frame 0 Read Transfer
1 1 0 0 0 0
XPT4/SAM1 Read
0 1 0 0 0 1
Frame 0 Write Transfer
1 1 0 0 0 1
XPT4/SAM1 Write
0 1 0 0 1 0
Frame 0 Split-Read Transfer
1 1 0 0 1 0
XPT4/SAM1 PDPT Read
0 1 0 0 1 1
Frame 0 Split-Write Transfer
1 1 0 0 1 1
XPT4/SAM1 PDPT Write
0 1 0 1 0 0
Frame 1 Read Transfer
1 1 0 1 0 0
XPT5/SOF1 Read
0 1 0 1 0 1
Frame 1 Write Transfer
1 1 0 1 0 1
XPT5/SOF1 Write
0 1 0 1 1 0
Frame 1 Split-Read Transfer
1 1 0 1 1 0
XPT5/SOF1 PDPT Read
0 1 0 1 1 1
Frame 1 Split-Write Transfer
1 1 0 1 1 1
XPT5/SOF1 PDPT Write
0 1 1 0 0 0
Reserved
1 1 1 0 0 0
XPT6/SAM0 Read
0 1 1 0 0 1
Reserved
1 1 1 0 0 1
XPT6/SAM0 Write
0 1 1 0 1 0
Reserved
1 1 1 0 1 0
XPT6/SAM0 PDPT Read
0 1 1 0 1 1
Reserved
1 1 1 0 1 1
XPT6/SAM0 PDPT Write
0 1 1 1 0 0
PT Read Transfer
1 1 1 1 0 0
XPT7/SOF0 Read
0 1 1 1 0 1
PT Write Transfer
1 1 1 1 0 1
XPT7/SOF0 Write
0 1 1 1 1 0
Reserved
1 1 1 1 1 0
XPT7/SOF0 PDPT Read
0 1 1 1 1 1
Idle
1 1 1 1 1 1
XPT7/SOF0 PDPT Write
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local memory interface (continued)
Table 30. Column-Time Status Codes
STATUS[5:0]
CYCLE TYPE
STATUS[5:0]
CYCLE TYPE
0 0 0 0 0 0
PP0 Low-Priority Packet Transfer
1 0 0 0 0 0
Reserved
0 0 0 0 0 1
PP0 High-Priority Packet Transfer
1 0 0 0 0 1
Reserved
0 0 0 0 1 0
PP0 Instruction Cache
1 0 0 0 1 0
Reserved
0 0 0 0 1 1
PP0 DEA
1 0 0 0 1 1
Reserved
0 0 0 1 0 0
PP1 Low-Priority Packet Transfer
1 0 0 1 0 0
Reserved
0 0 0 1 0 1
PP1 High-Priority Packet Transfer
1 0 0 1 0 1
Reserved
0 0 0 1 1 0
PP1 Instruction Cache
1 0 0 1 1 0
Reserved
0 0 0 1 1 1
PP1 DEA
1 0 0 1 1 1
Reserved
0 0 1 0 0 0
PP2 Low-Priority Packet Transfer
1 0 1 0 0 0
Reserved
0 0 1 0 0 1
PP2 High-Priority Packet Transfer
1 0 1 0 0 1
Reserved
0 0 1 0 1 0
PP2 Instruction Cache
1 0 1 0 1 0
Reserved
0 0 1 0 1 1
PP2 DEA
1 0 1 0 1 1
Reserved
0 0 1 1 0 0
PP3 Low-Priority Packet Transfer
1 0 1 1 0 0
Reserved
0 0 1 1 0 1
PP3 High-Priority Packet Transfer
1 0 1 1 0 1
Reserved
0 0 1 1 1 0
PP3 Instruction Cache
1 0 1 1 1 0
Reserved
0 0 1 1 1 1
PP3 DEA
1 0 1 1 1 1
Reserved
0 1 0 0 0 0
MP Low-Priority Packet Transfer
1 1 0 0 0 0
Reserved
0 1 0 0 0 1
MP High-Priority Packet Transfer
1 1 0 0 0 1
Reserved
0 1 0 0 1 0
MP Urgent Packet Transfer (Low)
1 1 0 0 1 0
Reserved
0 1 0 0 1 1
MP Urgent Packet Transfer (High)
1 1 0 0 1 1
Reserved
0 1 0 1 0 0
XPT/VCPT in Progress
1 1 0 1 0 0
Reserved
0 1 0 1 0 1
XPT/VCPT Complete
1 1 0 1 0 1
Reserved
0 1 0 1 1 0
MP Instruction Cache (Low)
1 1 0 1 1 0
Reserved
0 1 0 1 1 1
MP Instruction Cache (High)
1 1 0 1 1 1
Reserved
0 1 1 0 0 0
MP DEA (Low)
1 1 1 0 0 0
Reserved
0 1 1 0 0 1
MP DEA (High)
1 1 1 0 0 1
Reserved
0 1 1 0 1 0
MP Data Cache (Low)
1 1 1 0 1 0
Reserved
0 1 1 0 1 1
MP Data Cache (High)
1 1 1 0 1 1
Reserved
0 1 1 1 0 0
Frame 0
1 1 1 1 0 0
Reserved
0 1 1 1 0 1
Frame 1
1 1 1 1 0 1
Reserved
0 1 1 1 1 0
Refresh
1 1 1 1 1 0
Reserved
0 1 1 1 1 1
Idle
1 1 1 1 1 1
Write Drain / SDRAM DCAB
Low – MP operating in low-(normal) priority mode
High – MP operating in high-priority mode
68
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address multiplexing
To support various RAM devices, the SMJ320C80 can provide multiplexed row and column addresses on its
address bus. A full 32-bit address is always output at row time. The alignment of column addresses is configured
by the value input on the AS[2:0] pins at row time.
A Pins
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Row Time
A Pins
AS [2:0]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
001
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
x
2
1
0
010
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
x
x
2
1
0
100
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
2
1
0
011
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
2
1
0
100
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
x
2
1
0
110
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
x
x
2
1
0
111
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
x
x
x
2
1
0
Column Time
Figure 53. Address Multiplexing
dynamic bus sizing
The ’C80 supports data bus sizes of 8, 16, 32, or 64 bits. The value input on the BS[1:0] pins at row time
indicates the bus size of the addressed memory. This determines the maximum number of bytes which the ’C80
can transfer during each column access. If the number of bytes to be transferred exceeds the bus size, multiple
accesses are performed automatically to complete the transfer.
Table 31. Bus Size Selection
BS[1:0]
BUS SIZE
00
8 bits
01
16 bits
10
32 bits
11
64 bits
The selected bus size also determines which portion of the data bus is used for the transfer. For 64-bit memory,
the entire data bus is used. For 32-bit memory, D[31:0] are used in little-endian mode and D[63:32] are used
in big-endian mode. 16-bit buses use D[15:0] and D[63:48] and 8-bit buses use D[7:0] and D[63:56] for littleand big-endian modes, respectively. The ’C80 always aligns data to the proper portion of the bus and activates
the appropriate CAS strobes to ensure that only valid bytes are transferred.
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
cycle time selection
The ’C80 supports eight basic sets of memory timings to support various memory types directly. The cycle timing
is selected by the value input on the CT[2:0] pins at row time. The selected timing remains in effect until the next
row access.
Table 32. Cycle-Timing Selection
CT[2:0]
MEMORY TIMING
000
Pipelined (Burst Length 1) SDRAM, CAS Latency of 2
001
Pipelined (Burst Length 1) SDRAM, CAS Latency of 3
010
Interleaved (Burst Length 2) SDRAM, CAS Latency of 2
011
Interleaved (Burst Length 2) SDRAM, CAS Latency of 3
100
Pipelined 1 Cycle/Column
101
Nonpipelined 1 Cycle/Column
110
2 Cycle/Column
111
3 Cycle/Column
page sizing
Whenever an external memory access occurs, the TC records the 22 most significant bits of the address in its
internal LASTPAGE register. The address of each subsequent (column) access is compared to this value. The
page size value input on the PS[3:0] pins determines which bits of LASTPAGE are used for this comparison.
If a difference exists between the enabled LASTPAGE bits and the corresponding bits of the next access, then
the page has changed and the next memory access begins with a new row-address cycle.
Table 33. Page-Size Selection
PS[3:0]
ADDRESS BITS COMPARED
PAGE SIZE (BYTES)
0 0 0 0
A[31:6]
64
0 0 0 1
A[31:7]
128
0 0 1 0
A[31:8]
256
0 0 1 1
A[31:9]
512
0 1 0 0
A[31:10]
1K
0 1 0 1
A[31:18]
256K
0 1 1 0
A[31:19]
512K
0 1 1 1
A[31:20]
1 0 0 0
A[31:0]
1M
1–8†
1 0 0 1
A[31:11]
2K
1 0 1 0
A[31:12]
4K
1 0 1 1
A[31:13]
8K
1 1 0 0
A[31:14]
16K
1 1 0 1
A[31:15]
32K
1 1 1 0
A[31:16]
64K
1 1 1 1
A[31:17]
128K
† PS[3:0] = 1000 disables page-mode cycles so that the effective page size is the same
as the bus size
70
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block-write support
The SMJ320C80 supports three modes of VRAM block-write. The block-write mode is dynamically selectable
so that software can specify block-writes regardless of the type of block-write the addressed memory supports.
Block-writes are supported only for 64-bit buses. During block-write and load-color-register cycles, the BS[1:0]
inputs determine which block mode will be used.
Table 34. Block-Write Selection
BS[1:0]
BLOCK-WRITE MODE
0 0
Simulated
0 1
Reserved
1 0
4x
1 1
8x
SDRAM support
The SMJ320C80 provides direct support for synchronous DRAM (SDRAM), synchronous VRAM (SVRAM), and
synchronous graphics RAM (SGRAM). During ’C80 power-up refresh cycles, the external system must signal
the presence of these memories by inputting a CT2 value of 0. This causes the ’C80 to perform special
deactivate (DCAB) and mode register set (MRS) commands to initialize the synchronous RAMs. Figure 54
shows the MRS value generated by the ’C80.
SDRAM Mode
Register Bit
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
CT0
0
0
0
CT1
CT0, CT1 as input at the start of the MRS cycle
Figure 54. MRS Value
Because the MRS register is programmed through the SDRAM address inputs, the alignment of the MRS data
to the ’C80 logical-address bits is adjusted for the bus size (see Figure 55). The appearance of the MRS bits
on the ’C80 physical-address bus is dependent on the address multiplexing as selected by the AS[2:0] inputs.
’C80 LOGICAL ADDRESS BITS
BS[1:0]
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
0 0
X
X
X
X
11
10
9
8
7
6
5
4
3
2
1
A0
0
0 1
X
X
X
11
10
9
8
7
6
5
4
3
2
1
0
X
1 0
X
X
11
10
9
8
7
6
5
4
3
2
1
0
X
X
1 1
X
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
Figure 55. MRS Value Alignment
memory cycles
SMJ320C80 external memory cycles are generated by the TC’s external memory controller. The controller’s
state machine generates a sequence of states which define the transition of the memory interface signals. The
state sequence is dependent on the cycle timing selected for the memory access being performed as shown
in Figure 56. Memory cycles consist of row states and the column pipeline.
POST OFFICE BOX 1443
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71
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
memory cycles (continued)
rhiz
bus release
idle or abort
bus request
r1
always
r9
always
any cycle
fault, retry, or abort
always
r2
any cycle
r8
wait
r3
always
r5
MRS or DCAB
!MRS & !DCAB
spin
spin
r6
col access
rspin
wait
col access
Column Pipeline
Figure 56. Memory Cycle State Diagram
72
new page & (CT = 0xx or CT = 100 & write)
r4
CT = 0xx & !SRS
CT = 110
CT = 111
CT = 10x or 0xx & SRS
refresh & CT = 10x or CT = 0xx
refresh & CT = 110
r7
refresh & CT = 111
drn
POST OFFICE BOX 1443
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new page
always
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
row states
The row states make up the row time of each memory access. They occur when each new page access begins.
The transition indicators determine the conditions that cause transitions to another state.
Table 35. Row States
STATE
DESCRIPTION
r1
Beginning state for all memory accesses. Outputs row address (A[31:0]) and cycle type (STATUS[5:0]) and drives control
signals to their inactive state
r2
Common to all memory accesses. Asserts RL and drives DDIN according to the data transfer direction. AS[2:0], BS[1:0],
CT[2:0], PS[3:0], and UTIME inputs are sampled
r3
Common to all memory accesses. DBEN is driven to its active level. For non-SDRAM, W, TRG/CAS, and DSF are driven to their
active levels, and for non-SDRAM refreshes, all CAS/DQM strobes are activated. FAULT, READY, and RETRY inputs are
sampled.
r4
Inserted for 3 cycle/column accesses (CT=111) only. No signal transitions occur. RETRY input is sampled.
r5
Common to SDRAM and 2 or 3 cycle/column accesses (CT=0xx or 11x). RAS is driven low. W is driven low for DCAB and MRS
cycles and TRG/CAS is driven low for MRS and SDRAM refresh cycles.
r6
Common to all memory accesses. For SDRAM cycles, RAS, TRG/CAS, and W are driven high. For non-SDRAM, RAS is driven
low (if not already) and W, TRG/CAS, and DSF are driven to their appropriate levels. DBEN is driven low and READY and
RETRY are sampled.
rspin
Additional state to allow TC column time pipeline to load. No signal transitions occur. RETRY is sampled. The rspin state can, on
occasion, repeat multiple times.
r7
Common to 2 and 3 cycle/column refreshes (CT=11x). Processor activity code is output on STATUS[5:0]. RETRY input is
sampled.
r8
For 3 cycle/column refreshes only (CT=111). No signal transitions occur. RETRY input is sampled.
r9
Common to all refresh cycles. Processor activity code is output on STATUS[5:0] and RETRY input is sampled.
drn
Occurs for SDRAM cycles (CT = 0xx) and pipelined 1 cycle/column writes only. For SDRAM cycles, RAS, and W are activated
to perform a DCAB command. For pipelined writes, all CAS/DQM strobes are activated.
rhiz
High-impedance state. Occurs during host requests and repeats until bus is released by the host
Table 36. State Transition Indicators
INDICATOR
any cycle
CT=xxx
DESCRIPTION
Continuation of current cycle
State change occurs for indicated CT[2:0] value (as latched in r2 state)
abort
Current cycle aborted by TC in favor of higher-priority cycle
fault
FAULT input sampled low (in r3 state), memory access faulted
retry
RETRY input sampled low (in r3 state), row-time retry
wait
READY input sampled low (in r3, r6, or last column state) repeat current state
spin
Internally generated wait state to allow TC pipeline to load
new page
The next access requires a page change (new row access)
external memory timing examples
The following sections contain descriptions of the ’C80 memory cycles and illustrate the signal transitions for
those cycles. Memory cycles can be separated into two basic categories: DRAM-type cycles for use with
DRAM-like devices, SRAM, and peripherals, and SDRAM-type cycles for use with SDRAM-like devices.
POST OFFICE BOX 1443
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73
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
DRAM-type cycles
The DRAM-type cycles are page-mode accesses consisting of a row access followed by one or more column
accesses. Column accesses may be one, two, or three clock cycles in length with two and three cycle accesses
allowing the insertion of wait states to accommodate slow devices. Idle cycles can occur after necessary column
accesses have completed or between column accesses due to “bubbles” in the TC data-flow pipeline. The
pipeline diagrams in Figure 57 show the pipeline stages for each access type and when the CAS/DQM signal
corresponding to the column access is activated.
* ! """#
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1
2
1
2
! """#
+$(&' ,-&' ./ +$(&
1
2
! ""#
$%&' $% ($%&)$&' &( $% ($%&)$&
POST OFFICE BOX 1443
! ""#
+$(&' ,-&' % ./ +$(&
Figure 57. DRAM Cycle Column Pipelines
74
! """#
$%&' $% ($%&)$&' &( $% ($%&)$&
* ! """#
+$(&' ,-&' ./ +$(&
! """"#
+$(&' % $ $0&($ ,-#' ./ +$(&
! """"#
$%&' $% ($%&)$&' &( $% ($%&)$&
• HOUSTON, TEXAS 77251–1443
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles
Read cycles transfer data or instructions from external memory to the ’C80. The cycles can occur as a result
of a packet transfer, cache request, or DEA request. During the cycle, W is held high, TRG/CAS is driven low
after RAS to enable memory output drivers and DBEN and DDIN are low so that data transceivers can drive
into the ’C80. During column time, the TC places D[63:0] into the high-impedance state, allowing it to be driven
by the memory and latches input data during the appropriate column state. The TC always reads 64 bits and
extracts and aligns the appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. During
peripheral device packet transfers, DBEN and DDIN remain high.
POST OFFICE BOX 1443
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75
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
State
Col A
Col B
Col C
Col D
r1
r2
r3
r6
col
c1
col
c2
c1
col
c3
c2
c1
col
col
col
c3
c2
c1
c3
c2
c3
CLKOUT
CT[2:0]
4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
PAC
PAC
Row
Col A
Col B
Col C
Col D
Idle
RL
A[31:0]
RAS
–/A
B/C
A/B
C/D
D/–
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
A
DBEN
B
C
0 For Normal Reads, 1 For PDPT Reads
DDIN
For user-modified timing:
UTIME
RAS
–/A
CAS/DQM[7:0]
A/B
B/C
C/D
D/–
Figure 58. Pipelined 1-Cycle/Column Read-Cycle Timing
76
D
POST OFFICE BOX 1443
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r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
State
r1
r2
r3
Col A
r6
col
col
c1
c2
Col B
col
c1
col
r1
c2
Col C
c1
c2
Idle
CLKOUT
CT[2:0]
5
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
PAC
Row
Col A
Col B
Col C
A
B
C
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
A
B
C
0 For Normal Reads, 1 For PDPT Reads
DBEN
DDIN
For user-modified timing:
UTIME
RAS
A
CAS/DQM[7:0]
B
C
Figure 59. Nonpipelined 1-Cycle/Column Read-Cycle Timing
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77
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
State
r1
r2
r3
r5
r6
Col A
col
col
c1
c2
Col B
col
col†
col
c1
c2
c2
ci‡
Col C
col
col
c1
c2
CLKOUT
CT[2:0]
6
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
Row
Col A
PAC
Idle
PAC
RL
A[31:0]
Col B
Col C
RAS
A
CAS/DQM[7:0]
B
C
DSF
TRG/CAS
W
A
D[63:0]
B
C
0 For Normal Reads, 1 For PDPT Reads
DBEN
DDIN
For user-modified timing:
UTIME
RAS
A
CAS/DQM[7:0]
B
† Wait state inserted by external logic (example)
‡ Internally generated pipeline bubble (example)
Figure 60. 2-Cycle/Column Read-Cycle Timing
78
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C
r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
State
r1
r2
r3
r4
Col A
r5
r6
col
col
col
c1
c2
c3
Col B
col
col
col†
col
c1
c2
c3
c3
ci‡
Col C
col
col
col
c1
c2
c3
r1
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Idle
PAC
RL
A[31:0]
Row
Column A
Column B
Column C
A
B
C
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
A
D[63:0]
DBEN
B
C
0 For Normal Reads, 1 For PDPT Reads
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
† Wait state inserted by external logic (example)
‡ Internally generated pipeline bubble (example)
A
B
C
Figure 61. 3-Cycle/Column Read-Cycle Timing
write cycles
Write cycles transfer data from the ’C80 to external memory. These cycles can occur as a result of a packet
transfer, a DEA request, or an MP data cache write-back. During the cycle TRG/CAS is held high, W is driven
low after the fall of RAS to enable early-write cycles, and DDIN is high so that data transceivers drive toward
memory. The TC drives data out on D[63:0] and indicates valid bytes by activating the appropriate CAS/DQM
strobes. During peripheral device packet transfers, DBEN remains high and D[63:0] is placed in high impedance
so that the peripheral device can drive data into the memory.
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79
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
State
Col A
Col B
Col C
r1
r2
r3
r6
rspin
rspin
col
col
ci†
col
drn
c1
c1
c1
CLKOUT
CT[2:0]
4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Idle
PAC
Col A
Col B
Col C
A
B
C
Drain
RL
Row
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
A
D[63:0]
B
C
0 For Normal Write, 1 For PDPT Write
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
A
B
C
† Internally generated pipeline bubble (example)
Figure 62. Pipelined 1-Cycle/Column Write-Cycle Timing
80
POST OFFICE BOX 1443
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r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
State
Col A
Col B
Col C
r1
r2
r3
r6
rspin
rspin
col
c1
col
ci†
col
r1
c1
c1
CLKOUT
CT[2:0]
5
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Row
Col A
Col B
A
B
A
B
Idle
PAC
RL
A[31:0]
Col C
RAS
CAS/DQM[7:0]
C
DSF
TRG/CAS
W
D[63:0]
C
0 For Normal Write, 1 For PDPT Write
DBEN
DDIN
For user-modified timing:
UTIME
RAS
A
CAS/DQM[7:0]
B
C
† Internally generated pipeline bubble (example)
Figure 63. Nonpipelined 1-Cycle/Column Write-Cycle Timing
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81
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
State
r1
r2
r3
r5
r6
rspin
Col A
col
col
c1
c2
Col B
col
col†
col
c1
c2
c2
ci‡
Col C
col
col
c1
c2
CLKOUT
CT[2:0]
6
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
STATUS[5:0]
PAC
PAC
Col A
Col B
Col C
B
C
Idle
PAC
RL
Row
A[31:0]
RAS
A
CAS/DQM[7:0]
DSF
TRG/CAS
W
A
D[63:0]
B
C
0 For Normal Write, 1 For PDPT Write
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
† Wait state inserted by external logic (example)
‡ Internally generated pipeline bubble (example)
A
B
Figure 64. 2-Cycle/Column Write-Cycle Timing
82
POST OFFICE BOX 1443
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C
r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
State
r1
r2
r3
r4
Col A
r5
r6
col
col
col
c1
c2
c3
Col B
col
col
col†
col
c1
c2
c3
c3
ci‡
col
col
col
c1
c2
c3
Col C
r1
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Row
Col A
Col B
Idle
PAC
RL
A[31:0]
Col C
RAS
A
CAS/DQM[7:0]
B
C
DSF
TRG/CAS
W
A
D[63:0]
B
C
0 For Normal Write, 1 For PDPT Write
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
† Wait state inserted by external logic (example)
‡ Internally generated pipeline bubble (example)
A
B
C
Figure 65. 3-Cycle/Column Write-Cycle Timing
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83
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles
Load-color-register (LCR) cycles are used to load a VRAM’s color register prior to performing a block-write. LCR
cycles are supported only on 64-bit data buses. An LCR cycle closely resembles a normal write cycle because
it writes into a VRAM. The difference is that the DSF output is high at both the fall of RAS and the fall of
CAS/DQM. Also, because the VRAM color register is a single location, only one column access occurs.
The row address that is output by the TC is used for bank-decode only. Normally, all VRAM banks should be
selected during an LCR cycle because another LCR cycle cannot occur when a block-write memory-page
change occurs. The column address that is output during an LCR is likewise irrelevant because the VRAM color
register is the only location written. All CAS/DQM strobes are active during an LCR cycle.
If exception support for a given bank is enabled, the EXCEPT [1:0] inputs are sampled during LCR column states
and must be at valid levels. A retry code (EXCEPT [1:0] = 10) at column time has no effect, however, because
only one column access is performed.
If the BW field of the configuration cache entry for the given bank indicates that the addressed memory supports
only simulated block-writes, the LCR cycle will be changed into a normal write cycle at the start of the simulated
block-write.
84
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles (continued)
State
r1
r2
r3
r6
rspin
rspin
c1
drn
PAC
Drain
r1
CLKOUT
CT[2:0]
4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
STATUS[5:0]
RL
Row
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 66. Pipelined 1-Cycle/Column Load-Color-Register-Cycle Timing
POST OFFICE BOX 1443
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85
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles (continued)
State
r1
r2
r3
r6
rspin
rspin
c1
r1
CLKOUT
CT[2:0]
5
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
STATUS[5:0]
PAC
RL
A[31:0]
Row
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 67. Nonpipelined 1-Cycle/Column Load-Color-Register-Cycle Timing
86
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles (continued)
State
r1
r2
r3
r5
r6
rspin
c1
c2
r1
CLKOUT
CT[2:0]
6
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
STATUS[5:0]
PAC
RL
Row
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color Value
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 68. 2-Cycle/Column Load-Color-Register-Cycle Timing
POST OFFICE BOX 1443
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87
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles (continued)
State
r1
r2
r3
r4
r5
r6
c1
c2
c3
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
STATUS[5:0]
PAC
RL
Row
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color Value
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 69. 3-Cycle/Column Load-Color-Register-Cycle Timing
88
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles
Block-write cycles cause the data stored in the VRAM color registers to be written to the memory locations
enabled by the appropriate data bits output on the D[63:0] bus. This allows up to a total of 64 bytes (depending
on the type of block-write being used) to be written in a single-column access. This cycle is identical to a standard
write cycle with the following exceptions:
D DSF is active (high) at the fall of CAS, enabling the block-write function within the VRAMs.
D Only 64-bit bus sizes are supported during block-write; therefore, BS[1:0] inputs are used to indicate the
type of block-write that is supported by the addressed VRAMs, rather than the bus size.
D The two or three LSBs (depending on the type of block-write) of the column address are ignored by the
VRAMs because these column locations are specified by the data inputs.
D The values output by the TC on D[63:0] represent the column locations to be written to, using the color
register value. Depending on the type of block-write supported by the VRAM, all of the data bits are not
necessarily used by the VRAMs.
D Block-writes always begin with a row access. Upon completion of a block-write, the memory interface
returns to state r1 to await the next access.
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89
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
State
Col A
Col B
Col C
r1
r2
r3
r6
rspin
rspin
col
c1
ci†
col
col
drn
c1
c1
CLKOUT
CT[2:0]
4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Row
Col A
Col B
Col C
A
B
C
Sel A
Sel B
Sel C
A
B
C
Idle
PAC
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
† Internally generated pipeline bubble (example)
Figure 70. Pipelined 1-Cycle/Column Block-Write-Cycle Timing
90
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Drain
r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
State
Col A
Col B
Col C
r1
r2
r3
r6
rspin
rspin
col
c1
col
ci†
col
r1
c1
c1
CLKOUT
CT[2:0]
5
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Row
Col A
Col B
Idle
PAC
RL
A[31:0]
Col C
RAS
A
CAS/DQM[7:0]
B
C
DSF
TRG/CAS
W
D[63:0]
Sel A
Sel B
Sel C
A
B
C
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
† Internally generated pipeline bubble (example)
Figure 71. Nonpipelined 1-Cycle/Column Block-Write-Cycle Timing
POST OFFICE BOX 1443
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91
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
State
r1
r2
r3
r5
r6
rspin
Col A
Col B
Col C
col
col
c1
c2
col
c1
col†
col
c2
c2
ci‡
col
col
c1
c2
CLKOUT
CT[2:0]
6
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Col A
Col B
Idle
PAC
RL
Row
A[31:0]
Col C
RAS
A
CAS/DQM[7:0]
B
C
DSF
TRG/CAS
W
Col Sel A
D[63:0]
Col Sel B
Col Sel C
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
† Wait state inserted by external logic (example)
‡ Internally generated pipeline bubble (example)
A
B
Figure 72. 2-Cycle/Column Block-Write-Cycle Timing
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C
r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
State
Col A
Col B
Col C
r1
r2
r3
r4
r5
r6
col
c1
col
c2
col
c3
col
col
col
col†
c1
c2
c3
c3
ci‡
col
col
col
c1
c2
c3
r1
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Idle
PAC
RL
† Wait state inserted by external logic (example)
‡ Internally generated pipeline bubble (example)
Figure 73. 3-Cycle/Column Block-Write-Cycle Timing
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93
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles
Read-transfer (memory-to-register) cycles transfer a row from the VRAM memory array into the VRAM shift
register (sequential-access memory, or SAM). This causes the entire SAM (both halves of the split SAM) to be
loaded with the array data.
Split-register read-transfer (memory-to-split-register) cycles also transfer data from a row in the memory array
to the SAM. However, these transfers cause only half of the SAM to be written. Split-register read transfers allow
the inactive half of the SAM to be loaded with the new data while the other active half continues to shift data
in or out.
Write-transfer (register-to-memory) cycles transfer data from the SAM into a row of the VRAM array. This
transfer causes the entire SAM (both halves of the split SAM) to be written into the array.
Split-register write-transfer (split-register-to-memory) cycles also transfer data from the SAM to a row in the
memory array. However, these transfers write only half of the SAM into the array. Split-register write transfers
allow the inactive half of the SAM to be transferred into memory while the other (active) half continues to shift
serial data in or out.
Read and split-read transfers resemble a standard read cycle. Write and split-write transfers resemble a
standard write cycle. The TRG/CAS output is driven low prior to the fall of RAS to indicate a transfer cycle. Only
a single column access is performed so RETRY, while required to be at a valid level, has no effect if asserted
at column time. The value output on A[31:0] at column time represents the SAM tap point.
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transfer cycles (continued)
State
r1
r2
r3
r6
c1
c2
c3
r1
CLKOUT
CT[2:0]
4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
Idle
RL
A[31:0]
Row
Tap Point
RAS
CAS/DQM[7:0]
DSF
0 for Full Transfer, 1 for Split Transfer
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 74. Pipelined 1-Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing
POST OFFICE BOX 1443
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
r1
r2
r3
c1
c2
PAC
Idle
r6
r1
CLKOUT
CT[2:0]
5
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
RL
Row
A[31:0]
Tap Point
RAS
CAS/DQM[7:0]
DSF
0 for Full Transfer, 1 for Split Transfer
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 75. Nonpipelined 1-Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing
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transfer cycles (continued)
State
r1
r2
r3
r5
r6
c1
c2
r1
CLKOUT
CT[2:0]
6
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
RL
A[31:0]
Row
Tap Point
RAS
CAS/DQM[7:0]
0 for Full Transfer, 1 for Split Transfer
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 76. 2-Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
r1
r2
r3
r4
r5
r6
c1
c2
c3
r1
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
STATUS[5:0]
PAC
RL
Row
A[31:0]
Tap Point
RAS
CAS/DQM[7:0]
DSF
0 for Full Transfer, 1 for Split Transfer
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 77. 3-Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing
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transfer cycles (continued)
State
r1
r2
r3
r6
rspin
rspin
c1
drn
PAC
Drain
r1
CLKOUT
CT[2:0]
4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
RL
A[31:0]
Row
Tap Point
RAS
CAS/DQM[7:0]
0 for Full Transfer, 1 for Split Transfer
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 78. Pipelined 1-Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
r1
r2
r3
r6
rspin
rspin
c1
r1
CLKOUT
CT[2:0]
5
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
RL
Row
A[31:0]
Tap Point
RAS
CAS/DQM[7:0]
0 for Full Transfer, 1 for Split Transfer
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 79. Nonpipelined 1-Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing
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transfer cycles (continued)
State
r1
r2
r3
r5
r6
rspin
c1
c2
rl
CLKOUT
CT[2:0]
6
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
Row
Tap Point
RL
A[31:0]
RAS
CAS/DQM[7:0]
0 for Full Transfer, 1 for Split Transfer
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 80. 2-Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
r1
r2
r3
r4
r5
r6
c1
c2
c3
r1
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
STATUS[5:0]
PAC
RL
Row
A[31:0]
Column
RAS
CAS/DQM[7:0]
0 for Full Transfer, 1 for Split Transfer
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 81. 3-Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing
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refresh cycles
Refresh cycles are generated by the TC at the programmed refresh interval. They are characterized by the
following signal activity:
D
D
D
D
D
D
CAS falls prior to RAS.
All CAS pins (CAS[7:0]) are active.
TRG, W, and DBEN all remain inactive (high) because no data transfer occurs.
DSF is active (high) at the fall of CAS and is driven inactive prior to the fall of RAS.
The data bus is driven to the high-impedance state.
The upper half of the address bus (A[31:16]) contains the refresh pseudo-address and the lower half
(A[15:0]) is driven to all zeros.
D If RETRY is asserted at any sample point during the cycle, the cycle timing is not modified. Instead, the
pseudo-address and backlog counters are simply not decremented.
D Selecting user-modified timing has no effect on the cycles.
D Upon completion of the refresh cycle, the memory interface returns to state r1 to await the next access.
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refresh cycles (continued)
State
r1
r2
r3
r6
r9
CLKOUT
CT[2:0]
4/5
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
RL
A[31:16]
Refresh Pseudo Address
A[15:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Figure 82. 1-Cycle/Column Refresh-Cycle Timing
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r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
refresh cycles (continued)
State
r1
r2
r3
r5
r6
r7
r9
r1
CLKOUT
CT[2:0]
6
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
RL
A[31:16]
Refresh Pseudo Address
A[15:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Figure 83. 2-Cycle/Column Refresh-Cycle Timing
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
refresh cycles (continued)
State
r1
r2
r3
r4
r5
r6
r7
r8
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
RL
Refresh Pseudo Address
A[31:16]
A[15:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Figure 84. 3-Cycle/Column Refresh-Cycle Timing
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PAC
r9
r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM-type cycles
The SDRAM-type cycles support the use of SDRAM, SGRAM, or SVRAM devices for single-cycle memory
accesses. While SDRAM cycles use the same state sequences as DRAM cycles, the memory-control signal
transitions are modified to perform SDRAM command cycles. The supported SDRAM commands are:
DCAB
Deactivate (precharge) all banks
ACTV
Activate the selected bank and select the row
READ
Input starting column address and start read operation
WRT
Input starting column address and start write operation
MRS
Set SDRAM mode register
REFR
Auto-refresh cycle with internal address
SRS
Set special register (color register)
BLW
Block write
SDRAM cycles begin with an activate (ACTV) command followed by the requested column accesses. When
a memory-page change occurs, the selected bank is deactivated with a DCAB command.
The SMJ320C80 supports CAS latencies of 2 or 3 cycles and burst lengths of 1 or 2. These are selected by the
CT code input at the start of the access.
The column pipelines for SDRAM accesses are shown in Figure 85. Idle cycles can occur after necessary
column accesses have completed or between column accesses due to “bubbles” in the TC data flow pipeline.
The pipeline diagrams show the pipeline stages for each access type and when the CAS/DQM signal
corresponding to the column access is activated.
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SDRAM type cycles (continued)
#
#
' 1
' 3
1
#
' #
' ' 1
Burst-length 2, 3-cycle latency reads, read transfers,
split-read transfers
1
#
3#
' 3
Burst-length 2, 2-cycle latency reads, read transfers,
split-read transfers
3#
1
Burst-length 1 writes, block writes, SRSs, write transfers,
split-write transfers
1
' 3
' ' Burst-length 1, 3-cycle latency reads, read
transfers, split-read transfers
Burst-length 1, 2-cycle latency reads, read
transfers, split-read transfers
#
3#
Burst-length 2, 3-cycle latency writes
Burst-length 2, 3-cycle latency block-writes, write
transfers, split-write transfers
Figure 85. SDRAM Column Pipelines
special SDRAM cycles
To initialize the SDRAM properly, the SMJ320C80 performs two special SDRAM cycles after reset. The ’C80
first performs a deactivate cycle on all banks (DCAB) and then initializes the SDRAM mode register with a mode
register set (MRS) cycle. The CT code input at the start of the MRS cycle determines the burst length and latency
that is programmed into the SDRAM mode register.
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special SDRAM cycles (continued)
State
r1
r2
r3
r5
r1
CLKOUT
CT[2:0]
0xx
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
Figure 86. SDRAM Power-Up Deactivate Cycle Timing
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
special SDRAM cycles (continued)
State
r1
r2
r3
r5
r1
CLKOUT
CT[2:0]
0xx
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
Figure 87. SDRAM Mode-Register-Set Cycle Timing
SDRAM read cycles
Read cycles begin with an activate (ACTV) command to activate the bank and to select the row. The TC outputs
the column address and activates the TRG/CAS strobe for each read command. For burst-length 1 accesses,
a read command can occur on each cycle. For burst-length 2 accesses, a read command can occur every two
cycles. The TC places D[63:0] into the high-impedance state, allowing it to be driven by the memory, and latches
input data during the appropriate column state. The TC always reads 64 bits and extracts and aligns the
appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. The CAS/DQM strobes are
activated two cycles before input data is latched. If the second column in a burst is not required, then CAS/DQM
is not activated. During peripheral device packet transfers, DBEN remains high.
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SDRAM read cycles (continued)
State
r1
r2
r3
r5
Col Pipe
r6
Col A
Col B
Col C
Col D
col
c1
col
col
c2
c1
c3
c2
c1
col
col
r1
c3
c2
c1
c3
c2
c3
DCAB
CLKOUT
CT[2:0]
0
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
PAC
PAC
Row
Col A
Col B
Col C
Col D
A
B
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
C
D
0 For Normal Read, 1 For PDPT read
DBEN
DDIN
Command
ACTV
READ
READ
READ
READ
DCAB
Figure 88. SDRAM Burst-Length 1, 2-Cycle Latency Read-Cycle Timing
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM read cycles (continued)
State
r1
r2
r3
r5
r6
Col A
Col B
Col C
Col D
Col Pipe
col
c1
col
col
col
col
col
r1
c2
c1
c3
c2
c1
c4
c3
c2
c1
c4
c3
c2
c4
c3
c4
PAC
Idle
DCAB
B
C
CLKOUT
CT[2:0]
1
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
PAC
Row
Col A
Col B
Col C
RL
A[31:0]
Col D
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
A
0 For Normal Read, 1 For PDPT Read
DBEN
DDIN
Command
ACTV
READ
READ
READ
READ
Figure 89. SDRAM Burst-Length 1, 3-Cycle Latency Read-Cycle Timing
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DCAB
D
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM read cycles (continued)
State
r1
r2
r3
r5
Col Pipe
r6
col
col
col
Col A
Col B
Col C
Col D
c1
c2
c1
c3
c2
c1
col
col
r1
c3
c2
c1
c3
c2
c3
CLKOUT
CT[2:0]
2
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
DCAB
PAC
RL
A[31:0]
Row
Col A
(Col B)
Col C
(Col D)
A
B
C
D
RAS
CAS/DQM[7:0]
DSF
A, B
TRG/CAS
C, D
W
D[63:0]
A
B
C
D
0 For Normal Read, 1 For PDPT Read
DBEN
DDIN
Command
ACTV
READ
READ
DCAB
Figure 90. SDRAM Burst-Length 2, 2-Cycle Latency Read-Cycle Timing
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM read cycles (continued)
State
r1
r2
r3
r5
Col Pipe
r6
col
col
col
col
col
col
r1
Col A
Col B
Col C
Col D
c1
c2
c1
c3
c2
c1
c4
c3
c2
c1
c4
c3
c2
c4
c3
c4
Idle
DCAB
CLKOUT
CT[2:0]
3
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
RL
A[31:0]
Row
Col A
(Col B)
Col C
A
B
(Col D)
RAS
CAS/DQM[7:0]
C
D
A
B
DSF
A, B
TRG/CAS
C, D
W
D[63:0]
C
0 For Normal Read, 1 For PDPT Read
DBEN
DDIN
Command
ACTV
READ
READ
Figure 91. SDRAM Burst-Length 2, 3-Cycle Latency Read-Cycle Timing
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DCAB
D
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM write cycles
Write cycles begin with an activate (ACTV) command to activate the bank and select the row. The TC outputs
the column address and activates the TRG/CAS and W strobes for each write command. For burst-length 1
accesses, a write command can occur on each cycle. For burst-length 2 accesses, a write command can occur
every two cycles. The TC drives data out on D[63:0] during each cycle of an active-write command and indicates
valid bytes by driving the appropriate CAS/DQM strobes low. During peripheral device packet transfers, DBEN
remains high and D[63:0] are placed in the high-impedance state so that the peripheral can drive data into the
memories.
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SDRAM write cycles (continued)
State
Col Pipe
r1
r2
r3
r5
r6
rspin
Col A
Col B
Col C
Col D
col
c1
col
col
col
col
col
Idle
DCAB
c1
c1
c1
CLKOUT
CT[2:0]
0,1
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
PAC
PAC
Col A
Col B
Col C
A
B
C
D
A
B
C
D
A
B
C
D
RL
A[31:0]
Row
Col D
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
0 For Normal Read, 1 For PDPT Read
DBEN
DDIN
Command
ACTV
WRT
WRT
WRT
WRT
Figure 92. SDRAM Burst-Length 1 Write-Cycle Timing
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DCAB
r1
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM write cycles (continued)
State
Col Pipe
r1
r2
r3
r5
r6
rspin
Col A
Col B
Col C
Col D
col
c1
col
col
col
col
col
Idle
DCAB
r1
c1
c1
c1
CLKOUT
CT[2:0]
2, 3
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
PAC
Cycle Type
PAC
RL
A[31:0]
Row
Col A
(Col B)
Col C
A
B
C
(Col D)
RAS
CAS/DQM[7:0]
D
DSF
A, B
TRG/CAS
C, D
W
D[63:0]
A
B
C
D
DBEN
DDIN
Command
ACTV
WRT
WRT
DCAB
Figure 93. SDRAM Burst-Length 2 Write-Cycle Timing
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special register set cycles
Special register set (SRS) cycles are used to program control registers within an SVRAM or SGRAM. The ’C80
only supports programming of the color register for use with block-writes. The cycle is similar to a single
burst length 1 write cycle but DSF is driven high. The values output on the ’C80 address bits cause the color
register to be selected as shown in Figure 94.
SDRAM Address Pin
BS
A8
A7
A6
A5
A4
SDRAM Function
0
0
0
LC
LM
LS
SMJ320C80 Output Value
0
0
0
1
0
0
A3
A2
A1
A0
Stop Register
0
0
0
0
Figure 94. Special-Register-Set Value
State
r1
r2
r6
r3
rspin
rspin
col
c1
Col Pipe
CLKOUT
CT[2:0]
0xx
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
Row
SRS
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color
D[63:0]
DBEN
DDIN
SRS
Command
Figure 95. SDRAM SRS-Cycle Timing
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SDRAM block-write cycles
Block-write cycles allow SVRAMs and SGRAMs to write a stored color value to multiple column locations in a
single access. Block-write cycles are similar to write cycles except that DSF is driven high to indicate a
block-write command. Because burst is not supported for block-write, burst-length 2 accesses generate a single
block-write every other clock cycle.
State
Col Pipe
r1
r2
r3
r5
r6
rspin
Col A
Col B
Col C
Col D
col
c1
col
col
col
col
col
Idle
DCAB
r1
c1
c1
c1
CLKOUT
CT[2:0]
0,1
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
PAC
PAC
Col A
Col B
Col C
A
B
C
D
A
B
C
D
Sel A
Sel B
Sel C
Sel D
BLKW
BLKW
BLKW
BLKW
RL
A[31:0]
Row
Col D
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Command
ACTV
DCAB
Figure 96. SDRAM Burst-Length 1 Block-Write Cycle Timing
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SDRAM block-write cycles (continued)
State
Col Pipe
r1
r2
r3
r5
r6
rspin
Col A
Col B
col
c1
col
col
col
col
col
Idle
DCAB
c1
CLKOUT
CT[2:0]
2, 3
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
PAC
Cycle Type
PAC
RL
A[31:0]
Row
Col A
Col B
A
B
A
B
Sel A
Sel B
BLKW
BLKW
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Command
ACTV
Figure 97. SDRAM Burst-Length 2 Block-Write Cycle Timing
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SVRAM transfer cycles
The SVRAM read- and write-transfer cycles transfer data between the SVRAM memory-array and the serial
register (SAM). The SMJ320C80 supports both normal and split transfers for SVRAMs. Read- and split-read
transfers resemble a standard read cycle. Write- and split-write transfers resemble a standard write cycle.
Because the ’C80’s TRG output is used as CAS, external logic must generate a TRG signal (by decoding
STATUS) to enable the SVRAM transfer cycle. The value output on A[31:0] at column time represents the SAM
tap point.
State
Col Pipe
r1
r2
r5
r3
r6
col
c1
col
c2
r1
c3
CLKOUT
CT[2:0]
000
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
Row
Tap Pt.
DCAB
RL
A[31:0]
RAS
CAS/DQM[7:0]
0 For Full, 1 For Split
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
Command
RTR
DCAB
Figure 98. SVRAM Burst-Length 1, 2-Cycle Latency Read-Transfer Cycle Timing
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SVRAM transfer cycles (continued)
State
Col Pipe
r1
r2
r3
col
c1
col
c2
col
c3
Cycle Type
PAC
Idle
DCAB
Row
Tap Pt.
r5
r6
CLKOUT
CT[2:0]
001
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
0 For Full, 1 For Split
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
Command
RTR
DCAB
Figure 99. SVRAM Burst-Length 1, 3-Cycle Latency Read-Transfer Cycle Timing
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SVRAM transfer cycles (continued)
State
Col Pipe
r1
r2
r3
col
c1
col
c2
col
c3
Cycle Type
PAC
Idle
DCAB
Row
Tap Pt.
r5
r6
r1
CLKOUT
CT[2:0]
010
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
0 For Full, 1 For Split
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
Command
RTR
DCAB
Figure 100. SVRAM Burst-Length 2, 2-Cycle Latency Read-Transfer Cycle Timing
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SVRAM transfer cycles (continued)
State
Col Pipe
r1
r2
r3
r5
r6
col
col
c1
col
c2
col
c3
CLKOUT
CT[2:0]
011
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
Row
Tap Pt.
Idle
DCAB
RL
A[31:0]
RAS
CAS/DQM[7:0]
0 For Full, 1 For Split
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Command
ACTV
RTR
DCAB
Figure 101. SVRAM Burst-Length 2, 3-Cycle Latency Read-Transfer Cycle Timing
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SVRAM transfer cycles (continued)
State
Col Pipe
r1
r2
r3
col
c1
col
col
Cycle Type
PAC
Idle
DCAB
Row
Tap Pt.
r5
r6
r1
CLKOUT
CT[2:0]
00x
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
0 For Full, 1 For Split
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
Command
WTR
DCAB
Figure 102. SVRAM Burst-Length 1, Write-Transfer Cycle Timing
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SVRAM transfer cycles (continued)
r1
State
Col Pipe
r2
r3
r5
r6
col
c1
col
col
col
r1
CLKOUT
01x
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
Row
Tap Pt.
Idle
DCAB
RL
A[31:0]
RAS
CAS/DQM[7:0]
0 For Full, 1 For Split
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
Command
WTR
DCAB
Figure 103. SVRAM Burst-Length 2, Write-Transfer Cycle Timing
SDRAM refresh cycle
The SDRAM refresh cycle is performed when the TC receives an SDRAM cycle timing input (CT=0xx) at the
start of a refresh cycle. The RAS and TRG/CAS outputs are driven low for one cycle to strobe a refresh
command (REFR) into the SDRAM. The refresh address is generated internal to the SDRAM. The ’C80 outputs
a 16-bit pseudo-address (used for refresh bank decode) on A[31:16] and drives A[15:0] low.
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SDRAM refresh cycle (continued)
State
r1
r2
r3
r5
r6
r9
r1
CLKOUT
CT[2:0]
0xx
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
RL
A[31:16]
Refresh Pseudo-Address
A[15:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Command
REFR
Figure 104. SDRAM Refresh Cycle Timing
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host interface
The ’C80 contains a simple four-pin mechanism by which a host or another device can gain control of the ’C80
local memory bus. The HREQ input can be driven low by the host to request the ’C80’s bus. Once the TC has
completed the current memory access, it places the local bus (except CLKOUT) into a high-impedance state.
It then drives the HACK output low to indicate that the host device owns the bus and can drive it. The REQ[1:0]
outputs reflect the highest-priority cycle request being received internally by the TC. The host can monitor these
outputs to determine if it needs to relinquish the local bus back to the ’C80.
Table 37. TC Priority Cycles
REQ[1:0]
ASSOCIATED INTERNAL TC REQUEST
11
SRT, urgent refresh, XPT, or VCPT
10
Cache/DEA request, urgent packet transfer
01
High-priority packet transfer
00
Low-priority packet transfer, trickle refresh, idle
device reset
The SMJ320C80 is reset when the RESET input is driven low. The ’C80 outputs immediately go into a
high-impedance state with the exception of CLKOUT, HACK, and REQ[1:0]. While RESET is low, all internal
registers are set to their default values and internal logic is reset.
On the rising edge of RESET, the state of UTIME is sampled to determine if big-endian (UTIME = 0) or
little-endian (UTIME = 1) operation is selected. Also, on the rising edge of RESET, the state of HREQ is sampled
to determine if the master processor comes up running (HREQ = 0) or halted (HREQ = 1).
Once RESET is high, the ’C80 drives the high-impedance signals to their inactive values. The TC then performs
32 refresh cycles to initialize system memory. If, during initialization refresh, the TC receives an SDRAM cycle
timing code (CT = 0xx), it performs an SDRAM DCAB cycle and a MRS cycle to initialize the SDRAM, and then
continues the refresh cycles.
After completing initialization refresh, if the MP is running, the TC performs its instruction-cache-fill request to
fetch the cache block beginning at 0xFFFFFFC0. This block contains the starting MP instruction located at
0xFFFFFFF8. If the MP comes up halted, the instruction cache fill does not take place until the first occurrence
of an EINT3 interrupt to unhalt the MP.
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absolute maximum ratings over specified temperature ranges (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Case temperature, TC (M-temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
(A-temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
UNIT
3.135
3.3
3.465
V
0
0
0
V
VDD
VSS
Supply voltage
IOH
IOL
High-level output current
–400
µA
Low-level output current
2
mA
TC
Case temperature
Supply voltage (see Note 2)
M-temperature
–55
125
A-temperature
–40
85
°C
NOTE 2: To minimize noise on VSS, care should be taken to provide a minimum inductance path between the VSS pins and system ground.
electrical characteristics over recommended range of supply voltage and specified temperature
(unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
MIN
VIH
VIL
High-level input voltage
2
Low-level input voltage
–0.3
VOH
VOL
High-level output voltage
IO
II
IDD
VDD = MIN,
VDD = MAX
IOH = MAX
Low-level output voltage
Out ut current, leakage (high im
Output
impedance)
edance)
(except EMU0 and EMU1)
VDD = MAX,
VDD = MAX,
VO = 2.8 V
VO = 0.6 V
Input current (except TCK, TDI, and TMS), TRST
VI = VSS to VDD
VDD = MAX,
50 MHz
Supply current (see Note 3)
TYP§
MAX
UNIT
VDD + 0.3
0.8
V
2.2
V
0.8
Ci
V
20
–20
1§
10§
V
µA
A
±20
µA
2.5
A
Input capacitance
pF
Co
Output capacitance
10§
pF
‡ For conditions shown as MIN/MAX, use the appropriate value specified under the recommended operating conditions.
§ All typical values are at VDD = 3.3 V, TA = 25°C
¶ Typical steady-state VOH will not exceed VDD
NOTE 3: Maximum supply current is derived from a test case that generates the theoretical maximum data flow using a worst case checkerboard
data pattern on a sustained cycle by cycle basis. Actual maximum IDD varies in real applications based on internal and external data
flow and transitions. Typical supply current is derived from a test case which attempts to emulate typical use conditions of the on-chip
processors with random data. Typical IDD varies from application to application based on data flow and transitions and on-chip processor
utilization.
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PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CT
IOH
Where:
IOL
IOH
VLOAD
CT
=
=
=
=
2.0 mA (all outputs)
400 µA (all outputs)
1.5 V
60 pF typical load circuit capacitance
Figure 105. Test Load Circuit
signal transition levels
TTL-output levels are driven to a minimum logic-high level of 2.2 V and to a maximum logic-low level of
0.8 V. Figure 106 shows the TTL-level outputs.
2.2 V
1.75 V
1.0 V
0.8 V
Figure 106. TTL-Level Outputs
TTL-output transition times are specified as follows:
D For a high-to-low transition, the level at which the output is said to be no longer high is 1.75 V, and the level
at which the output is said to be low is 1.0 V.
D For a low-to-high transition, the level at which the output is said to be no longer low is 1.0 V, and the level
at which the output is said to be high is 1.75 V.
Figure 107 shows the TTL-level inputs.
2V
0.8 V
Figure 107. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
2 V, and the level at which the input is said to be low is 0.8 V.
D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V, and the level at which the input is said to be high is 2 V.
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PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
A
A[31:0]
RDY
READY
CAS
CAS/DQM[7:0]
RST
RESET
CFG
AS[2:0], BS[1:0], CT[2:0], PS[3:0], UTIME
RTY
RETRY
CKI
CLKIN
REQ
REQ[1:0]
CKO
CLKOUT
RL
RL
CMP
RETRY, READY, FAULT
RR
READY, RETRY
D
D[63:0]
SCK
SCLK0, SCLK1
EIN
EINT1, EINT2, EINT3, or EINTx
TCK
TCK
EMU
EMU0, EMU1
TDI
TDI
FCK
FCLK0, FCLK1
TDO
TDO
HAK
HACK
TMS
TMS
HRQ
HREQ
TRS
TRST
LIN
LINT4
UTM
UTIME
MID
A[31:0], STATUS[5:0]
SI
HSYNC0, VSYNC0, CSYNC0, HSYNC1, VSYNC1,
or CSYNC1
OUT
A[31:0], CAS/DQM[7:0], D[63:0], DBEN, DDIN,
DSF, RAS, RL, STATUS[5:0], TRG/CAS, W
SY
HSYNC0, VSYNC0, CSYNC0/HBLNK0,
CBLNK0/VBLNK0, HSYNC1, VSYNC1,
CSYNC1/HBLNK1, CBLNK1/VBLNK1, CAREA0, or
CAREA1
RAS
RAS
XPT
XPT[2:0] OR XPTx
Lowercase subscripts and their meanings are:
The following letters and symbols and their meanings are:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
h
hold time
Z
High impedance
su
setup time
X
Unknown, changing, or don’t care level
t
transition time
w
pulse duration (width)
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general notes on timing parameters
The period of the output clock (CLKOUT) is twice the period of the input clock (CLKIN), or 2 × tc(CKI). The half
cycle time (tH) that appears in the following tables is one-half of the output clock period, or equal to the input
clock period, tc(CKI).
All output signals from the ’C80 (including CLKOUT) are derived from an internal clock such that all output
transitions for a given half cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.
CLKIN timing requirements (see Figure 108)
NO
1
2
3
4
MIN
MAX
UNIT
tc(CKI)
tw(CKIH)
Period of CLKIN (tH)
10
ns
Pulse duration of CLKIN high
4.2
ns
tw(CKIL)
tt(CKI)
Pulse duration of CLKIN low
4.2
Transition time of CLKIN
ns
1.5*
ns
* This parameter is not production tested.
1
4
2
4
CLKIN
3
Figure 108. CLKIN Timing
local-bus switching characteristics over full operating range: CLKOUT† (see Figure 109)
NO
5
6
7
8
PARAMETER
tc(CKO)
tw(CKOH)
Period of CLKOUT
tw(CKOL)
tt(CKO)
Pulse duration of CLKOUT low
MIN
MAX
2tc(CKI)‡*
tH–4.5
Pulse duration of CLKOUT high
ns
ns
tH–4.5
Transition time of CLKOUT
UNIT
ns
2.5*
ns
† The CLKOUT output has twice the period of CLKIN. No propagation delay or phase relationship to CLKIN is ensured. Each state of a memory
access begins on the falling edge of CLKOUT.
‡ This parameter can also be specified as 2tH.
* This parameter is not production tested.
tH
5
tH
tH
tH
8
6
8
CLKOUT
7
Figure 109. CLKOUT Timing
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device reset timing requirements (see Figure 110)
NO
MIN
Initial reset during power-up
MAX
UNIT
6th
6th
ns
ns
Hold time, HREQ low after RESET high to configure self-bootstrap mode
4th
0
Setup time of UTIME low to RESET high to configure big-endian operation
4th
ns
Hold time, UTIME low after RESET high to configure big-endian operation
0
ns
9
tw(RSTL)
P l duration,
d ti
l
Pulse
RESET low
10
Setup time of HREQ low to RESET high to configure self-bootstrap mode
11
tsu(HRQL-RSTH)
th(RSTH-HRQL)
12
tsu(UTML-RSTH)
13
th(RSTH-UTML)
Reset during active operation
ns
ns
9
RESET
10
11
HREQ
13
12
UTIME
Figure 110. Device-Reset Timing
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local bus timing requirements: cycle configuration inputs (see Figure 111)
The cycle configuration inputs are sampled at the beginning of each row access during the r2 state. The inputs
typically are generated by a static decode of the A[31:0] and STATUS[5:0] outputs.
NO
14
15
16
MIN
tsu(CFGV-CKOH)
th(CKOH-CFGV)
ta(MIDV-CFGV)
UNIT
Setup time, AS, BS, CT, PS, and UTIME valid to CLKOUT no longer low
8
ns
Hold time, AS, BS, CT, PS, and UTIME valid after CLKOUT high
2
ns
Access time, AS, BS, CT, PS, and UTIME valid after memory identification
(A, STATUS) valid
tH
tH
tH
tH
3tH – 10
tH
CLKOUT
Cycle Type
STATUS[5:0]
Row Address
A[31:0]
15
RL
16
14
AS[2:0]
Valid
BS[1:0]
Valid
CT[2:0]
Valid
PS[3:0]
Valid
UTIME
Valid
Figure 111. Local Bus Timing: Cycle Configuration Inputs
134
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tH
ns
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing: cycle completion inputs (see Figure 112 and Figure 113)
The cycle completion inputs are sampled at the beginning of each row access at the start of the r3 state. The
READY input is sampled also at the start of the r6 state and during each column access (2 and 3 cyc/col
accesses only). The RETRY input is sampled on each CLKOUT falling edge following r3. The value n as used
in the parameters represents the integral number of half cycles between the transitions of the two signals in
question.
NO
MIN
Access time, RETRY, READY, FAULT valid after memory identification
(A, STATUS) valid
17
ta(MIDV-CMPV)
18
tsu(CMPV-CKOL)
th(CKOL-CMPV)
Setup time, RETRY, READY, FAULT valid to CLKOUT no longer high
7.5
Hold time, RETRY, READY, FAULT valid after CLKOUT low
1.2
ta(RASL-RRV)
ta(RLL-RRV)
Access time RETRY, READY valid from RAS low
19
20
21
22
ta(CASL-RRV)
(CASL RRV)
POST OFFICE BOX 1443
UNIT
ntH–8
ns
ns
ns
ntH–7.5
ntH–7.5
Access time, RETRY, READY valid from RL low
Access time
time, READY valid from CAS low
MAX
2 cyc/col accesses
tH–12
3 cyc/col accesses
2tH–8
• HOUSTON, TEXAS 77251–1443
ns
ns
ns
135
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing: cycle completion inputs (continued)
tH
tH
tH
tH
tH
tH
tH
tH
CLKOUT
STATUS[5:0]
A[31:0]
RL
RAS
17
18
21
19
20
RETRY
READY
FAULT
Figure 112. Local Bus Timing: Row-Time Cycle Completion Inputs
136
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
tH
tH
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing: cycle completion inputs (continued)
tH
tH
tH
tH
tH
tH
tH
tH
tH
tH
CLKOUT
STATUS[5:0]
A[31:0]
CAS/DQM[7:0]
18
22
19
17
READY
RETRY
Figure 113. Local Bus Timing: Column-Time Cycle Completion Inputs
POST OFFICE BOX 1443
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137
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
general output signal characteristics over operating conditions
The following general timing parameters apply to all SMJ320C80 output signals unless otherwise specifically
given. The value n as used in the parameters represents the integral number of half cycles between the
transitions of the two outputs in question. For timing purposes, outputs fall into one of three groups – the data
bus (D[63:0]); the other output buses (A[31:0], STATUS[5:0], CAS/DQM[7:0]; and non-bus outputs (DBEN, RL,
DDIN, DSF, RAS, TRG/CAS, W). When measuring output to output, the named group refers to the second
output to transition (output B), and the first output (output A) refers to any output group.
NO
PARAMETER
MIN
23
th(OUTV-CKOL)
Hold time, CLKOUT high after output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
24
th(OUTV-CKOH)
Hold time, CLKOUT low after output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
25
th(CKOL-OUTV)
th(CKOH-OUTV)
26
Hold time, output valid after CLKOUT low
Hold time, output valid after CLKOUT high
27
th(OUTV-OUTV)
Hold time, output valid after output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
28
td(CKOH-OUTV)
Delay time, CLKOUT no longer low to output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS,TRG/CAS, W, RL
29
td(CKOL-OUTV)
Delay time, CLKOUT no longer high to output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS,TRG/CAS, W, RL
30
td(OUTV-CKOH)
td(OUTV-CKOL)
31
ntH–5.6
ntH–5.0†
ntH–4.3
ntH–5.6
ntH–5.0†
ntH–4.3
ns
ns
ns
ntH–6.5
ntH–6.0†
ntH–5
ns
ntH+6.5
ntH+5.5†
ntH+5
ntH+6.5
ntH+5.5†
ntH+5
Delay time, output no longer valid to CLKOUT low
ntH+5
ntH+5.5
ntH+6.5
ntH+6.0†
ntH+5
32
td(OUTV-OUTV)
33
tw(OUTV)
Pulse duration, output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
† Except for CAS/DQM[7:0] during nonuser-timed 2-cycle/column accesses
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ntH–6.5
ntH–6.0†
ntH–5.0
UNIT
ns
ntH–5.5
ntH–5
Delay time, output no longer valid to CLKOUT high
Delay time, output no longer valid to output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
138
MAX
ns
ns
ns
ns
ns
ns
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
general output signal characteristics over operating conditions (continued)
tH
tH
tH
tH
tH
tH
tH
tH
tH
tH
tH
tH
CLKOUT
30
26
28
24
Output A
25
31
32
23
27
29
Output B
33
Figure 114. General Output-Signal Timing
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139
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
data input timing (see Figure 115)
The following general timing parameters apply to the D[63:0] inputs unless otherwise specifically given. The
value n as used in the parameters represents the integral number of half cycles between the transitions of the
output and input in question.
NO
34
35
36
37
38
39
40
PARAMETER
MIN
MAX
UNIT
ta(CKOH-DV)
ta(CKOL-DV)
Access time, CLKOUT high to D[63:0] valid
tsu(DV-CKOH)
tsu(DV-CKOL)
Setup time, D[63:0] valid to CLKOUT no longer low
6.1
ns
Setup time, D[63:0] valid to CLKOUT no longer high
6.1
ns
th(CKOL-DV)
th(CKOH-DV)
Hold time, D[63:0] valid after CLKOUT low
2
ns
Hold time, D[63:0] valid after CLKOUT high
2
ns
ta(OUTV-DV)
ntH–5.3
ntH–6.5
Access time, CLKOUT low to D[63:0] valid
Access time, output valid to D[63:0] inputs valid A[31:0], CAS/DQM[7:0]†,
STATUS[5:0], RL
DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W
ns
ns
ntH–7
ns
ntH–6.5
41 th(OUTV-DV)‡
Hold time, D[63:0] valid after output valid RAS, CAS/DQM[7:0], A[31:0]
3
† Except CAS/DQM[7:0] during nonuser-timed 2-cycle/column accesses
‡ Applies to RAS, CAS/DQM[7:0], and A[31:0] transitions that occur on CLKOUT edge coincident with input data sampling
tH
tH
tH
tH
tH
tH
tH
tH
tH
tH
CLKOUT
38
39
37
36
34
35
D[63:0]
41
40
Output
Figure 115. Data-Input Timing
140
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
tH
ns
tH
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing: 2-cycle/column CAS timing
These timing parameters apply to the CAS/DQM[7:0] signals during 2-cycle-per-column memory accesses
only. They should be used in place of the general output and data input timing parameters when the
2-cycle/column (nonuser-timed) cycle timing is selected (CT[2:0] inputs = 0b110). The value n as used in the
parameters represents the integral number of half cycles between the transitions of the signals in question.
NO
42
43
MIN
tw(CASH)
tw(CASL)
Pulse duration, CAS/DQM high
MAX
tH–2
3tH–9.5
Pulse duration, CAS/DQM low
Hold time, CAS/DQM high after output valid
D[63:0]
A[31:0], STATUS[5:0]
DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W
44
th(OUTV-CASL)
45
Hold time, output valid after CAS/DQM low
46
th(CASL-OUTV)
ta(CASL-DV)
47
th(CASH-DV)
Hold time, data valid after CAS/DQM high
tH
tH
tH
tH
ns
ns
ntH–4.5
ntH–4.0
ntH–3
ntH–9.5
Access time, data valid from CAS/DQM low
ns
ns
3tH–12
2
tH
tH
tH
tH
tH
UNIT
ns
ns
tH
CLKOUT
42
43
CAS/DQM[7:0]
44
45
Output
47
46
D[63:0]
Figure 116. 2-Cycle/Column CAS Timing
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141
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
external interrupt timing (see Figure 117)
The following description defines the timing of the edge-triggered interrupts EINT1 – EINT3 and the
level-triggered interrupt LINT4 (see Note 4).
NO
48
49
50
MIN
tw(EINL)
tsu(EINH-CKOH)
Pulse duration, EINTx low
tw(EINH)
tsu(LINL-CKOL)
Pulse duration, EINTx high
Setup time, EINTx high before CLKOUT no longer low
51
Setup time, LINT4 low before CLKOUT no longer high
† This parameter must only be met to ensure that the interrupt is recognized on the indicated cycle.
* This parameter is not production tested.
NOTE 4: In order to ensure recognition, LINT4 must remain low until cleared by the interrupt service routine.
Interrupt Recognized
CLKOUT
49
50
EINTx
51
48
LINT4
Figure 117. External Interrupt Timing
142
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
MAX
UNIT
6*
9.5†
ns
6*
9.5†
ns
ns
ns
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
XPT input timing (see Figure 118 and Figure 119)
The following description defines the sampling of the XPT[2:0] inputs. The value encoded on the XPT[2:0] inputs
is synchronized over multiple cycles to ensure that a stable value is present.
NO
52
53
54
MIN
tw(XPTV)
tsu(XPTV-CKOH)
Pulse duration, XPTx valid
th(CKOH-XPTV)
th(RLL-XPTV)
Hold time, XPT[2:0] valid after CLKOUT high
MAX
12tH*
12†
Setup time, XPT[2:0] valid before CLKOUT no longer low
ns
ns
5
XPT Inputs Sampled
ns
6tH‡*
55
Hold time, XPT[2:0] valid after RL low
† This parameter must only be met to ensure that the XPT input is recognized on the indicated cycle.
‡ This parameter must be met to ensure that a second XPT request does nor occur.
* This parameter is not production tested.
UNIT
ns
XPT Inputs Recognized
CLKOUT
53
54
52
XPT[2:0]
Figure 118. XPT Input Timing – XPT Recognition
CLKOUT
STATUS[5:0]
XPTn Row Status
RL
55
XPT[2:0]
XPTn
XPTz
Figure 119. XPT Input Timing – XPT Service
POST OFFICE BOX 1443
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143
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
host-interface timing (see Figure 120)
’C80-40
NO
56
MIN
tsu(REQV-CKOH)
th(CKOH-REQV)
Setup time, REQ1–REQ0 valid to CLKOUT no longer low
57
58
th(HRQL-HAKL)
Hold time for HACK high after HREQ goes low*
td(HAKL-OUTZ)
Dela time,
Delay
time HACK low
lo to output
o tp t hi-Z
hi Z
60
td(HRQH-HAKH)
td(HAKH-OUTD)
Delay time, HREQ high to HACK no longer low
Delay time, HACK high to outputs driven†
61
tH – 7
tH – 7
Hold time, REQ1–REQ0 valid after CLKOUT high
59
D[63:0]
1*
10
CLKOUT
57
REQ[1:0]
62
58
60
HACK
61
59
A[31:0]
RL, TRG,
WE, DSF,
DSF2, DBEN
RAS
CAS[7:0]
D[63:0]
DDIN
Figure 120. Host-Interface Timing
144
POST OFFICE BOX 1443
ns
1*
HREQ Sampled
HREQ
ns
4tH – 12*
6tH
8.5
• HOUSTON, TEXAS 77251–1443
UNIT
ns
All signals except D[63:0]
62 tsu(HRQL-CKOH) Setup time, HREQ low to CLKOUT no longer low (see Note 5)
* This parameter is not production tested.
NOTE 5: Parameter must be met only to ensure HREQ recognition during the indicated clock cycle.
56
MAX
ns
ns
ns
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
video interface timing: SCLK timing (see Figure 121)
NO
63
64
65
66
MIN
MAX
UNIT
tc(SCK)
tw(SCKH)
SCLK period
13
ns
Pulse duration, SCLK high
5
ns
tw(SCKL)
tt(SCK)
Pulse duration, SCLK low
5
ns
Transition time, SCLK (rise and fall)
2*
ns
* This parameter is not production tested.
63
66
64
66
SCLK0
SCLK1
65
Figure 121. Video Interface Timing: SCLK Timing
POST OFFICE BOX 1443
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145
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
video interface timing: FCLK input and video outputs (see Note 6 and Figure 122)
NO
67
68
69
70
MIN
MAX
UNIT
tc(FCK)
tw(FCKH)
FCLK period
25
ns
Pulse duration, FCLK high
8
ns
tw(FCKL)
tt(FCK)
Pulse duration, FCLK low
8
ns
Transition time, FCLK (rise and fall)
2*
ns
71
th(FCKL-SYL)
Hold time, HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK, or CAREA high after FCLK
low
72
th(FCKL-SYH)
Hold time, HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK, or CAREA low after FCLK
low
73
td(FCKL-SYL)
Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK,
or CAREA low
20
ns
74
td(FCKL-SYH)
Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK,
or CAREA high
20
ns
0
ns
0
ns
* This parameter is not production tested.
NOTE 6: Under certain circumstances, these outputs also can transition asynchronously. These transitions occur when controller timing register
values are modified by user programming. If the new register value forces the output to change states, then this transition occurs without
regard to FCLK inputs.
70
68
67
70
69
FCLK0
FCLK1
74
73
72
HSYNCn, VSYNCn,
CSYNCn/HBLNKn
CBLNKn/VBLNKn
CAREAn
71
Figure 122. Video Interface Timing: FCLK Input and Video Outputs
146
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
video interface timing: external sync inputs (see Figure 123)
When configured as inputs, the HSYNCn, VSYNCn, and CSYNCn signals may be driven asynchronously. The
following parameters apply only when the inputs are being generated synchronous to FCLKn in order to ensure
recognition on a particular FLCKn edge.
NO
75
76
77
78
MIN
MAX
UNIT
tsu(SIL-FCKH)
th(FCKH-SIL)
Setup time, HSYNC, VSYNC, or CSYNC low to FCLK no longer low†
Hold time, HSYNC, VSYNC, or CSYNC high after FCLK high‡
5
ns
7
ns
tsu(SIH-FCKH)
th(FCKH-SIH)
Setup time, HSYNC, VSYNC, or CSYNC high to FCLK no longer low§
Hold time, HSYNC, VSYNC, or CSYNC low after FCLK high¶
5
ns
7
ns
† This parameter must be met only to ensure the input is recognized as low at FLCK edge B.
‡ This parameter must be met only to ensure the input is recognized as high at FLCK edge A.
§ This parameter must be met only to ensure the input is recognized as high at FLCK edge D.
¶ This parameter must be met only to ensure the input is recognized as low at FLCK edge C.
A
B
C
D
FCLK0
FCLK1
76
77
78
HSYNC0, HSYNC1
VSYNC0, VSYNC1
CSYNC0, CSYNC1
(Inputs)
75
Figure 123. Video Interface Timing: External Sync Inputs
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147
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
emulator interface connection
The ’C80 supports emulation through a dedicated emulation port that is a superset of the IEEE Standard 1149.1
(JTAG) Standard. To support the ’C80 emulator, a target system must include a 14-pin header (2 rows of 7 pins)
with the connections shown in Figure 124. Table 38 describes the emulation signal.
TMS
1
2
TRST
TDI
3
4
GND
PD(+3.3V)
5
6
No pin (key)
TDO
7
8
GND
TCKRET
9
10
GND
TCK
11
12
GND
EMU0
13
14
EMU1
Pin Spacing: 0.100 in. (X,Y)
Pin Width: 0.025 in, square post
Pin Length: 0.235 in. nominal
(see Table 38)
Figure 124. Target System Header
Table 38. Target Connectors
XDS510
SIGNAL
XDS510
STATE
TARGET
STATE
TMS
O
I
TDI
O
I
Test-mode select†
Test-data input†
TDO
I
O
Test-data output†
TCK
O
I
TRST
O
I
Test clock – 10-MHz clock source from emulator. Can be used to drive system-test clock.†
Test reset†
EMU0
I
I/O
Emulation pin 0
EMU1
I
I/O
Emulation pin 1
PD (3.3 V)
I
O
Presence detect. Indicates that the target is connected and powered up. Should be tied to
+ 3.3 V on target system.
TCKRET
I
O
Test clock return. Test clock input to the XDS510 emulator. Can be buffered or unbuffered
version of TCK.†
DESCRIPTION
† IEEE Standard 1149.1
For best results, the emulation header should be located as close as possible to the ’C80. If the distance exceeds
six inches, the emulation signals should be buffered. See Figure 125.
XDS510 is a trademark of Texas Instruments Incorporated.
148
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
emulator-interface connection (continued)
3.3 V
EMU0
EMU1
TRST
TMS
TDI
TDO
3.3 V
T34
13
J35
14
L33
2
N33
1
H34
3
P32
7
E35
11
TCK
’C80
9
6 in. or less
EMU0
3.3 V
5
PD
EMU1
EMU0
EMU1
4
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
TRST
6
TMS
8
TDI
10
TDO
12
3.3 V
T34
13
J35
14
L33
2
N33
1
H34
3
P32
7
E35
11
TCK
TCKRET
Emulator
Header
9
’C80
More than 6 in.
3.3 V
5
EMU0
PD
EMU1
4
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
6
8
10
12
TCKRET
Emulator
Header
Figure 125. Emulation Header Connections – Emulator-Driven Test Clock
The target system also can generate the test clock. This allows the user to:
D Set the test clock frequency to match the system requirements. (The emulator provides only a 10-MHz
test clock.)
D Have other devices in the system that require a test clock when the emulator is not connected
3.3 V
EMU0
EMU1
TRST
TMS
TDI
TDO
TCK
3.3 V
T34
13
J35
14
L33
2
N33
1
H34
3
P32
7
E35
11
9
’C80
System
Test
Clock
EMU0
PD
EMU1
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
3.3 V
5
4
6
8
10
12
TCKRET
Emulator
Header
More than 6 in.
Figure 126. Emulation Header Connections – System-Driven Test Clock
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149
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
emulator-interface connection (continued)
For multiprocessor applications, the following conditions are recommended:
D To reduce timing skew, buffer TMS, TDI, TDO, and TCK through the same physical package.
D If buffering is used, 4.7-kΩ resistors are recommended for TMS, TDI, and TCK, which should be pulled
high (3.3 V).
D Buffering EMU0 and EMU1 is recommended highly to provide isolation. The buffers need not be in the
same physical package as TMS, TCK, TDI, or TDO. Pullups to 3.3 V are required and should provide
a signal rise time of less than 10 µs. A 4.7-kΩ resistor is suggested for most applications.
D To ensure high-quality signals, special printed wire board (PWB) routing and use of termination resistors
may be required. The emulator provides fixed series termination (33 Ω) on TMS and TDI, and optional
parallel terminators (180-Ω pullup and 270-Ω pulldown) on TCKRET and TDO.
3.3 V
EMU0
EMU1
TRST
TMS
TDI
TDO
TCK
3.3 V
T34
13
J35
14
L33
2
N33
1
H34
3
P32
7
E35
11
9
EMU0
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
EMU1
TRST
TMS
TDI
TDO
TCK
4
6
8
10
12
TCKRET
’C80
EMU0
PD
EMU1
3.3 V
5
Emulator
Header
T34
J35
L33
N33
H34
P32
E35
’C80
Figure 127. Emulation Header Connections – Multiprocessor Applications
150
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
MECHANICAL DATA
GF (S-CPGA-P305)
CERAMIC PIN GRID ARRAY PACKAGE
1.717 (43,61)
TYP
1.683 (42,75)
1.879 (47,73)
SQ
1.841 (46,76)
0.100 (2,54)
AR
AN
AL
AJ
AG
AE
AC
AA
W
U
R
N
L
J
G
E
C
A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
Heatsink
0.050 (1,27)
0.060 (1,52)
0.040 (1,02)
0.019 (0,48)
0.014 (0,36)
0.026 (0,660)
0.006 (0,152)
0.045 (1,14) DIA 4 Places
0.040 (1,02)
0.190 (4,83)
0.170 (4,32)
0.150 (3,81)
0.180 (4,57)
0.110 (2,79)
0.140 (3,56)
4040035-3/E 03/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Package thickness of 0.150 (3,81) / 0.110 (2,79) includes package body and lid, but does not include integral heatsink or attached
features.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
151
SGUS025A – AUGUST 1998 – REVISED JUNE 2002
MECHANICAL DATA
HFH (R-CQFP-F320)
CERAMIC QUAD FLATPACK WITH NCTB
76,40
74,85
75,40
74,60
57,00
55,60
44,44
43,56
1,55
Dia
1,45
(4 Places)
5,50
4,50
39,50
BSC
320
1
241
240
DETAIL “C”
Heatsink
70,00
3,60
3,50
161
160
80
81
DETAIL “B”
2,60
2,50
2,60
Dia (2 Places)
2,50
DETAIL ”A”
0,50 MAX
320 0,25
0,18
0,51
4,55 MAX
4,00 MAX
0,20
0,10
0,35
0,05
0,50
DETAIL “A”
NOTES: A.
B.
C.
D.
E.
152
DETAIL “B”
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals will be gold plated.
Falls within JEDEC MO-134 AD
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1,05
0,75
DETAIL “C”
4040232-6/E 09/96
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
5962-9679101QXA
ACTIVE
CPGA
GF
305
1
TBD
Call TI
N / A for Pkg Type
5962-9679101QYC
ACTIVE
CFP
HFH
320
1
TBD
Call TI
N / A for Pkg Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SM320C80GFA50
NRND
CPGA
GF
305
1
TBD
Call TI
N / A for Pkg Type
SM320C80GFM50
ACTIVE
CPGA
GF
305
1
TBD
Call TI
N / A for Pkg Type
SM320C80HFHM50
ACTIVE
CFP
HFH
320
1
TBD
Call TI
N / A for Pkg Type
SMJ320C80GFM50
ACTIVE
CPGA
GF
305
1
TBD
Call TI
N / A for Pkg Type
SMJ320C80HFHM50
ACTIVE
CFP
HFH
320
1
TBD
Call TI
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP028B – JANUARY 1995 – REVISED JUNE 1999
HFH (R-CQFP-F320)
CERAMIC QUAD FLATPACK WITH NCTB
76,40
74,85
75,40
74,60
57,00
55,60
44,44
SQ
43,56
1,55
Dia
1,45
4 Places
5,50
Tie Bar Width
4,50
39,50
BSC
320
1
241
240
DETAIL ”C”
70,00 BSC
3,60
3,50
161
160
80
81
DETAIL ”B”
2,60
2,50
DETAIL ”A”
320 X
2,60
Dia 2 Places
2,50
0,50 MAX
0,25
0,18
3,21 MAX
2,66 MAX
0,20
0,10
0,35
0,05
0,50
DETAIL ”A”
NOTES: A.
B.
C.
D.
E.
F.
DETAIL ”B”
1,05
0,75
DETAIL ”C”
4040232-4/F 12/98
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
This package is hermetically sealed with a metal lid.
The terminals are gold-plated.
Leads not shown for clarity purposes
Falls within JEDEC MO-134AD
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MCPG021B – FEBRUARY 1996 – REVISED DECEMBER 2001
GF (S-CPGA-P305)
CERAMIC PIN GRID ARRAY
1.717 (43,61)
TYP
1.683 (42,75)
1.879 (47,73)
SQ
1.841 (46,76)
0.100 (2,54)
AR
AN
AL
AJ
AG
AE
AC
AA
W
U
R
A1 Corner
N
L
J
G
E
C
A
1 3
5
7
9 11 13 15 17 19 21 23 25 27 29 31 33 35
Bottom View
Heatslug
0.050 (1,27)
0.060 (1,52)
0.040 (1,02)
0.026 (0,660)
0.006 (0,152)
0.045 (1,14) DIA 4 Places
0.019 (0,48)
0.014 (0,36)
0.040 (1,02)
0.190 (4,83)
0.170 (4,32)
0.150 (3,81)
0.180 (4,57)
0.110 (2,79)
0.140 (3,56)
4040035-3/F 11/01
NOTES: A.
B.
C.
D.
E.
F.
G.
H.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Index mark can appear on top or bottom, depending on package vendor.
Pins are located within 0.010 (0,25) diameter of true position relative to
each other at maximum material condition and within 0.030 (0,76) diameter
relative to the edge of the ceramic.
This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
The pins can be gold-plated or solder-dipped.
Package thickness of 0.150 (3,81) / 0.110 (2,79) includes package body and lid,
but does not include integral heatslug or attached features.
Falls within JEDEC MO-128AK
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MCQF008B – FEBRUARY 1996 – REVISED JUNE 1999
HFH (R-CQFP-F320)
CERAMIC QUAD FLATPACK WITH NCTB
76,40
74,85
75,40
74,60
57,00
55,60
44,44
43,56
1,55
Dia
1,45
4 Places
5,50
4,50 Tie Bar Width
39,50
BSC
320
1
241
240
DETAIL ”C”
Heat Sink
70,00 BSC
3,60
3,50
161
160
80
81
2,60
2,50
2,60
Dia 2 Places
2,50
DETAIL ”A”
320 X
DETAIL ”B”
0,50 MAX
0,64
0,38
0,25
0,18
3,85 MAX
2,66 MAX
0,20
0,10
0,35
0,05
0,50
DETAIL ”A”
NOTES: A.
B.
C.
D.
E.
F.
DETAIL ”B”
1,05
0,75
DETAIL ”C”
4040232-6/F 12/98
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
This package is hermetically sealed with a metal lid.
The terminals are gold-plated.
Leads not shown for clarity purposes
Falls within JEDEC MO-134AD
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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