application INFO available UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B Regulating Pulse Width Modulators FEATURES DESCRIPTION • 8 to 35V Operation The UC1525B/1527B series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1V buried zener reference is trimmed to ±0.75% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200mA. The UC1525B output stage features NOR logic, giving a LOW output for an OFF state. The UC1527B utilizes OR logic which results in a HIGH output level when OFF. • 5.1V Buried Zener Reference Trimmed to ±0.75% • 100Hz to 500kHz Oscillator Range • Separate Oscillator Sync Terminal • Adjustable Deadtime Control • Internal Soft-Start • Pulse-by-Pulse Shutdown • Input Undervoltage Lockout with Hysteresis • Latching PWM to Prevent Multiple Pulses • Dual Source/Sink Output Drivers • Low Cross Conduction Output Stage • Tighter Reference Specifications BLOCK DIAGRAM UDG-95055 SLUS376 JULY 1995 UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (Note 1) Supply Voltage, (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage (VC). . . . . . . . . . . . . . . . . . . . . . +40V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +5.5V Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VIN Output Current, Source or Sink . . . . . . . . . . . . . . . . . . . 500mA Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA Power Dissipation at TA = +25°C. . . . . . . . . . . . . . . . . 1000mW Power Dissipation at TC = +25°C . . . . . . . . . . . . . . . . 2000mW Operating Junction Temperature . . . . . . . . . . –55°C to +150°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V Collector Supply Voltage (VC) . . . . . . . . . . . . . . +4.5V to +35V Sink/Source Load Current (steady state) . . . . . . . . 0 to 100mA Sink/Source Load Current (peak) . . . . . . . . . . . . . . 0 to 400mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA Oscillator Frequency Range. . . . . . . . . . . . . . 100Hz to 400kHz Oscillator Timing Resistor . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ Oscillator Timing Capacitor . . . . . . . . . . . . . . 0.001µF to 0.1µF Dead Time Resistor Range . . . . . . . . . . . . . . . . . . . 0Ω to 500Ω Note 1: Range over which the device is functional and parameter limits are guaranteed. All currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. CONNECTION DIAGRAMS DIL-16, SOIC-16 (Top View) J or N, DW Packages LCC-20, PLCC-20 (Top View) L, Q Packages ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the UC1525B and UC1527B; –40°C to +85°C for the UC2525B and UC2527B; 0°C to +70°C for the UC3525B and UC3527B; +VIN = 20V, TA = TJ. UC1525B/UC2525B UC1527B/UC2527B PARAMETER TEST CONDITIONS UC3525B UC3527B MIN TYP MAX MIN TYP MAX UNITS 5.062 5.10 5.138 5.036 5.10 5.164 V Reference Section Output Voltage TJ = 25°C Line Regulation VIN = 8V to 35V 5 10 5 10 mV Load Regulation IL = 0mA to 20mA 7 15 7 15 mV 50 mV Temperature Stability (Note 2) Over Operating Range Total Output Variation Line, Load, and Temperature Short Circuit Current VREF = 0, TJ =25°C 80 100 Output Noise Voltage (Note 2) 10Hz ≤ f ≤10kHz, TJ = 25°C 40 Long Term Stability (Note 2) TJ = 125°C, 1000 Hrs. 3 2 10 5.036 50 5.164 10 5.024 5.176 V 80 100 mA 200 40 200 µVrms 10 3 10 mV UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the UC1525B and UC1527B; –40°C to +85°C for the UC2525B and UC2527B; 0°C to +70°C for the UC3525B and UC3527B; +VIN = 20V, TA = TJ. UC1525B/UC2525B UC1527B/UC2527B PARAMETER TEST CONDITIONS MIN TYP MAX ±2 UC3525B UC3527B MIN TYP MAX UNITS ±6 ±2 ±6 % ±0.3 ±1 ±1 ±2 % ±3 ±6 ±3 ±6 % 120 Hz Oscillator Section (Note 3) Initial Accuracy (Notes 2 & 3) TJ = 25°C Voltage Stability (Notes 2 & 3) VIN = 8V to 35V Temperature Stability (Note 2) Over Operating Range Minimum Frequency RT = 200kW, CT = 0.1mF 120 Maximum Frequency RT = 2kW, CT = 470pF 400 Current Mirror IRT = 2mA 1.7 3.0 3.5 TJ = 25°C 0.3 1.2 Clock Amplitude (Notes 2 & 3) Clock Width (Notes 2 & 3) Sync Threshold Sync Input Current Sync Voltage = 3.5V 400 2.0 kHz 2.2 1.7 2.0 2.2 mA 3.0 3.5 0.5 1.0 0.3 0.5 1.0 ms 2.0 2.8 1.2 2.0 2.8 V 1.0 2.5 1.0 2.5 mA 0.5 5 2 10 mV 1 10 1 10 mA 1 mA V Error Amplifier Section (VCM = 5.1V) Input Offset Voltage Input Bias Current Input Offset Current 1 DC Open Loop Gain RL ³ 10 MegW 60 75 60 75 dB Gain-Bandwidth Product (Note 2) AV = 0dB, TJ = 25°C 1 2 1 2 MHz Output Low Level 0.2 Output High Level 0.5 0.2 0.5 V 3.8 5.6 3.8 5.6 V Common Mode Rejection VCM = 1.5V to 5.2V 60 75 60 75 dB Supply Voltage Rejection VIN = 8V to 35V 50 60 50 60 dB 45 49 45 49 0.7 0.9 0.7 0.9 PWM Comparator Minimum Duty Cycle 0 Maximum Duty Cycle (Note 3) Input Threshold (Note 3) Zero Duty Cycle Input Threshold (Note 3) Maximum Duty Cycle Input Bias Current (Note 2) 0 % % V 3.3 3.6 3.3 3.6 V 0.05 1.0 0.05 1.0 mA 50 80 50 80 mA 0.4 0.7 0.4 0.7 V 0.8 1.0 0.8 1.0 V Shutdown Section Soft Start Current VSHUTDOWN = 0V, VSOFTSTART = 0V Soft Start Low Level VSHUTDOWN = 2.5V Shutdown Threshold To outputs, VSOFTSTART = 5.1V, TJ =25°C Shutdown Input Current VSHUTDOWN = 2.5V 0.4 1.0 0.4 1.0 mA Shutdown Delay (Note 2) VSHUTDOWN = 2.5V, TJ = 25°C 0.2 0.5 0.2 0.5 ms 0.2 0.4 0.2 0.4 V 1.0 2.0 1.0 2.0 25 0.6 25 0.6 Output Drivers (Each Output) (Vc = 20V) Output Low Level ISINK = 20mA ISINK = 100mA V ISOURCE = 20mA 18 19 18 19 V ISOURCE = 100mA 17 18 17 18 V Undervoltage Lockout VCOMP and VSOFTSTART = High 6 7 6 7 Collector Leakage VC = 35V Output HIgh Level 8 200 3 8 V 200 mA UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for the UC1525B and UC1527B; –40°C to +85°C for the UC2525B and UC2527B; 0°C to +70°C for the UC3525B and UC3527B; +VIN = 20V, TA = TJ. UC1525B/UC2525B UC1527B/UC2527B PARAMETER TEST CONDITIONS MIN TYP MAX UC3525B UC3527B MIN TYP MAX UNITS Output Drivers (Each Output) (VC = 20V) (cont.) Rise Time (Note 2) CL = 1nF, TJ = 25°C 100 600 100 600 ns Fall Time (Note 2) CL = 1nF, TJ = 25°C 50 300 50 300 ns Cross conduction charge Per cycle, TJ = 25°C 30 VIN = 35V 14 30 nc Total Standby Current Supply Current 20 14 20 mA Note 2: Ensured by design. Not 100% tested in production. Note 3: Tested at fosc= 40kHz (RT = 3.6KW, CT = 0.01mF, RD = 0W). Approximate oscillator frequency is defined by: f = 1 C T • (0.7 • RT + 3RD ) PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS UC1525B Output Saturation Characteristics UC1525B Output Circuit (1/2 Circuit Shown) UDG-95056 UDG-95057 UDG-95058 In conventional push-pull bipolar designs, forward base drive is controlled by R1-R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C, and C2. UDG-95059 For single-ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. 4 UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B UDG-95060 UDG-95061 The low source impedance of the output drivers provides rapid charging of power FET input capacitance while minimizing external components. Low power transformers can be driven directly by the UC1525B. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground. PRINCIPLES OF OPERATION AND TYPICAL CHARACTERISTICS Shutdown Options (See Block Diagram) plying a positive signal on Pin 10 performs two functions: the PWM latch is immediately set providing the fastest turn-off signal to the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release. Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100µA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by ap- UC1525B Oscillator Schematic UDG-95062 5 UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B Oscillator Charge Time vs. TRand CT Oscillator Discharge Time vs.DRand CT UDG-95064 UDG-95063 UC1525B Error Amplifier Error Amplifier Open-Loop Frequency Response UDG-95065 UDG-95066 6 UC1525B UC1527B UC2525B UC2527B UC3525B UC3527B LAB TEST FIXTURE UDG-95067 7 PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8951105EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type UC1525BJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type 1 TBD A42 N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) UC1525BJ883B ACTIVE CDIP J 16 UC2525BDWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC2525BDWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3525BDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3525BDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3525BDWTR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3525BDWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UC3525BN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3525BNG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3527BN ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type UC3527BNG4 ACTIVE PDIP N 16 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF UC1525B, UC3525B : • Space: UC1525B-SP NOTE: Qualified Version Definitions: • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UC2525BDWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1 UC3525BDWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC2525BDWTR SOIC DW 16 2000 346.0 346.0 33.0 UC3525BDWTR SOIC DW 16 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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