TI SN74LV165D

SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
D
D
D
D
D
EPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2 V at VCC, TA = 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
SN54LV165 . . . J OR W PACKAGE
SN74LV165 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
SH/LD
CLK
E
F
G
H
QH
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
CLK INH
D
C
B
A
SER
QH
SN54LV165 . . . FK PACKAGE
(TOP VIEW)
CLK
SH/LD
NC
VCC
CLK INH
D
description
The ’LV165 parallel-load, 8-bit shift registers are
designed for 2.7-V to 5.5-V VCC operation.
E
F
NC
G
H
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
D
C
NC
B
A
QH
GND
NC
QH
SER
When the device is clocked, data is shifted toward
the serial output QH. Parallel-in access to each
stage is provided by eight individual direct data
inputs that are enabled by a low level at the SH/ LD
input. The ’LV165 feature a clock inhibit function
and a complemented serial output QH.
4
Clocking is accomplished by a low-to-high
NC – No internal connection
transition of the clock (CLK) input while SH/ LD is
held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are
interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK
INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/ LD is held
high. The parallel inputs to the register are enabled while SH/ LD is held low independently of the levels of CLK,
CLK INH, or SER.
The SN54LV165 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV165 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
SH/ LD
CLK
CLK INH
L
X
X
Parallel load
H
H
X
H
X
H
Q0
Q0
H
L
↑
Shift
H
↑
L
Shift
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
logic diagram (positive logic)
A
SH/LD
CLK INH
CLK
SER
B
11
1
C
12
D
13
E
14
F
3
G
4
H
5
6
15
2
S
C1
1D
R
10
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
Pin numbers shown are for D, DB, J, PW, and W packages.
typical shift, load, and inhibit sequences
CLK
CLK INH
SER
L
SH/LD
Data
Inputs
A
H
B
L
C
H
D
L
E
H
F
L
G
H
H
H
QH
H
H
L
H
L
H
L
H
QH
L
L
H
L
H
L
H
L
Inhibit
Serial Shift
Load
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
S
C1
1D
R
9
7
QH
QH
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . . 1.30 W
DB package . . . . . . . . . . . . . . . . . . . 0.55 W
PW package . . . . . . . . . . . . . . . . . . . 0.5 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
"
"
"
"
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 4)
SN54LV165
VCC
Supply voltage
VIH
High level input voltage
High-level
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VIL
Low level input voltage
Low-level
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI
VO
Input voltage
MAX
MIN
MAX
2.7
5.5
2.7
5.5
2
2
3.15
3.15
0
Output voltage
0
IOH
High level output current
High-level
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
IOL
Low level output current
Low-level
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
∆t /∆v
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
SN74LV165
MIN
0.8
1.65
1.65
0
0
V
V
0.8
VCC
VCC
UNIT
VCC
VCC
–6
–6
–12
–12
6
6
12
12
V
V
V
mA
mA
0
100
0
100
ns / V
–55
125
–40
85
°C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
VCC†
TEST CONDITIONS
IOH = – 100 µA
IOH = – 6 mA
MIN to MAX
IOH = – 12 mA
IOL = 100 µA
4.5 V
3V
SN54LV165
MIN
TYP
II
VI = VCC or GND
ICC
VI = VCC or GND,
GND
nICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
MIN
TYP
VCC – 0.2
2.4
VCC – 0.2
2.4
3.6
3.6
MIN to MAX
IOL = 6 mA
IOL = 12 mA
SN74LV165
MAX
MAX
V
0.2
0.2
3V
0.4
0.4
4.5 V
0.55
0.55
3.6 V
±1
±1
5.5 V
±1
±1
3.6 V
20
20
5.5 V
20
20
3 V to 3.6 V
500
500
IO = 0
UNIT
3.3 V
2.5
2.5
5V
3
3
V
µA
µA
µA
pF
F
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV165
VCC = 5.5 V
± 0.5 V
fclock
tw
tsu
th
Clock frequency
Pulse duration
Hold time
MAX
0
50
MAX
0
40
MIN
MAX
0
30
14
18
22
SH/LD low
14
18
22
SH/LD high before CLK↑
10
13
17
8
11
14
10
12
15
Data before SH/LD↑
8
12
17
SER data after CLK↑
6
6
5
Parallel data after SH/LD↑
6
6
5
CLK INH before CLK↑
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
MIN
VCC = 2.7 V
CLK high or low
SER before CLK↑
Setup time
MIN
VCC = 3.3 V
± 0.3 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN74LV165
VCC = 5.5 V
± 0.5 V
fclock
tw
tsu
th
Clock frequency
Pulse duration
0
50
MIN
MAX
0
40
MIN
MAX
0
30
14
18
22
SH/LD low
14
18
22
SH/LD high before CLK↑
10
13
17
8
11
14
10
12
15
Data before SH/LD↑
8
12
17
SER data after CLK↑
6
6
5
Parallel data after SH/LD↑
6
6
5
CLK INH before CLK↑
Hold time
MAX
VCC = 2.7 V
CLK high or low
SER before CLK↑
Setup time
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LV165
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
VCC = 5.5 V ± 0.5 V
MIN
TYP
MAX
50
CLK
tpd
SH/LD
QH or QH
H
90
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
40
75
VCC = 2.7 V
MIN
MAX
30
UNIT
MHz
20
24
20
38
47
19
24
19
36
44
15
20
15
29
36
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN74LV165
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
VCC = 5.5 V ± 0.5 V
MIN
TYP
MAX
50
CLK
tpd
SH/LD
QH or QH
H
90
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
40
75
VCC = 2.7 V
MIN
MAX
30
UNIT
MHz
20
24
20
38
47
19
24
19
36
44
15
20
15
29
36
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissi
dissipation
ation ca
capacitance
acitance
CL = 50 pF
F,
VCC
3.3 V
TYP
5V
57
UNIT
33
f = 10 MHz
pF
F
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
S1
1 kΩ
From Output
Under Test
Vz
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
Vz
GND
1 kΩ
WAVEFORM
CONDITION
Vm
Vi
Vz
LOAD CIRCUIT
VCC = 4.5 V
to 5.5 V
0.5 × VCC
VCC
2 × VCC
VCC = 2.7 V
to 3.6 V
1.5 V
2.7 V
6V
Vi
Vm
Timing Input
0V
tw
tsu
Vi
Input
Vm
th
Vi
Vm
Vm
Data Input
Vm
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Vi
Vm
Input
0V
VOH
Vm
Output
Vm
VOL
Output
VOH
Vm
0V
Vm
VOL
tPLZ
Output
Waveform 1
S1 at Vz
(see Note B)
tPLH
tPHL
Vm
Vm
tPZL
tPHL
tPLH
Vi
Output
Control
Vm
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Vm
tPZH
0.5 × Vz
VOL + 0.3 V
VOL
tPHZ
Vm
VOH – 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN74LV165D
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
SN74LV165DBLE
OBSOLETE
SSOP
DB
16
TBD
Call TI
Call TI
SN74LV165DR
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
SN74LV165PWLE
OBSOLETE
TSSOP
PW
16
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
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to Customer on an annual basis.
Addendum-Page 1
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