PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8432-11 is a general purpose, dual output Crystal-to-3.3V Differential LVPECL High Frequency HiPerClockS™ Synthesizer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8432-11 has a selectable TEST_CLK or crystal inputs. The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The VCO operates at a frequency range of 200MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. Output frequencies up to 700MHz for FOUT and 350MHz for FOUT/2 can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics and the multiple frequency outputs of the ICS8432-11 makes it an ideal clock source for Fiber Channel 1 and 2, and Infiniband applications. • Dual differential 3.3V LVPECL outputs ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • TEST_CLK can accept the following input levels: LVCMOS or LVTTL • Maximum FOUT frequency: 700MHz • Maximum FOUT/2 frequency: 350MHz • VCO range: 200MHz to 700MHz • Parallel interface for programming counter and VCO frequency multiplier and dividers • Cycle-to-cycle jitter: 25ps (maximum) • RMS period jitter: TBD • 3.3V supply voltage • 0°C to 70°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT XTAL_OUT nP_LOAD M0 M1 M2 M3 M4 TEST_CLK VCO_SEL VCO_SEL XTAL_SEL 32 31 30 29 28 27 26 25 XTAL_IN XTAL_OUT MR FOUT nFOUT M5 1 24 XTAL_IN M6 2 23 TEST_CLK M7 3 22 XTAL_SEL M8 4 21 VCCA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK VEE 8 17 MR 9 10 11 12 13 14 15 16 VEE nFOUT FOUT VCCO nFOUT/2 FOUT/2 VCC TEST FOUT/2 nFOUT/2 S_LOAD S_DATA S_CLOCK nP_LOAD ICS8432-11 TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View M0:M8 N0:N1 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8432CY-11 www.icst.com/products/hiperclocks.html 1 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the input frequency and the M divider is defined as follows: The ICS8432-11 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the ICS8432-11. This input is fed into the phase detector. A 25MHz clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector. fVCO = fxtal x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 8 ≤ M ≤ 28. The frequency out is defined as follows: fOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGHto-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note, that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8432-11 support two input modes to program the PLL M divider and N output divider. The two input operational modes are parallel and serial. Figure1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout/2 SERIAL LOADING S_CLOCK S_DATA T1 T0 * NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 S_LOAD nP_LOAD PARALLEL LOADING M, N M0:M8, N0:N1 nP_LOAD S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: 8432CY-11 The NULL timing slot must be observed. www.icst.com/products/hiperclocks.html 2 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 M5 Input 2, 3, 4, 28, 29, 30, 31, 32 M6, M7, M8, M0, M1, M2, M3, M4 Input M divider inputs. Data latched on LOW-to-HIGH transistion of Pulldown nP_LOAD input. LVCMOS / LVTTL interface levels. 5, 6 N0, N1 Input Pulldown Pullup 7 nc Unused 8, 1 6 VEE Power 9 TEST Output 10 VCC Power 11, 12 FOUT/2, nFOUT/2 Output 13 VCCO Power 14, 15 FOUT, nFOUT Output 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VCCA Power 22 XTAL_SEL Input Pullup 23 24, 25 TEST_CLK XTAL_IN, XTAL_OUT Input Pulldown 26 nP_LOAD Input Pulldown 27 VCO_SEL Input Pullup Input Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. No connect. Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS interface levels. Core supply pin. Half frequency differential output for the synthesizer. 3.3V LVPECL interface levels. Output supply pin. Differential output for the synthesizer. 3.3V LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are rset causing the true outputs (FOUTx) to go low and the inver ted outputs (nFOUTx) to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between crystal or test inputs as the PLL reference source. LVCMOS / LVTTL interface levels. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. Test clock input. LVCMOS / LVTTL interface levels. Crystal oscillator inputs. XTAL_IN is the input. XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 8432CY-11 www.icst.com/products/hiperclocks.html 3 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. TABLE 3A. PARALLEL AND ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER SERIAL MODES FUNCTION TABLE Inputs MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X L L Data Data X X X L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data L H X X L X X L H X X H ↑ Data Conditions Reset. M and N counters reset. Data on M and N inputs passed directly to the M divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE VCO Frequency (MHz) M Divide 200 8 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 0 0 0 0 0 1 0 0 0 225 9 0 0 0 0 0 1 0 0 1 250 10 0 0 0 0 0 1 0 1 0 275 11 0 0 0 0 0 1 0 1 1 • • • • • • • • • • • • • • • • • • • • • • 650 26 0 0 0 0 1 1 0 1 0 675 27 0 0 0 0 1 1 0 1 1 700 28 0 0 0 0 1 1 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency of 25MHz. 0 TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Output Frequency (MHz) Inputs N Divider Value FOUT FOUT/2 Minimum Maximum N1 N0 Minimum Maximum 0 0 1 200 70 0 125 350 0 1 2 100 350 62.5 175 1 0 4 50 175 31.25 87.5 1 1 8 25 87.5 15.625 43.75 8432CY-11 www.icst.com/products/hiperclocks.html 4 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC VCCA Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VCCO Output Supply Voltage 3.465 V IEE Power Supply Current 110 mA ICCA Analog Supply Current 15 mA Maximum Units 2 VCC + 0.3 V -0.3 0.8 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, Input S_DATA, S_LOAD, nP_LOAD High Current M5, XTAL_SEL, VCO_SEL IIH IIL Input Low Current Test Conditions Minimum Typical M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD VCC = 3.465V, VIN = 0V -5 µA M5, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA 2. 6 V VOH Output High Voltage TEST; NOTE 1 VOL Output Low Voltage TEST; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VCCO/2. See “Parameter Measurement Information” section, “3.3V Output Load Test Circuit” figure. 8432CY-11 www.icst.com/products/hiperclocks.html 5 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1. 0 V Maximum Units NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical TEST_CLK; NOTE 1 12 25 MHz XTAL_IN, XTAL_OUT; Input Frequency 12 25 MHz fIN NOTE 1 S_CLOCK TBD MHz NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 200MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 17 ≤ M ≤ 58. Using the maximum frequency of 25MHz, valid values of M are 8 ≤ M ≤ 28. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Typical Mode of Oscillation Maximum Units Fundamental Frequency 12 25 MHz Equivalent Series Resistance (ESR) 70 Ω Shunt Capacitance 7 pF Drive Level 1 mW TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency Test Conditions tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 3 Minimum Typical 25 Maximum Units 700 MHz 25 ps tjit(per) Period Jitter, RMS; NOTE 1, 3 TBD ps tsk(o) Output Skew; NOTE 2, 3 TBD ps tR Output Rise Time 20% to 80% @ 50MHz 30 0 700 ps tF Output Fall Time 20% to 80% @ 50MHz 30 0 700 ps M, N to nP_LOAD tS tH odc Setup Time Hold Time 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns Output Duty Cycle 47 PLL Lock Time tLOCK All parameters measured at 500MHz unless noted otherwise. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 8432CY-11 www.icst.com/products/hiperclocks.html 6 53 % 10 ms REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V VOH V CC , VCCA, VCCO Qx SCOPE VREF LVPECL nQx VEE VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram Reference Point Mean Period (Trigger Edge) -1.3V ± 0.165V (First edge after trigger) 3.3V OUTPUT LOAD AC TEST CIRCUIT PERIOD JITTER nFOUT nFOUT, nFOUT/2 FOUT, FOUT/2 ➤ nFOUT/2 tcycle n ➤ FOUT ➤ tcycle n+1 ➤ FOUT/2 t jit(cc) = tcycle n –tcycle n+1 tsk(o) 1000 Cycles OUTPUT SKEW CYCLE-TO-CYCLE JITTER nFOUT, nFOUT/2 80% FOUT, FOUT/2 80% VSW I N G t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD 8432CY-11 OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 7 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATIONS STORAGE AREA NETWORKS application frequencies as well as the ICS8432-11 configurations used to generate the appropriate frequency. A variety of technologies are used for interconnection of the elements within a SAN. The tables below list the common Table 8. COMMON SANS APPLICATIONS FREQUENCIES Interconnect Technology Clock Rate Reference Frequency to SERDES (MHz) Crystal Frequency (MHz) Gigabit Ethernet Fibre Channel 1.25 GHz 125, 250, 156.25 25, 19.53125 FC1 1.0625 GHz FC2 2.1250 GHz 106.25, 53.125, 132.8125 16.6015625, 25 2.5 GHz 125, 250 25 Infiniband Table 9. CONFIGURATION DETAILS Interconnect Technology FOR SANS APPLICATIONS Crystal Frequency (MHz) ICS8432-11 Output Frequency to SERDES (MHz) 25 125 0 0 0 0 1 0 1 0 25 250 0 0 0 0 1 0 1 25 156.25 0 0 0 0 1 1 19.53125 156.25 0 0 0 1 0 25 53.125 0 0 0 0 25 106.25 0 0 0 16.6015625 132.8125 0 0 25 125 0 25 250 0 ICS8432-11 M & N Settings M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 Gigabit Ethernet Fiber Channel 1 Fiber Channel 2 Infiniband 8432CY-11 www.icst.com/products/hiperclocks.html 8 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8432-11 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. TERMINATION FOR 3.3V VCC .01μF 10Ω V CCA .01μF 10μF FIGURE 2. POWER SUPPLY FILTERING LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 8432CY-11 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 9 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE The schematic of the ICS8432-11 layout example used in this layout guideline is shown in Figure 4A. The ICS8432-11 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The lay- out in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board. C1 C2 M5 M6 M7 M8 N0 N1 nc VEE VCC ICS8432-11 X_IN T_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR TEST VCC FOUT/2 nFOUT/2 VCCO FOUT nFOUT VEE 1 2 3 4 5 6 7 8 9 10 11 12 VCC 13 FOUT 14 FOUTN 15 16 U1 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD X_OUT 32 31 30 29 28 27 26 25 X1 VCC 24 23 22 21 20 19 18 17 R7 10 REF_IN XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK C11 0.01u C16 10u VCC R1 125 R3 125 Zo = 50 Ohm IN+ C14 0.1u TL1 C15 0.1u + Zo = 50 Ohm IN- TL2 VCC=3.3V R2 84 FIGURE 4A. SCHEMATIC 8432CY-11 OF RECOMMENDED LAYOUT www.icst.com/products/hiperclocks.html 10 R4 84 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: • The differential 50Ω output traces should have same length. All the resistors and capacitors are size 0603. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a spearation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. • Make sure no other signal traces are routed between the clock trace pair. CLOCK TRACES • The matching termination resistors should be located as close to the receiver input pins as possible. AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL_IN) and 25 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. X1 GND VCC VIA U1 PIN 1 C11 C16 VCCA R7 Close to the input pins of the receiver R4 R3 TL1N TL1N C15 C14 TL1 TL1 R2 TL1, TL2 are 50 Ohm traces and equal length FIGURE 4B. PCB BOARD LAYOUT 8432CY-11 FOR ICS8432-11 www.icst.com/products/hiperclocks.html 11 R1 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8432-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8432-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.2mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 381.2mW + 60.4mW = 441.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 10 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.441W * 42.1°C/W = 88.6°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 10. THERMAL RESISTANCE ΘJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8432CY-11 www.icst.com/products/hiperclocks.html 12 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX =V CCO_MAX – 1.0V (VCCO_MAX - VOH_MAX) = 1.0V • For logic low, VOUT = V =V OL_MAX (V CCO_MAX -V OL_MAX CCO_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX ))/R ] * (V -V OH_MAX CCO_MAX L -V )= OH_MAX [(2V - 1V)/50Ω) * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 8432CY-11 www.icst.com/products/hiperclocks.html 13 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 11. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8432-11 is: 3765 8432CY-11 www.icst.com/products/hiperclocks.html 14 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER FOR 32 LEAD LQFP TABLE 12. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC 0.60 0.75 L 0.45 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8432CY-11 www.icst.com/products/hiperclocks.html 15 REV. E MAY 20, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8432-11 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 13. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8432CY-11 ICS8432CY-11 32 Lead LQFP tray 0°C to 70°C ICS8430CY-11T ICS8432CY-11 32 Lead LQFP 1000 tape & reel 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8432CY-11 www.icst.com/products/hiperclocks.html 16 REV. E MAY 20, 2005