ICS ICS952001

ICS952001
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for P4™ processor
Features/Benefits:
•
Programmable output frequency, divider ratios, output
rise/falltime, output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write
operations.
•
For PC133 SDRAM system use the ICS9179-06 as the
memory buffer.
•
For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
•
Uses external 14.318MHz crystal.
Key Specifications:
•
PCI - PCI output skew: < 500ps
•
CPU - SDRAM output skew: < 1ns
•
AGP - AGP output skew: <150ps
Pin Configuration
VDDREF
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
*PCI_STOP#
VDDPCI
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Block Diagram
PLL2
48MHz
24_48MHz
/2
X1
X2
CPU
SDRA M
Z CLK
AGP
(M H z )
6 6 .6 7
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
1 0 0 .0 0
8 0 .0 0
8 0 .0 0
9 5 .0 0
9 5 .0 0
6 6 .6 7
(M H z )
6 6 .6 7
100.00
200.00
133.33
150.00
125.00
160.00
133.33
200.00
166.67
166.67
133.33
133.33
9 5 .0 0
126.67
6 6 .6 7
(M H z )
6 6 .6 7
6 6 .6 7
6 6 .6 7
6 6 .6 7
6 0 .0 0
6 2 .5 0
6 6 .6 7
8 0 .0 0
6 6 .6 7
6 2 .5 0
7 1 .4 3
6 6 .6 7
6 6 .6 7
6 3 .3 3
6 3 .3 3
5 0 .0 0
(M H z )
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
Note: For additional margin testing frequencies, refer to Byte 4
952001 Rev A 01/24/02
VDDSD
SDRAM
GNDSD
CPU_STOP#*
CPUCLKT_1
CPUCLKC_1
VDDCPU
GNDCPU
CPUCLKT_0
CPUCLKC_0
IREF
GNDA
VDDA
SCLK
SDATA
PD#*/Vtt_PWRGD
GNDAGP
AGPCLK0
AGPCLK1
VDDAGP
VDDA48
48MHz
24_48MHz/MULTISEL*
GND48
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
XTAL
OSC
PLL1
Spread
Spectrum
B it 2 B it 7 B it 6 B it 5 B it 4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin 300-mil SSOP and TSSOP
Functionality
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS952001
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
•
2 - Pairs of differential CPUCLKs (differential current mode)
•
1 - SDRAM @ 3.3V
•
8 - PCI @3.3V
•
2 - AGP @ 3.3V
•
2 - ZCLKs @ 3.3V
•
1- 48MHz, @3.3V fixed.
•
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
•
3- REF @3.3V, 14.318MHz.
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
Control
Logic
2
CPU
DIVDER
Stop
2
2
ZCLK
DIVDER
PCI
DIVDER
REF (1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
ZCLK (1:0)
2
Stop
6
PCICLK (9:0)
PCICLK_F (1:0)
Config.
Reg.
2
AGP
DIVDER
2
AGP (1:0)
I REF
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
ICS952001
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
General Description
The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero
delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 11, 13, 19, 29,
42, 48
2
3
4
PIN NAME
TYPE
VDD
PWR
FS0
IN
REF0
OUT
DESCRIPTION
Power supply for 3.3V
FS2
IN
REF2
OUT
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
FS1
IN
REF1
OUT
5, 8, 18, 24, 25,
32, 37, 41, 46
6
7
10, 9
GND
PWR
Ground pin for 3V outputs.
X1
X2
ZCLK(1:0)
IN
OUT
OUT
12
PCI_STOP#
IN
FS3
PCICLK_F0
FS4
PCICLK_F1
IN
OUT
IN
OUT
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Hyperzip clock outputs.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
MODE pin is in Mobile mode
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
PCICLK (5:0)
OUT
PCI clock outputs.
MULTISEL
24_48MHz
48MHz
AVDD
AGPCLK (1:0)
IN
OUT
OUT
PWR
OUT
PD#
IN
Vtt_PWRGD
IN
34
35
SDATA
SCLK
I/O
IN
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Clock output for super I/O/USB default is 24MHz
48MHz output clock
Analog power supply 3.3V
AGP outputs defined as 2X PCI. These may not be stopped.
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal.
When Vtt_PWRGD goes high the frequency select will be latched at
power on thereafter the pin is an asynchronous active low power down
pin.
2
Data pin for I C circuitry 5V tolerant
2
Clock pin of I C circuitry 5V tolerant
38
I REF
OUT
43, 39
CPUCLKC (1:0)
OUT
44, 40
CPUCLKT (1:0)
OUT
45
CPU_STOP#
IN
47
SDRAM
OUT
14
15
23, 22, 21, 20, 17,
16
26
27
28, 36
30, 31
33
This pin establishes the reference current for the CPUCLK
pairs. This pin requires a fixed precision resistor tied to ground
in order to establish the appropriate current.
"Complementary" clocks of differential pair CPU outputs. These clocks
are 180° out of phase with SDRAM clocks. These open drain outputs
need an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase
with SDRAM clocks. These open drain outputs need an external 1.5V pullup.
Stops all CPUCLKs clocks at logic 0 level, when MODE pin is in Mobile
mode
SDRAM clock output.
Third party brands and names are the property of their respective owners.
2
ICS952001
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
CPUCLK Swing Select Functions
MULTSEL0
Byte 23
Bit 7
Board Target
Trace/Term Z
0
0
60 ohms
0
0
50 ohms
0
1
60 ohms
0
1
50 ohms
1
0
60 ohms
1
0
50 ohms
1
1
60 ohms
1
1
50 ohms
0
0
30 (DC equiv)
0
0
25 (DC equiv)
0
1
30 (DC equiv)
0
1
25 (DC equiv)
1
0
30 (DC equiv)
1
0
25 (DC equiv)
1
1
30 (DC equiv)
1
1
25 (DC equiv)
Reference R,
Iref=
Vdd/(3*Rr)
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Third party brands and names are the property of their respective owners.
3
Output
Current
Voh @ Z,
Iref=2.32mA
Ioh = 5*Iref
0.71V @ 60
Ioh = 5*Iref
0.59V @ 50
Ioh = 4*Iref
0.56V @ 60
Ioh = 4*Iref
0.47V @ 50
Ioh = 6*Iref
0.85V /2 60
Ioh = 6*Iref
0.71V @ 50
Ioh = 7*Iref
0.99V @ 60
Ioh = 7*Iref
0.82V @ 50
Ioh = 5*Iref
0.75V @ 30
Ioh = 5*Iref
0.62V @ 20
Ioh = 4*Iref
0.60 @ 20
Ioh = 4*Iref
0.5V @ 20
Ioh = 6*Iref
0.90V @ 30
Ioh = 6*Iref
0.75V @ 20
Ioh = 7*Iref
1.05V @ 30
Ioh = 7*Iref
0.84V @ 20
ICS952001
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
General I2C serial interface information for the ICS952001
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
*See notes on the following page.
Third party brands and names are the property of their respective owners.
4
Not acknowledge
stoP bit
ICS952001
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Serial Configuration Command Bitmap
Bytes 0-3: Are reserved for external clock buffer.
Byte4: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2
Bit 7:4
Bit 3
Bit 1
Bit 0
Description
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4
FS4 FS3 FS2
FS1
FS0
CPU
SDRAM
ZCLK
0
0
0
0
0
66.67
66.67
66.67
0
0
0
0
1
100.00
100.00
66.67
0
0
0
1
0
100.00
200.00
66.67
0
0
0
1
1
100.00
133.33
66.67
0
0
1
0
0
100.00
150.00
60.00
0
0
1
0
1
100.00
125.00
62.50
0
0
1
1
0
100.00
160.00
66.67
0
0
1
1
1
100.00
133.33
80.00
0
1
0
0
0
100.00
200.00
66.67
0
1
0
0
1
100.00
166.67
62.50
0
1
0
1
0
100.00
166.67
71.43
0
1
0
1
1
80.00
133.33
66.67
0
1
1
0
0
80.00
133.33
66.67
0
1
1
0
1
95.00
95.00
63.33
0
1
1
1
0
95.00
126.67
63.33
0
1
1
1
1
66.67
66.67
50.00
1
0
0
0
0
105.00
140.00
70.00
1
0
0
0
1
100.90
100.90
67.27
1
0
0
1
0
108.00
144.00
72.00
1
0
0
1
1
100.90
134.53
67.27
1
0
1
0
0
112.00
149.33
74.67
1
0
1
0
1
133.33
100.00
66.67
1
0
1
1
0
133.33
133.33
66.67
1
0
1
1
1
133.33
166.67
66.67
1
1
0
0
0
100.00
133.00
80.00
1
1
0
0
1
100.00
100.00
80.00
1
1
0
1
0
100.00
166.67
83.33
1
1
0
1
1
133.33
160.00
80.00
1
1
1
0
0
100.00
133.00
100.00
1
1
1
0
1
100.00
100.00
100.00
1
1
1
1
0
100.00
166.67
100.00
1
1
1
1
1
133.33
160.00
100.00
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit , 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
PWD
AGP
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
70.00
67.27
72.00
67.27
74.67
66.67
66.67
66.67
66.67
66.67
62.50
66.67
66.67
66.67
62.50
66.67
PCI
33.33
33.33
33.33
33.33
30.00
31.25
33.33
33.33
33.33
31.25
41.67
33.33
33.33
31.67
31.67
25.00
35.00
33.63
36.00
33.63
37.33
33.33
33.33
33.33
33.33
33.33
31.25
33.33
33.33
33.33
31.25
33.33
Spread Precentage
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
Third party brands and names are the property of their respective owners.
5
00000
Note1
0
0
0
ICS952001
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Byte 5: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Pin#
30
31
PWD
1
1
Bit 5
26
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15
14
4
3
2
X
X
X
X
X
Description
AGPCLK1
AGPCLK1
SEL24_48MHz
(1=24MHz, 0=48MHz)
FS4 Read Back
FS3 Read Back
FS2 Read Back
FS1 Read Back
FS0 Read Back
Byte 6: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Pin#
10
9
PWD
1
1
Bit 5
14
0
Bit 4
15
0
Bit 3
40, 39
1
Bit 2
44, 43
1
Bit 1
Bit 0
39, 40
43, 44
1
1
Description
ZCLK1
ZCLK0
PCICLK_F0 stop control
0 = Free Running; 1 = Stop
PCICLK_F1 stop control
0 = Free Running; 1 = Stop
CPUCLKT/C0 stop control
0 = Free Running; 1 = Stop
CPUCLKT/C1 stop control
0 = Free Running; 1 = Stop
CPUCLKT/C0 output control
CPUCLKT/C1 output control
Byte 7: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
15
14
23
22
21
20
17
16
PWD
1
1
1
1
1
1
1
1
Description
PCICLK_F1
PCICLK_F0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 8: Byte Count Read Back Register
Bit
Bit 7
Bi t 6
Bit 5
Bi t 4
Bit 3
Bit 2
Bi t 1
Bi t 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
0
0
0
Note: Writing to this register will configure
0
byte count and how many bytes will be
read back, default is 0FH = 15 bytes.
1
1
1
1
Third party brands and names are the property of their respective owners.
6
ICS952001
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Byte 9: Watchdog Timer Count Register
Bit
Bit 7
B it 6
B it 5
B it 4
Bit 3
B it 2
B it 1
B it 0
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
0
0
0
1
0
0
0
0
Description
The decimal representation of these 8 bits
correspond to X • 290ms the watchdog
timer will wait before it goes to alarm mode
and reset the frequency to the safe setting.
Default at power up is 16 • 290ms = 4.6
seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Bit 7
Program
Enable
0
Bit 6 WD Enable
Bit 5 WD Alarm
Bit 4
S F4
Bit 3
SF3
Bit 2
SF2
Bit 1
SF1
Bit 0
S F0
0
0
0
0
0
0
1
Description
Programming Enable bit
0 = no programming. Frequencies are selected by
HW latches or Byte0
1 = enable all I2 C programing.
Watchdog Enable bit
Watchdog Alarm Status 0 = normal 1= alarm status
Watchdog safe frequency bits. Writing to these bits
will configure the safe frequency corrsponding to
Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
N divider bit 8
The decimal respresentation of Mdiv (6:0)
corresposd to the reference divider value.
Default at power up is equal to the latched
inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
X
X
X
X
X
X
X
X
Description
The decimal representation of Ndiv (8:0)
correspond to the VCO divider value.
Default at power up is equal to the latched
inputs selecton. Notice Ndiv 8 is located in
Byte 11.
Third party brands and names are the property of their respective owners.
7
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Byte 13: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
X
X
X
X
X
X
X
X
Description
The Spread Spectrum (12:0) bit will
program the spread precentage. Spread
precent needs to be calculated based on
the VCO frequency, spreading profile,
spreading amount and spread frequency. It
is recommended to use ICS software for
spread programming. Default power on is
latched FS divider.
Byte 14: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SD Div 3
SD Div 2
SD Div 1
SD Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
PWD
X
X
X
X
X
X
X
X
Description
SDRAM clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 1. Default at power up is latched
FS divider.
CPUCLKT/C clock divider ratio can be
configured via these 4 bits individually.
For divider selection table refer to
Table 1. Default at power up is latched
FS divider.
Byte 16: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP Div 3
AGP Div 2
AGP Div 1
AGP Div 0
ZCLK Div 3
ZCLK Div 2
ZCLK Div 1
ZCLK Div 0
PWD
X
X
X
X
X
X
X
X
Description
AGP clock divider ratio can be
configured via these 4 bits
individually. For divider selection
table refer to Table 1. Default at
power up is latched FS divider.
ZCLK clock divider ratio can be
configured via these 4 bits
individually. For divider selection
table refer to Table 1. Default at
power up is latched FS divider.
Third party brands and names are the property of their respective owners.
8
ICS952001
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Byte 17: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP_INV
ZCLK_INV
SD_INV
CPU_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
PWD
0
0
0
0
X
X
X
X
Table 1
Div (3:2)
Table 2
00
01
10
11
00
/2
/4
/8
/16
01
/3
/6
/12
Div (1:0)
Description
AGP Phase Inversion bit
ZCLK Phase Inversion bit
SDRAM Phase Inversion bit
CPUCLK Phase Inversion bit
PCI clock divider ratio can be
configured via these 4 bits
individually. For divider selection
table refer to table 2. Default at
power up is latched FS divider.
Div (3:2)
00
01
10
11
00
/4
/8
/16
/32
/24
01
/3
/6
/12
/24
Div (1:0)
10
/5
/10
/20
/40
10
/5
/10
/20
/40
11
/7
/14
/28
/56
11
/7
/14
/28
/56
Byte 18: Group Skew Control Register
Bit
Name
PWD
Bit 7
CPU_Skew 1
1
Bit 6
CPU_Skew 0
0
Bit 5
SD_Skew 1
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SD_Skew 0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
1
1
1
1
1
Description
These 2 bits delay the CPUCLKT/C (1:0)
clocks with respect to all other clocks.
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
These 2 bits delay the SDRAM with respect to
CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
(Reserved)
Byte 19: Group Skew Control Register
B it
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N ame
These 4bi ts control
C PU-ZC LK(1:0)
These 4 bi ts control
C PU-AGP(1:0)
P WD
Programmable D elay Stop
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0 1 1 0 2.75ns 1 1 1 0 3.95ns
0 1 1 1 2.90ns 1 1 1 1 4.10ns
Third party brands and names are the property of their respective owners.
9
1.85ns
2.00ns
2.15ns
2.30ns
2.45ns
2.60ns
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
3.05ns
3.20ns
3.35ns
3.50ns
3.65ns
3.80ns
ICS952001
Preliminary Product Preview
Integrated
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Byte 20: Group Skew Control Register
B it
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N ame
P WD
These 4bi ts control
C PU-PC IC LK_F(1:0)
These 4 bi ts control
C PU-PC IC LK(5:0)
Programmable D elay Stop
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1.85ns
2.00ns
2.15ns
2.30ns
2.45ns
2.60ns
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
3.05ns
3.20ns
3.35ns
3.50ns
3.65ns
3.80ns
0
0
0 1 1 0 2.75ns 1 1 1 0 3.95ns
0 1 1 1 2.90ns 1 1 1 1 4.10ns
Byte 21: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
24/48_Slew
AGP_Slew
ZCLK_Slew
REF_Slew
PWD
0
0
0
0
0
0
0
0
Description
24/48 MHz clock slew rate control bits.
01 = strong; 00, 11 = normal; 10 = weak
AGP clock slew rate control bits.
01 = strong; 00, 11 = normal; 10 = weak
ZCLK clock slew rate control bits.
01 = strong; 00, 11 = normal; 10 = weak
REF clock slew rate control bits.
01 = strong; 00, 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SDRAM Slew
(Reser ved)
PCICLK_F Slew
PCICLK Slew
PWD
0
0
X
X
0
0
0
0
Description
SDRAM clock slew rate control bits.
01 = strong; 00, 11 = normal;10 = weak
(Reser ved)
PCICLK_F clock slew rate control bits.
01 = strong; 00, 11 = normal;10 = weak
PCICLK clock slew rate control bits.
01 = strong; 00, 11 = normal;10 = weak
Byte 23: Output Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
47
27
26
4
3
2
PWD
0
1
1
1
1
1
1
1
Description
Iref Output Control
MULITSEL Readback
SDRAM
48MHz
24_48MHz
REF2
REF1
REF0
Third party brands and names are the property of their respective owners.
10
ICS952001
Preliminary Product Preview
Integrated
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Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . .
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . .
4.6 V
3.6V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
–65°C to +150°C
115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T A = 0 - 70C; Supply Voltage VDD
PARAMETER
SYMBOL
Input High Voltage
VIH
Input Low Voltage
V IL
Input High Current
I IH
Input Low Current
I IL1
Input Low Current
I IL2
Operating
I DD3.3O P
Supply Current
Power Down
I DD3.3PD
Supply Current
Input frequency
Fi
Pin Inductance
Lpin
Input Capacitance1
C IN
C out
C INX
Transition Time1
Ttrans
Settling Time
1
Clk Stabilization1
Delay
1
= 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
CONDITIONS
MIN
TYP
2
VSS-0.3
VIN = VDD
-5
VIN = 0 V; Inputs with no pull-up resistors
-5
VIN = 0 V; Inputs with pull-up resistors
-200
C L = 30 pF; CPU @ 133 MHz
C L = 0 pF
VDD = 3.3 V
MAX
VDD +0.3
0.8
5
280
UNITS
V
V
mA
mA
mA
mA
25
mA
7
MHz
nH
5
6
45
pF
pF
pF
14.32
Logic Inputs
Out put pin capacitance
X1 & X2 pins
27
To 1st crossing of target Freq.
3
mS
Ts
From 1st crossing to 1% target Freq.
3
mS
TSTAB
t PZH ,t PZH
t PLZ ,t PZH
From VDD = 3.3 V to 1% target Freq.
output enable delay (all outputs)
output disable delay (all outputs)
3
10
10
mS
nS
nS
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
1
1
ICS952001
Preliminary Product Preview
Integrated
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Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
RDSP2B1
RDSN2B1
VOH2B
VOL2B
IOH2B
IOL2B
tr2B1
tf2B1
dt2B1
tsk2B1
tjcyc-cyc1
CONDITIONS
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
MIN
TYP
13.5
13.5
2
-27
27
0.4
0.4
45
MAX UNITS
45
45
50
0.4
-27
30
1.6
1.6
55
175
250
Ω
Ω
V
V
mA
mA
ns
ns
ns
ps
ps
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - PCI
T A = 0 - 70C; V DD = 3.3 V +/-5% ; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
CONDITIONS
RDSP1
1
V O = V DD*(0.5)
RDSN1
V OH1
V OL1
I OH1
I OL1
1
V O = V DD*(0.5)
I OH = -18 mA
I OL = 9.4 mA
V OH = 2.0 V
V OL = 0.8 V
t r1
1
V OL = 0.4 V, V OH = 2.4 V
Fall Time
t f1
1
V OH = 2.4 V, V OL = 0.4 V
Duty Cycle
dt1 1
V T = 1.5 V
1
V T = 1.5 V
V T = 1.5 V
Rise Time
Skew Window
Jitter
1
SYMBOL
ts k 1
t j1s 1 1
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
MAX
UNITS
12
55
Ω
12
2.4
55
Ω
V
V
mA
mA
MIN
TYP
0.4
-22
25
45.0
2.0
ns
2.0
ns
55.0
%
500
ps
250
ps
ICS952001
Preliminary Product Preview
Integrated
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Electrical Characteristics - 24M, 48M, REF
TA = 0 - 70C; V DD = V DDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
RDSP5
V O = V DD*(0.5)
RDSN5
V OH5
V OL5
I OH5
I OL5
1
V O = V DD*(0.5)
I OH = -14 mA
I OL = 6.0 mA
V OH = 2.0 V
V OL = 0.8 V
UNITS
20
60
Ω
20
2.4
60
Ω
V
V
mA
mA
TYP
10
t r5
V OL = 0.4 V, V OH = 2.4 V
Fall Time
t f5
1
V OH = 2.4 V, V OL = 0.4 V
Duty Cycle
dt51
t j1s51
Jitter
MAX
MIN
0.4
-20
1
Rise Time
1
CONDITIONS
1
V T = 1.5 V
V T = 1.5 V
45.0
4.0
ns
4.0
ns
55.0
%
500
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
T A = 0 - 70C; V DD =V DDL 3.3 V +/-5% ; CL = 30 pF (unless otherwise stated)
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
RDSP2A
1
V O = V DD*(0.5)
10
20
Ω
RDSN2A
V OH2A
V OL2A
I OH2A
I OL2A
1
V O = V DD*(0.5)
I OH = -28 mA
I OL = 19 mA
V OH = 2.0 V
V OL = 0.8 V
10
2.4
20
Ω
V
V
mA
mA
t r2A
1
V OL = 0.4 V, V OH = 2.4 V
0.5
Fall Time
t f2A
1
V OH = 2.4 V, V OL = 0.4 V
Duty Cycle
Jitter1
dt2A 1
V T = 1.5 V
V T = 1.5 V
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
1
SYMBOL
t cy c -c y c
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
0.4
-42
33
2.0
ns
0.5
2
ns
45
55
%
250.0
ps
ICS952001
Preliminary Product Preview
Integrated
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Shared Pin Operation Input/Output Pins
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming
resistors should be located close to the series termination
resistor to minimize the current loop area. It is more important
to locate the series termination resistor close to the driver
than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
14
ICS952001
Preliminary Product Preview
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PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
Normal
Normal
0
iref * Mult
Float
Third party brands and names are the property of their respective owners.
15
ICS952001
Preliminary Product Preview
Integrated
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c
N
SYMBOL
L
E1
E
INDEX
AREA
1 2
α
h x 45°
D
A
A
A1
b
c
D
E
E1
e
h
L
N
α
A1
-Ce
b
SEATING
PLANE
.10 (.004) C
N
48
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
D (inch)
MIN
.620
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS952001yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
16
MAX
.630
ICS952001
Preliminary Product Preview
Integrated
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Systems, Inc.
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-
1.20
-
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
SEE VARIATIONS
D
8.10 BASIC
E
E1
6.00
e
L
N
.0035
.008
SEE VARIATIONS
6.20
0.319
.236
0.50 BASIC
0.45
0.75
SEE VARIATIONS
.244
0.020 BASIC
.018
.30
SEE VARIATIONS
α
0°
8°
0°
8°
aaa
-
0.10
-
.004
MIN
MAX
MIN
12.40
12.60
VARIATIONS
N
48
D mm.
D (inch)
.488
.496
MO-153 JEDEC
Doc.# 10-0039
7/6/00 Rev B
Ordering Information
ICS952001yFT
Example:
ICS XXXX y G - PPP
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G=TSSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Registered Company
9001
For more information on Integrated Circuit Systems Inc. or any of our products please visit our web site at:
http://www.icst.com
17
MAX