ICS ICS950908

ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Recommended Application:
Features/Benefits:
VIA Pro266/PN266/CLE266/CM400 chipset for PIII/Tualatin/C3 •
Programmable output frequency.
Processor
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
Output Features:
•
Programmable output skew.
•
1 - Pair of differential CPU clocks @ 3.3V (CK408)/
•
Programmable spread percentage for EMI control.
•
1 - Pair of differential open drain CPU clocks (K7)
•
Watchdog timer technology to reset system
•
2 - Push pull CPUT_CS clocks @ 2.5V
if system malfunctions.
•
3 - AGP @ 3.3V
•
Programmable watch dog safe frequency.
•
7 - PCI @ 3.3V
•
Support I2C Index read/write and block read/write
•
1 - 48MHz @ 3.3V fixed
operations.
•
1 - 24_48MHz @ 3.3V
•
Uses external 14.318MHz crystal.
•
2 - REF @ 3.3V, 14.318MHz
Key Specifications:
•
CPU_CS - CPUT/C: <±250ps
•
CPU_CS - AGP: <±250ps
•
CPU - DDR/SD: <±250ps
•
PCI - PCI: <500ps
Pin Configuration
Frequency Table
*FS0/REF0 1
FS2
FS1
FS0
CPUCLK
MHz
AGP
MHz
PCICLK
MHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
160.00
164.00
166.60
170.00
175.00
180.00
185.00
190.00
66.80
100.90
133.60
200.40
66.60
100.00
200.00
133.30
80.00
82.00
66.60
68.00
70.00
72.00
74.00
76.00
66.80
67.27
66.80
66.80
66.60
66.60
66.60
66.60
40.00
41.00
33.30
34.00
35.00
36.00
37.00
38.00
33.40
33.63
33.40
33.40
32.30
33.30
33.30
33.30
Board Target
Trace/Term Z
Reference R,
Iref =
VDD/(3*Rr)
0
50 ohms
Rr = 221 1%,
Iref = 5.00mA
Ioh = 4* I REF
1.0V @ 50
1
50 ohms
Rr = 475 1%,
Iref = 2.32mA
Ioh = 6* I REF
0.7V @ 50
MULTISEL0
Output
Current
Voh @ Z
56 Vtt_PWRGD#**/REF1
GND 2
55 VDDREF
X1 3
54 GND
X2 4
53 CPUCLKT/CPUCLKODT
VDDAGP 5
52 CPUCLKC/CPUCLKODC
*MODE/AGPCLK0 6
51 VDDCPU3.3
*SEL_408/K7/AGPCLK1 7
50 VDDCPU2.5
*(PCI_STOP#)AGPCLK2 8
49 CPUT0_CS
GNDAGP 9
48 CPUT1_CS
**FS1/PCICLK_F 10
47 GND
**SEL_SDR/DDR#/PCICLK1 11
46 FBOUT
*MULTSEL/PCICLK2 12
45 BUF_IN
GNDPCI 13
PCICLK3 14
PCICLK4 15
VDDPCI 16
PCICLK5 17
*(CLK_STOP#)/PCICLK6 18
ICS950908
FS3
44 DDRT0/SDRAM0
43 DDRC0/SDRAM1
42 DDRT1/SDRAM2
41 DDRC1/SDRAM3
40 VDD3.3_2.5
39 GND
GND48 19
38 DDRT2/SDRAM4
*FS3/48MHz 20
37 DDRC2/SDRAM5
*FS2/24_48MHz 21
36 DDRT3/SDRAM6
AVDD48 22
35 DDRC3/SDRAM7
VDD 23
34 VDD3.3_2.5
GND 24
33 GND
IREF 25
32 DDRT4/SDRAM8
*(PD#)RESET# 26
31 DDRC4/SDRAM9
SCLK 27
30 DDRT5/SDRAM10
SDATA 28
29 DDRC5/SDRAM11
* Internal 120K pull-up resistor to VDD.
** Internal 120K pull-down resistor to GND.
56-Pin 300-mil SSOP
0653A—07/26/04
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
General Description
The ICS950908 is a single chip clock solution for desktop designs using the VIA Pro266/PN266/CLE266/CM400 chipset with
PC133 or DDR memory.
The ICS950908 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
(1:0)
FBOUT
Mode
SEL_SDR/DDR#
BUF_IN
SEL_408/K7#
Power Groups
Pin Number
Description
VDD
GND
55
2
Xtal, Ref
5
9
AGP [0:2], CPU digital, CPU PLL
16
13
PCI [0:5], PCI_F outputs
22
19
48MHz, Fix Digital, Fix Analog
23
24
Master clock, CPU Analog
34, 40
33, 39
DDR/SDR outputs
50
47
2.5V CPUT_CS output
51
54
3.3V CPUT/C & CPUOD_T/C
0653A—07/26/04
2
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Pin Description
PIN
#
1
PIN
NAME
2
3
4
5
6
*FS0/REF0
PIN
TYPE
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
GND
X1
X2
VDDAGP
PWR
IN
OUT
PWR
Ground pin.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Power supply for AGP clocks, nominal 3.3V
DESCRIPTION
I/O
Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / AGP clock output.
I/O
7
*MODE/AGPCLK0
*SEL_408/K7/AGPCLK1
8
*(PCI_STOP#)AGPCLK2
I/O
9
10
GNDAGP
**FS1/PCICLK_F
PWR
I/O
CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / AGP clock output.
Ground pin for the AGP outputs
Frequency select latch input pin / 3.3V PCI free running clock output.
11
**SEL_SDR/DDR#/PCICLK1
I/O
Memory type select latch input pin 0= DDR, 1= PC133 SDRAM / 3.3V PCI clock output.
12
*MULTSEL/PCICLK2
I/O
13
14
15
16
17
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PWR
OUT
OUT
PWR
OUT
18
*(CLK_STOP#)/PCICLK6
I/O
19
20
21
22
23
24
GND48
*FS3/48MHz
*FS2/24_48MHz
AVDD48
VDD
GND
PWR
I/O
I/O
PWR
PWR
PWR
25
IREF
OUT
26
*(PD#)RESET#
I/O
27
SCLK
28
SDATA
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive strength
IN
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 3.3V PCI clock
output.
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
Stops all CPU, DDR/SDRAM and FB_OUT clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / PCI clock output.
Ground pin for the 48MHz outputs
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V
Power supply, nominal 3.3V
Ground pin.
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
Asynchronous active low input pin used to power down the device into a low power
state. This input is activated by the MODE selection pin / Real time system reset
signal for frequency gear ratio change or watchdog timer timeout. This signal is active
low.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Pin description continued on next page.
0653A—07/26/04
3
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Pin Description Continued
PIN
#
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
PIN
NAME
DDRC5/SDRAM11
DDRT5/SDRAM10
DDRC4/SDRAM9
DDRT4/SDRAM8
GND
VDD3.3_2.5
DDRC3/SDRAM7
DDRT3/SDRAM6
DDRC2/SDRAM5
DDRT2/SDRAM4
GND
VDD3.3_2.5
DDRC1/SDRAM3
DDRT1/SDRAM2
DDRC0/SDRAM1
DDRT0/SDRAM0
BUF_IN
FBOUT
GND
CPUT1_CS
CPUT0_CS
VDDCPU2.5
VDDCPU3.3
PIN
TYPE
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
OUT
PWR
OUT
OUT
PWR
PWR
52
CPUCLKC/CPUCLKODC
OUT
53
CPUCLKT/CPUCLKODT
OUT
54
55
GND
VDDREF
PWR
PWR
56
Vtt_PWRGD#**/REF1
I/O
DESCRIPTION
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complimentary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Input Buffers for memory outputs.
Memory feed back output.
Ground pin.
True clock of differential pair 2.5V push-pull CPU outputs.
True clock of differential pair 2.5V push-pull CPU outputs.
Power pin for the CPUCLKs. 2.5V
Power pin for the CPUCLKs. 3.3V
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias / "Complementary" clocks of
differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /
2.5V CPU clock output.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "True" clocks of differential pair CPU
outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / 14.318 MHz
reference clock.
Mode Pin - Power Management Input Control
MODE, Pin 6
(Latched Input)
0
1
Pin 26
Pin 18
Pin 8
PD#
(Input)
RESET#
(Output)
CPU_STOP#
(Input)
PCICLK5
(Output)
PCI_STOP#
(Input)
AGP2
(Output)
0653A—07/26/04
4
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
General I2C serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
*See notes on the following page.
0653A—07/26/04
5
Not acknowledge
stoP bit
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Byte 0: Functionality and frequency select register (Default=0)
Bit
Bit2
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
PWD
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
010101-
Bit7 Bit6 Bit5 Bit4 CPUCLK AGPCLK PCICLK
MHz
MHz
MHz
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Frequency is selected by
Frequency is selected by
Normal
Spread spectrum enable
Running
Tristate all outputs
102.00
68.00
34.00
105.00
70.00
35.00
108.00
72.00
36.00
111.00
74.00
27.00
114.00
76.00
38.00
117.00
78.00
39.00
120.00
80.00
40.00
123.00
82.00
41.00
126.00
72.00
36.00
130.00
74.30
37.10
133.90
66.95
33.48
140.00
70.00
35.00
144.00
72.00
36.00
148.00
74.00
37.00
152.00
76.00
38.00
156.00
78.00
39.00
160.00
80.00
40.00
164.00
82.00
41.00
166.60
66.60
33.30
170.00
68.00
34.00
175.00
70.00
35.00
180.00
72.00
36.00
185.00
74.00
37.00
190.00
76.00
38.00
66.80
66.80
33.40
100.90
67.27
33.63
133.60
66.80
33.40
200.40
66.80
33.40
66.60
66.60
32.30
100.00
66.60
33.30
200.00
66.60
33.30
133.30
66.60
33.30
hardware select, latched inputs
Bit 2,7:4
Spread %
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.50% Center Spread
+/- 0.50% Center Spread
+/- 0.50% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
0 to - 0.6% Down Spread
0 to - 0.6% Down Spread
0 to - 0.6% Down Spread
0 to - 0.6% Down Spread
Notes 1, 2
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
2. B0b2 default = 0.
0653A—07/26/04
6
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Byte 1: CPU Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
29
10
30
31
49
32
53, 52
48
PWD
1
1
1
1
1
1
1
1
Description
SDRAM11/DDRC5 (Active/Inactive)
PCICLK_F (Active/Inactive)
SDRAM10/DDRT5 (Active/Inactive)
SDRAM9/DDRC4 (Active/Inactive)
CPUT0_CS Free running control; 1 = free running; 0 = not free running
SDRAM8/DDRT4 (Active/Inactive)
CPUCLKT/C (Active/Inactive)
CPUCLKT1_CS (Active/Inactive)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
46
18
17
15
14
12
11
53, 52
PWD
1
1
1
1
1
1
1
1
Description
FB_OUT Free running control; 1 = free running; 0 = not free running
PCICLK5 (Active/Inactive)
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLK1 (Active/Inactive)
PCICLK0 (Active/Inactive)
CPUCLKT/C Free running control; 1 = free running; 0 = not free running
Byte 3: Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
46
56
48
8
7
6
PWD
1
1
1
1
1
1
1
1
Description
FB_OUT (Active/Inactive)
SEL 24_48, 0=24Mhz 1=48MHz
SD/DDR free running control; 1 = free running; 0 not free running
REF1 (Active/Inactive)
CPUT1_CS free running control; 1 = free running; 0 not free running
AGPCLK 2 (Active/Inactive)
AGPCLK 1 (Active/Inactive)
AGPCLK 0 (Active/Inactive)
Byte 4: Frequency Select Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Pin#
20
21
49
1
PWD
X
X
X
X
1
1
1
1
Description
Latched FS3
Latched FS2
Latched FS1
Latched FS0
48MHz (Active/Inactive)
24_48MHz (Active/Inactive)
CPUT0_CS (Active/Inactive)
REF0 (Active/Inactive)
0653A—07/26/04
7
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Pin#
35
36
37
38
41
42
43
44
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7/DDRC3 (Active/Inactive)
SDRAM6/DDRT3 (Active/Inactive)
SDRAM5/DDRC2 (Active/Inactive)
SDRAM4/DDRT2 (Active/Inactive)
SDRAM3/DDRC1 (Active/Inactive)
SDRAM2/DDRT1 (Active/Inactive)
SDRAM1/DDRC0 (Active/Inactive)
SDRAM0/DDRT0 (Active/Inactive)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
PWD
X
X
X
X
0
0
0
1
Description
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
PWD
Description
0
0
0
Device ID values will be based on individual device
1
"01h" in this case.
0
1
1
1
Byte 8: Byte Count Read Back Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
0
0
0
Note: Writing to this register will configure byte count and how
0
many bytes will be read back, default is 0FH = 15 bytes.
1
1
1
1
0653A—07/26/04
8
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Byte 9: Watchdog Timer Count Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
0
0
0
The decimal representation of these 8 bits correspond to X •
1
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
0
16 • 290ms = 4.6 seconds.
0
0
0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Bi t 7
Program
Enable
0
Bi t 6
WD Enable
0
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
WD Alarm
S F4
S F3
S F2
S F1
S F0
0
0
0
0
0
0
Description
Programming Enable bit
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I2C programing.
Software Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Watchdog Alarm Status 0 = normal 1= alarm status
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider value. Default at power up is equal to the
latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
Description
X
X
X
The decimal representation of Ndiv (8:0) correspond to the
X
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
X
X
X
X
0653A—07/26/04
9
ICS950908
Preliminary Product Preview
Integrated
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Systems, Inc.
Byte 13: Spread Spectrum Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
Description
X
X
The Spread Spectrum (12:0) bit will program the spread
X
precentage. Spread precent needs to be calculated based on the
X
VCO frequency, spreading profile, spreading amount and spread
X
frequency. It is recommended to use ICS software for spread
X
programming. Default power on is latched FS divider.
X
X
Byte 14: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
PWD
0
1
0
1
0
1
0
1
Description
CPUCLKC/T clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
CPUCLKT_CS clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP Div 3
AGP Div 2
AGP Div 1
AGP Div 0
Reser ved
Reser ved
Reser ved
Reser ved
PWD
0
1
0
1
-
Description
AGP clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
Reser ved
0653A—07/26/04
10
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Byte 17: Output Divider Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
AGP_INV
Reserved
CPU_INV
CPU_INV
PWD
0
0
0
0
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
1
0
0
1
Description
AGP Phase Inversion bit
Reserved
CPU T/C Phase Inversion bit
CPUT/C_CS Phase Inversion bit
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
Table 1
Div (3:2)
Table 2
00
01
10
11
00
/2
/4
/8
/16
Div (1:0)
Div (3:2)
00
01
10
11
00
/4
/8
/16
/32
Div (1:0)
01
/3
/6
/12
/24
01
/3
/6
/12
/24
10
/5
/10
/20
/40
10
/5
/10
/20
/40
11
/7
/14
/28
/56
11
/9
/18
/36
/72
Byte 18: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
CPUCLKT_CS
Group Skew
Control
CPUCLKT/C
Group Skew
Control
AGPCLK
Group Skew
Control
Reserved
Reserved
PWD
1
0
1
0
1
Description
These 2 bits delay the CPUCLKT/C_CS with respect to
CPUCLKT_CS
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
These 2 bits delay the CPUCLKT/C clock with respect to
CPUCLKT/C_CS
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
0
These 2 bits delay the AGPCLK clocks with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
X
X
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Reserved
PCICLK(5:0)
Group Skew
Control
PWD
Description
1
0
Reserved
0
0
1
These 4 bits can change the CPU to PCI (5:0) skew from 1.4ns 0
2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bits (3:0) will increase or decrease the delay of the
0
PCI clocks by 100ps.
0
0653A—07/26/04
11
ICS950908
Preliminary Product Preview
Integrated
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Systems, Inc.
Byte 20: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
PCICLK_F
Group Skew
Control
Reserved
PWD
Description
1
These 4 bits can change the CPU to PCIF skew from 1.4ns 0
2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bit (3:0) will increase or decrease the delay of the
0
PCI clocks by 100ps.
0
1
0
Reserved
0
0
Byte 21: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Reserved
CPUCLKT/C
OD/CS
AGP_0
Slew Rate Control
PWD
0
1
0
1
0
1
0
1
Description
Reserved
CPUCLKT/C OD/CS clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
AGP_0 clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
Byte 22: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
AGP(2:1)
Slew Rate Control
PCICLK_F
Slew Rate Control
PCICLK(7:4)
Slew Rate Control
PCICLK(3:0)
Slew Rate Control
PWD
0
1
0
1
0
1
0
1
Description
AGP(2:1) clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
PCICLK_F clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
PCICLK(7:4) clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
PCICLK(3:0) clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
Byte 23: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
REF (1:0)
Slew Rate Control
Reserved
48MHz
Slew Rate Control
24_48MHz
Slew Rate Control
PWD
0
1
0
1
0
1
0
1
Description
REF clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
Reserved
48MHz clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
24_48MHz clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
0653A—07/26/04
12
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +5%
PARAMETER
SYMBOL
Input High Voltage
VIH
2
VDD + 0.3
V
Input Low Voltage
Input High Current
VIL
VSS - 0.3
0.8
V
-5
-5
5
mA
mA
CONDITIONS
Input Low Current
IIH
IIL1
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
Operating
IDD3.3OP
Supply Current
Power Down
Supply Current
IDD3.3PD
Fi
Pin Inductance
Lpin
Input Capacitance1
CIN
Cout
Logic Inputs
Out put pin capacitance
C INX
X1 & X2 pins
Ttrans
Transition Time
Settling Time1
Clk Stabilization
Delay
1
TYP
MAX
-200
CL = 0 pF; Select @ 66M
CL = Full load
IREF=2.32
IREF= 5mA
Input frequency
1
MIN
UNITS
mA
100
280
20
37
VDD = 3.3 V;
mA
mA
mA
mA
MHz
27
7
nH
5
6
pF
pF
45
pF
To 1st crossing of target Freq.
3
mS
Ts
From 1st crossing to 1% target Freq.
3
mS
TSTAB
From VDD = 3.3 V to 1% target Freq.
tPZH,tPZH
tPLZ,tPZH
3
mS
output enable delay (all outputs)
1
10
nS
output disable delay (all outputs)
1
10
nS
1
Guaranteed by design, not 100% tested in production.
0653A—07/26/04
13
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - CPUCLKC/T
TA = 0 - 70º C; VDD = 3.3 V +/-5%; (unless otherwise stated)
PARAMETER
Current Source
Output Impedance
Output High Voltage
Output High Current
Rise Time1
Differential Crossover
Voltage1
Duty Cycle1
1
Skew , CPU to CPU
Jitter, Cycle-to-cycle1
SYMBOL
ZO
CONDITIONS
VO = VX
VOH
IOH
tr
MIN
TYP
MAX
3000
VOL = 20%, VOH = 80%
W
0.71
-13.92
VR = 475Ω +1%; IREF = 2.32mA; IOH = 6*IREF
UNITS
175
1.2
700
V
mA
ps
VX
Note 3
45
50
55
%
dt
tsk
VT = 50%
VT = 50%
VT = VX
45
51
55
150
200
%
ps
ps
MIN
2
TYP
tjcyc-cyc
Notes:
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLKT/C_CS
TA = 0 - 70ÜC; V DD = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH2B
VOL2B
I OH2B
IOL2B
1
Rise Time
t r2B
Differential Crossover
Voltage1
VX
Duty Cycle
dt2B1
Skew
t sk2B
Jitter, One Sigma
Jitter, Absolute
1
1
t j1s2B
t jabs2B1
I OH = -12.0 mA
I OL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
19
VOL = 0.4 V, VOH = 2.0 V
1
Jitter, Cycle-to-cycle t jcyc-cyc2B
CONDITIONS
1
MAX UNITS
V
0.4
V
-19
mA
mA
1.6
ns
55
%
55
%
VT = 1.25 V
175
ps
VT = 1.25 V
250
ps
VT = 1.25 V
VT = 1.25 V
150
ps
+250
ps
Note 3
45
VT = 1.25 V
45
-250
Guaranteed by design, not 100% tested in production.
0653A—07/26/04
14
50
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - SDRAM
TA = 0 - 70°C; V DD = 3.3V +/-5%, VDDL = 2.5V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
1
Fall Time
1
Duty Cycle
Skew window1
Propagation Time1
(Buffer In to Output)
SYMBOL
V OH3
V OL3
I OH3
IOL3
CONDITIONS
IOH = -28 mA
IOL = 20 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.4
TYP
41
MAX UNITS
V
0.4
V
-40
mA
mA
t r3
VOL = 0.4 V, V OH = 2.4 V
2
ns
t f3
dt3
VOH = 2.4 V, V OL = 0.4 V
VT = 1.5 V
2
55
ns
%
t sk3
VT = 1.5 V
250
ps
Tprop
VT = 1.5 V
5
ns
45
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - DDRT/C
TA = 0 - 70°C; V DDL = 2.5 V +/-5%, CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
V OH3
V OL3
I OH3
IOL3
Skew1(window)
Tr31
Tf31
Dt31
Tsk 1
Jitter
t jcyc-cyc 1
Fall Time1
Duty Cycle1
CONDITIONS
IOH = -11 mA
IOL = 11 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2
12
TYP
MAX UNITS
V
0.4
V
-12
mA
mA
20% to 80%
2.2
ns
80% to 20%
2.2
ns
53
%
250
ps
250
ps
VT = 50%
47
VT = 50%
VT = 1.25 V
0653A—07/26/04
15
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%; C L = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
F0 1
R DSN11
VOH1
VOL1
Output High Current
Output Low Current
CONDITIONS
MIN
TYP
MAX
UNITS
55
MHz
Ω
33.33
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
2.4
0.55
V
V
IOH1
IOL1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
-33
30
-33
38
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
Fall Time
tf11
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
Duty Cycle
VT = 1.5 V
45
55
%
Skew
dt11
tsk11
500
ps
Jitter
tjcyc-cyc1
250
ps
MAX
UNITS
MHz
55
Ω
VT = 1.5 V
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - AGP
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =10-30 pF (unless otherwise stated)
PARAMETER
Output Frequency
SYMBOL
FO1
Output Impedance
R DSP11
VO = VDD*(0.5)
12
Output High Voltage
Output Low Voltage
VOH1
VOL1
IOH = -1 mA
IOL = 1 mA
2.4
0.4
V
V
Output High Current
IOH1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
-33
-33
mA
Output Low Current
IOL1
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
30
38
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
Fall Time
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
VT = 1.5 V
45
55
%
Skew
tf11
d t11
tsk11
VT = 1.5 V
500
ps
Jitter
tjcyc-cyc1
VT = 1.5 V
250
ps
Duty Cycle
CONDITIONS
1
Guaranteed by design, not 100% tested in production.
0653A—07/26/04
16
MIN
TYP
66.66
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - 48MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Frequency
FO1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
RDSN11
Output Low Current
48DOT Rise Time
48DOT Fall Time
VCH 48 USB
Rise Time
VCH 48 USB
Fall Time
48 DOT to 48 USB
Skew
Duty Cycle
Jitter
CONDITIONS
MIN
VO = VDD*(0.5)
TYP
MAX
48
UNITS
MHz
55
Ω
-29
0.55
-23
V
V
mA
29
27
mA
VOL = 0.4 V, VOH = 2.4 V
0.5
1
ns
VOH = 2.4 V, VOL = 0.4 V
0.5
1
ns
tr 1
VOL = 0.4 V, VOH = 2.4 V
1
2
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
1
2
ns
1
ns
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
IOL1
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
tr11
tf11
VOH1
VOL1
IOH1
tskew 1
VT=1.5V
d t11
VT = 1.5 V
VT = 1.5 V
tjcyc-cyc1
12
2.4
45
55
%
350
ps
MAX
UNITS
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =10-20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Frequency
FO1
CONDITIONS
MIN
TYP
MHz
60
Ω
0.4
V
V
-23
27
mA
mA
Output Impedance
RDSP11
VO = VDD*(0.5)
20
Output High Voltage
Output Low Voltage
VOH1
VOL1
IOH = -1 mA
IOL = 1 mA
2.4
Output High Current
Output Low Current
IOH1
IOL1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
-29
29
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
1
4
ns
Fall Time
tf11
dt11
VOH = 2.4 V, VOL = 0.4 V
1
4
ns
45
55
500
%
ps
Duty Cycle
Jitter
tjcyc-cyc
VT = 1.5 V
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
0653A—07/26/04
17
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
0653A—07/26/04
18
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
Power Down Waveform
0ns
25ns
1
50ns
2
VCO Internal
CPU 100MHz
3.3V 66MHz
PCI 33MHz
APIC 16.7MHz
PD#
SDRAM 100MHz
REF 14.318MHZ
48MHZ
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
0653A—07/26/04
19
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
0ns
10ns
20ns
30ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.5V 66MHz
PCI 33MHz
APIC 16.7MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
0653A—07/26/04
20
40ns
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
c
N
L
E1
INDEX
AREA
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
N
α
E
1 2
h x 45°
D
A
A1
-Ce
N
SEATING
PLANE
b
.10 (.004) C
56
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
18.31
18.55
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS950908yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0653A—07/26/04
21
D (inch)
MIN
.720
MAX
.730
ICS950908
Preliminary Product Preview
Integrated
Circuit
Systems, Inc.
c
N
L
E1
INDEX
AREA
E
1 2
α
D
A
A2
VARIATIONS
A1
N
-Ce
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
a
0°
8°
0°
8°
aaa
-0.10
-.004
56
SEATING
PLANE
b
D mm.
MIN
13.90
D (inch)
MAX
14.10
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
aaa C
Ordering Information
ICS950908yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0653A—07/26/04
22
MIN
.547
MAX
.555