INTEGRAL IN74HC02A

TECHNICAL DATA
IN74HC02A
Quad 2-Input NOR Gate
The IN74HC02A is identical in pinout to the LS/ALS02. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC02AN Plastic
IN74HC02AD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
PIN 14 =VCC
PIN 7 = GND
Output
A
B
Y
L
L
H
L
H
L
H
L
L
H
H
L
1
IN74HC02A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
PD
Tstg
TL
*
Power Dissipation in Still Air, Plastic DIP
SOIC Package*
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**
Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
IN74HC02A
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
Guaranteed Limit
V
25 °C
to
-55°C
≤85
°C
≤125
°C
Unit
VIL
Maximum Low -Level
Input Voltage
VOUT=0.1 V or
VCC=0.1 V
IOUT ≤ 20 µА
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VIH
Minimum High-Level
Input Voltage
VOUT=0.1 V or
VCC=0.1 V
IOUT ≤ 20 µА
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VOL
Maximum Low-Level
Output Voltage
VIN=VIH or VIL
IOUT ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or VIL
IOUT ≤ 4.0 mA
4.5
0.26
0.33
0.4
VIN=VIH or VIL
IOUT ≤ 5.2 mA
6.0
0.26
0.33
0.4
VIN=VIH or VIL
IOUT ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
VIN=VIH or VIL
IOUT ≤ 4.0 mA
4.5
3.98
3.84
3.7
VIN=VIH or VIL
IOUT ≤ 5.2 mA
6.0
5.48
5.34
5.2
VOH
Minimum High-Level
Output Voltage
V
IIL
Maximum Low-Level
Input Leakage Current
VIL=GND
6.0
-0.1
-1.0
-1.0
µA
IIH
Maximum High-Level
Input Leakage Current
VIH=VCC
6.0
0.1
1.0
1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIL=VCC
VIH=GND
IOUT=0 µA
6.0
1.0
10
40
µA
3
IN74HC02A
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Unit
Test
Conditions
VCC
Guaranteed Limit
V
25 °C
to
-55°C
≤85°C
≤125°C
tPLH, tPHL
Maximum Propagation Delay,
Input A or B to Output Y (Figures
1 and 2)
VIL=0 V
VIH=VCC
tLH=tHL=6 ns
CL = 50 pF
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tTLH, tTHL
Maximum Output Transition
Time, Any Output (Figures 1 and
2)
VIL=0 V
VIH=VCC
tLH=tHL=6 ns
CL = 50 pF
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
10
10
10
pF
CIN
Maximum Input Capacitance
6.0
CPD
Power Dissipation Capacitance
(Per Gate) Used to determine the
no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
5.0
ТА = 25°C,VCC=5.0 V
Figure 1. Switching Waveforms
pF
22
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
4
IN74HC02A
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
Dimension, mm
8
14
B
7
1
Symbol
MIN
MAX
A
18.67
19.69
B
6.1
7.11
5.33
C
F
L
C
-T- SEATING
PLANE
N
G
M
K
J
H
D
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
A
14
8
H
B
1
G
P
7
R x 45
C
-TK
D
SEATING
PLANE
M
Symbol
MIN
MAX
A
8.55
8.75
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
G
1.27
H
5.27
J
0°
8°
K
0.1
0.25
1. Dimensions A and B do not include mold flash or protrusion.
M
0.19
0.25
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
P
5.8
6.2
R
0.25
0.5
J
0.25 (0.010) M T C M
NOTES:
F
5