IN74HCT241A OCTAL 3-STATE NONINVERTING BUFFER/LINE DRIVER/LINE RECEIVER High-Performance Silicon-Gate CMOS The IN74HCT241A is identical in pinout to the LS/ALS241. The IN74HCT241 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has noninverting outputs and two output enables. Enable A is activelow and Enable B is active-high. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION IN74HCT241AN Plastic IN74HCT241ADW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 20=VCC PIN 10 = GND Enable A L L H Output A YA L H X L H Z X = don’t care Z = high impedance 1 Inputs Enable B H H L B Outpu t YB L H X L H Z IN74HCT241A MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±20 IOUT DC Output Current, per Pin mA ±35 ICC DC Supply Current, VCC and GND Pins mA ±75 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types t r, tf Input Rise and Fall Time (Figure 1) Min 4.5 0 Max 5.5 VCC Unit V V -55 0 +125 500 °C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74HCT241A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V 25 ≤85 ≤125 °C to °C °C 55°C VIH Minimum High- VOUT= VCC-0.1 V 4.5 2.0 2.0 2.0 Level Input IOUT≤ 20 µA 5.5 2.0 2.0 2.0 Voltage VIL Maximum Low VOUT= 0.1 V 4.5 0.8 0.8 0.8 -Level Input IOUT ≤ 20 µA 5.5 0.8 0.8 0.8 Voltage VOH Minimum High- VIN= VIH 4.5 4.4 4.4 4.4 Level Output IOUT ≤ 20 µA 5.5 5.4 5.4 5.4 Voltage VIN= VIH 3.7 4.5 3.98 3.8 IOUT ≤ 6.0 mA 4 VIN VOL Maximum = VIL 4.5 0.1 0.1 0.1 Low-Level 5.5 0.1 0.1 0.1 IOUT ≤ 20 µA Output Voltage VIN= VIL 0.4 4.5 0.26 0.3 IOUT ≤ 6.0 mA 3 VIN=VCC or GND IIN Maximum 5.5 ±0.1 ±1. ±1.0 Input Leakage 0 Current Output in High-Impedance 5.5 ±0.5 ±5. ±10.0 IOZ Maximum three State State 0 VIN Leakage = VIL or VIH Current VOUT=VCC or GND VIN=VCC ICC Maximum or GND 5.5 4.0 40 160 Quiescent IOUT=0µA Supply Current (per Package) Additional VIN = 2.4 V, Any One Input ≥-55°C 25°C to ∆ICC VIN=VCC or GND, Other Quiescent 125°C Inputs Supply Current IOUT=0µA 5.5 2.9 2.4 NOTE: Total Supply Current = ICC + ∑∆ICC 3 Unit V V V V µA µA µA mA IN74HCT241A AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Unit Symbol Parameter 25 °C ≤85°C ≤125 to °C -55°C tPLH, Maximum Propagation Delay, A to YA or 23 29 35 ns tPHL B to YB (Figures 1 and 3) tPLZ, Maximum Propagation Delay, Output 30 38 45 ns tPHZ Enable to YA or YB (Figures 2 and 4) tPZH, Maximum Propagation Delay, Output 26 33 39 ns tPZL Enable to YA or YB (Figures 2 and 4) 12 15 18 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) CIN Maximum Input Capacitance 10 10 10 pF 15 15 15 pF COUT Maximum Three-State Output Capacitance (Output in High-Impedance State) CPD Power Dissipation Capacitance (Per Enable Output) Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms Typical @25°C,VCC=5.0 V 55 pF Figure 2. Switching Waveforms 4 IN74HCT241A Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/4 of the Device) 5