TECHNICAL DATA KK74HCT240A Octal 3-State Inverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS The KK74HCT240A is identical in pinout to the LS/ALS240. The KK74HCT240A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This octal inverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other busoriented systems. The device has inverting outputs and two active-low output enables. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION KK74HCT240AN P lastic KK74HCT240ADW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 20=VCC PIN 10 = GND Outputs Enable A, Enable B A,B YA,YB L L H L H L H X Z X = don’t care Z = high impedance 1 KK74HCT240A MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) Min Max Unit 4.5 5.5 V 0 VCC V -55 +125 °C 0 500 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HCT240A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V 25 °C to -55°C ≤85 °C ≤125 °C Unit VIH Minimum HighLevel Input Voltage VOUT=0.1 V ⎢IOUT⎢≤ 20 µA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low Level Input Voltage VOUT= VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum HighLevel Output Voltage VIN= VIL ⎢IOUT⎢ ≤ 20 µA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V VIN=VIL ⎢IOUT⎢ ≤ 6.0 mA 4.5 3.98 3.84 3.7 VIN=VIH ⎢IOUT⎢ ≤ 20 µA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIH ⎢IOUT⎢ ≤ 6.0 mA 4.5 0.26 0.33 0.4 VOL Maximum LowLevel Output Voltage V IIN Maximum Input Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA IOZ Maximum three State Leakage Current Output in High-Impedance State VIN = VIL or VIH VOUT=VCC or GND 5.5 ±0.5 ±5.0 ±10.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 5.5 4.0 40 160 µA ∆ICC Additional Quiescent Supply Current VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs ≥-55°C 25°C to 125°C mA 2.9 2.4 IOUT=0µA 5.5 NOTE: Total Supply Current = ICC + ∑∆ICC 3 KK74HCT240A AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) 20 25 30 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 28 35 42 ns tPZH, tPZL Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 25 31 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 12 15 18 ns Maximum Input Capacitance 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) 15 15 15 pF CIN COUT Power Dissipation Capacitance (Per Enable Output) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms Typical @25°C,VCC=5.0 V 55 pF Figure 2. Switching Waveforms 4 KK74HCT240A Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/8 of the Device) 5 KK74HCT240A N SUFFIX PLASTIC DIP (MS - 001AD) A Dimension, mm 11 20 B 1 10 Symbol MIN MAX A 24.89 26.92 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 N G K M J H D 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 013AC) A 20 11 H Dimension, mm B 1 P 10 G R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. F M Symbol MIN MAX A 12.6 13 B 7.4 7.6 C 2.35 2.65 D 0.33 0.51 F 0.4 1.27 G 1.27 H 9.53 J 0° 8° K 0.1 0.3 M 0.23 0.32 P 10 10.65 R 0.25 0.75 6