INTEL 8XC196NP

8XC196NP COMMERCIAL
CHMOS 16-BIT MICROCONTROLLER
n
n
n
n
n
n
n
n
n
n
n
n
n
25 MHz Operation at 4.5–5.5 Volts
n
1 Mbyte of Linear Address Space
Optional 4 Kbytes of ROM
1000 Bytes of Register RAM
Register-register Architecture
32 I/O Port Pins
16 Prioritized Interrupt Sources
4 External Interrupt Pins and NMI Pin
2 Flexible 16-bit Timer/Counters with
Quadrature Counting Capability
3 Pulse-width Modulator (PWM) Outputs
with High Drive Capability
Full-duplex Serial Port with Dedicated
Baud-rate Generator
Peripheral Transaction Server
n
n
n
n
n
Chip-select Unit
— 6 Chip Select Pins
— Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each
Chip Select
— Programmable Wait States (0, 1, 2,
or 3) for Each Chip Select
— Programmable Bus Width (8- or 16bit) for Each Chip Select
— Programmable Address Range for
Each Chip Select
1.12 µs 16 × 16 Unsigned
Multiplication
1.92 µs 32/16 Unsigned Division
100-pin SQFP or 100-pin QFP Package
Complete System Development
Support
High-speed CHMOS Technology
Event Processor Array (EPA) with 4
High-speed Capture/Compare Channels
The 8XC196NP is a member of Intel’s 16-bit MCS® 96 microcontroller family. The device features 1 Mbyte of
linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch
between multiplexed and demultiplexed operation. When operating at 25 MHz in demultiplexed mode, the
8XC196NP can access a 100 ns memory device with zero wait states. The 8XC196NP is available without
ROM (80C196NP) or with 4 Kbytes of ROM (83C196NP).
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such
products. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
October 1995
Order Number: 272459-005
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
16
CPU
1000
Byte
Register
File
24 Bytes
CPU SFRs
RALU
Interrupt
Controller
Peripheral
Transaction
Server
Microcode
Engine
4K Bytes
ROM (optional)
Memory Controller
with
Chip Select
Chip Select
CS5:0#
Control
Signals
Queue
8
A19:16/
EPORT3:0
16
A15:0
Timer 1
Timer 2
Event
Processor
Array
Serial
Port
Port 1
Port 2
Port 1/
EPA3:0,
Timer 1,
Timer 2
Port 2/
Hold Control,
SIO,
EXTINT1:0
Pulse
Width
Modulator
Baud
Rate
Gen
Port
3
AD15:0
Port
4
Port 3/
Port 4/
EXTINT3:2 PWM2:0
A2351-01
Figure 1. 8XC196NP Block Diagram
2
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
PROCESS INFORMATION
Table 1. Thermal Characteristics
θJA
θJC
100-pin SQFP
55°C/W
14°C/W
100-pin QFP
56°C/W
16°C/W
Package Type
This device is manufactured on P648, a CHMOS IV
process. Additional process and reliability information is available in Intel’s Components Quality
and Reliability Handbook (order number 210997).
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
will change depending on operating conditions and
the application. The Intel Packaging Handbook
(order number 240800) describes Intel’s thermal
impedance test methodology.
X
XX
8
X
X
XXXXX
XX
De
ily
ed
am
pe
tF
eS
uc
vic
od
Pr
rm
Op
ns
tio
Op
ns
in
n-
tio
ur
on
ati
ns
ry
mo
nfo
me
sI
m-
es
oc
tio
dB
an
Op
re
atu
ing
er
ag
ra
ck
og
Pr
Pr
Pa
mp
Te
A2815-01
Figure 2. The 8XC196NP Family Nomenclature
Table 2. Description of Product Nomenclature
Parameter
Temperature and Burn-in Options
Packaging Options
Options
Description
no mark
Commercial operating temperature range (0°C to 70°C)
with Intel standard burn-in.
S
SB
QFP
SQFP
Program–memory Options
0
3
No ROM
ROM
Process Information
C
CHMOS
Product Family
196NP
Device Speed
no mark
25 MHz
3
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 3. 8XC196NP Memory Map
Address
(Note 1)
Description
Notes
FF FFFFH
FF 3000H
External device (memory or I/O) connected to address/data bus
FF 2FFFH
FF 2000H
Internal ROM or external device (memory or I/O) connected to address/data bus
(determined by EA# pin)
2,9
FF 1FFFH
FF 0000H
External device (memory or I/O) connected to address/data bus
3,9
FE FFFFH
0F 0000H
Overlaid memory (reserved for future devices)
3,9
0E FFFFH
01 0000H
896 Kbytes of external device (memory or I/O) connected to address/data bus
9
00 FFFFH
00 3000H
External device (memory or I/O) connected to address/data bus
9
00 2FFFH
00 2000H
External device (memory or I/O) connected to address/data bus or remapped
internal ROM
5, 6,9
00 1FFFH
00 1FE0H
Memory-mapped peripheral special-function registers (SFRs)
4, 7,9
00 1FDFH
00 1F00H
Internal peripheral special-function registers (SFRs)
00 1EFFH
00 0400H
External device (memory or I/O) (reserved for future devices)
00 03FFH
00 0100H
Upper register file (general-purpose register RAM)
8, 10
00 00FFH
00 0018H
Lower register file (general-purpose register RAM and stack pointer)
8, 11
00 0017H
00 0000H
Lower register file (CPU SFRs)
9
4, 7, 10
6
4, 7, 8, 11
NOTES:
1. Internally, there are 24 address bits (A23:0); however, only 20 address lines (A19:0) are bonded out.
The external address space is 1 Mbyte (00000–FFFFFH).
2. The 8XC196NP resets to internal address FF2080H (FF2080H in internal ROM or F2080H in external
memory).
3. Do not locate code in addresses xF0000–xF00FFH. These addresses are reserved for the ICE in-circuit emulator. Unless otherwise noted, write 0FFH to reserved memory locations.
4. Unless otherwise noted, write 0 to reserved SFR bits.
5. These areas are mapped into internal ROM if the REMAP bit (CCB1.2) is set and EA# is at logic 1.
Otherwise, they are mapped to external memory.
6. WARNING: The contents or functions of these memory locations may change with future device revisions, in which case a program that relies on one or more of these locations may not function properly.
7. Refer to the 8XC196NP User’s Manual or 8XC196NP Quick Reference for SFR descriptions.
8. Code executed in locations 000000H to 0003FFH will be forced external.
9.
Address with indirect, indexed, or extended modes.
10. Address with indirect, indexed, or extended modes or through register windows.
11. Address with direct, indirect, indexed, or extended modes.
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RESET#
NMI
EA#
A0
A1
VCC
VSS
A2
A3
A4
A5
A6
A7
VCC
VSS
NC
NC
P3.0 / CS0#
P3.1 / CS1#
P3.2 / CS2#
P3.3 / CS3#
VSS
P3.4 / CS4#
P3.5 / CS5#
P3.6 / EXTINT2
P3.7 / EXTINT3
P1.0 / EPA0
VCC
P1.1 / EPA1
P1.2 / EPA2
P1.3 / EPA3
P1.4 / T1CLK
P1.5 / T1DIR
VCC
P1.6 / T2CLK
VSS
P1.7 / T2DIR
P4.0 / PWM0
P4.1 / PWM1
P4.2 / PWM2
P4.3
VCC
VSS
P2.0 / TXD
P2.1 / RXD
P2.2 / EXTINT0
P2.3 / BREQ#
P2.4 / EXTINT1
P2.5 / HOLD#
P2.6 / HLDA#
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VCC
AD8
VSS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
A16 / EPORT.0
A17 / EPORT.1
VCC
VSS
A18 / EPORT.2
A19 / EPORT.3
WR# / WRL#
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
SB8XC196NP
View of component as
mounted on PC board
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RD#
BHE# / WRH#
ALE
INST
READY
RPD
ONCE
VSS
VCC
VSS
A8
A9
A10
A11
A12
A13
A14
A15
NC
VSS
XTAL1
XTAL2
VSS
NC
P2.7 / CLKOUT
A2348-04
Figure 3. 8XC196NP 100-pin SQFP Package
5
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. 8XC196NP 100-pin SQFP Pin Assignment
Pin
†
6
Name
Pin
Name
Pin
Name
Pin
Name
1
RESET#
26
EXTINT3/P3.7
51
CLKOUT/P2.7
76
WR#/WRL#
2
NMI
27
EPA0/P1.0
52
NC†
77
EPORT.3/A19
3
EA#
28
VCC
53
VSS
78
EPORT.2/A18
4
A0
29
EPA1/P1.1
54
XTAL2
79
VSS
5
A1
30
EPA2/P1.2
55
XTAL1
80
VCC
6
V CC
31
EPA3/P1.3
56
VSS
81
EPORT.1/A17
7
VSS
32
T1CLK/P1.4
57
NC†
82
EPORT.0/A16
8
A2
33
T1DIR/P1.5
58
A15
83
AD15
9
A3
34
VCC
59
A14
84
AD14
10
A4
35
T2CLK/P1.6
60
A13
85
AD13
11
A5
36
VSS
61
A12
86
AD12
12
A6
37
T2DIR/P1.7
62
A11
87
AD11
13
A7
38
PWM0/P4.0
63
A10
88
AD10
14
VCC
39
PWM1/P4.1
64
A9
89
AD9
15
VSS
40
PWM2/P4.2
65
A8
90
VSS
16
NC†
41
P4.3
66
VSS
91
AD8
17
NC†
42
VCC
67
VCC
92
VCC
18
CS0#/P3.0
43
VSS
68
VSS
93
AD7
19
CS1#/P3.1
44
TXD/P2.0
69
ONCE
94
AD6
20
CS2#/P3.2
45
RXD/P2.1
70
RPD
95
AD5
21
CS3#/P3.3
46
EXTINT0/P2.2
71
READY
96
AD4
22
VSS
47
BREQ#/P2.3
72
INST
97
AD3
23
CS4#/P3.4
48
EXTINT1/P2.4
73
ALE
98
AD2
24
CS5#/P3.5
49
HOLD#/P2.5
74
BHE#/WRH#
99
AD1
25
EXTINT2/P3.6
50
HLDA#/P2.6
75
RD#
100
AD0
To be compatible with future versions of the Nx family, tie the no connection (NC) pins as follows:
Pin 57 = VSS, Pin 16 = VCC, Pin 17 = VSS (5 volts on this pin will enable a clock doubler on future
devices), and Pin 52 = VCC.
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 5. 100-pin SQFP Pin Assignment Arranged by Functional Categories
Address & Data
Name
Address & Data (cont)
Pin
Name
Input/Output
Pin
Name
Power & Ground
Pin
Name
Pin
A0
4
AD13
85
CS0#/P3.0
18
VCC
6
A1
5
AD14
84
CS1#/P3.1
19
VCC
14
A2
8
AD15
83
CS2#/P3.2
20
VCC
28
CS3#/P3.3
21
VCC
34
Bus Control & Status
CS4#/P3.4
23
VCC
42
A3
9
A4
10
Pin
CS5#/P3.5
24
VCC
67
ALE
73
EPA0/P1.0
27
VCC
80
13
BHE#/WRH#
74
EPA1/P1.1
29
VCC
92
65
BREQ#
47
EPA2/P1.2
30
VSS
7
A9
64
HOLD#
49
EPA3/P1.3
31
VSS
15
A10
63
HLDA#
50
EPORT.0
82
VSS
22
A11
62
INST
72
EPORT.1
81
VSS
36
A12
61
RD#
75
EPORT.2
78
VSS
43
A13
60
READY
71
EPORT.3
77
VSS
53
A14
59
WR#/WRL#
76
P2.2
46
VSS
56
A15
58
A16
82
A5
11
A6
12
A7
A8
Name
Processor Control
P2.3
47
VSS
66
P2.4
48
VSS
68
Pin
P2.5
49
VSS
79
51
P2.6
50
VSS
90
EA#
3
P2.7
51
EXTINT0
46
P3.6
25
99
EXTINT1
48
P3.7
26
98
EXTINT2
25
P4.3
41
AD3
97
EXTINT3
26
PWM0/P4.0
38
NC
17
AD4
96
NMI
2
PWM1/P4.1
39
NC
52
AD5
95
ONCE
69
PWM2/P4.2
40
NC
57
AD6
94
RESET#
RXD/P2.1
45
AD7
93
RPD
70
T1CLK/P1.4
32
AD8
91
XTAL1
55
T1DIR/P1.5
33
AD9
89
XTAL2
54
T2CLK/P1.6
35
AD10
88
T2DIR/P1.7
37
AD11
87
TXD/P2.0
44
AD12
86
A17
81
A18
78
CLKOUT
Name
A19
77
AD0
100
AD1
AD2
1
No Connection
Name
NC
Pin
16
7
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VCC
AD8
VSS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
A16 / EPORT.0
A17 / EPORT.1
VCC
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S8XC196NP
View of component as
mounted on PC board
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
A18 / EPORT.2
A19 / EPORT.3
WR# / WRL#
RD#
BHE# / WRH#
ALE
INST
READY
RPD
ONCE
VSS
VCC
VSS
A8
A9
A10
A11
A12
A13
A14
A15
VSS
XTAL1
XTAL2
VSS
P2.7 / CLKOUT
NC
P2.6 / HLDA#
P2.5 / HOLD#
P1.1 / EPA1
P1.2 / EPA2
P1.3 / EPA3
P1.4 / T1CLK
P1.5 / T1DIR
VCC
P1.6 / T2CLK
VSS
P1.7 / T2DIR
P4.0 / PWM0
P4.1 / PWM1
P4.2 / PWM2
P4.3
VCC
VSS
P2.0 / TXD
P2.1 / RXD
P2.2 / EXTINT0
P2.3 / BREQ#
P2.4 / EXTINT1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AD0
NC
RESET#
NMI
EA#
A0
A1
VCC
VSS
A2
A3
A4
A5
A6
A7
VCC
VSS
NC
P3.0 / CS0#
P3.1 / CS1#
P3.2 / CS2#
P3.3 / CS3#
VSS
P3.4 / CS4#
P3.5 / CS5#
P3.6 / EXTINT2
NC
P3.7 / EXTINT3
P1.0 / EPA0
VCC
A2349-03
Figure 4. 8XC196NP 100-pin QFP Package
8
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. 8XC196NP 100-pin QFP Pin Assignment
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
AD0
26
EXTINT2/P3.6
51
HOLD#/P2.5
76
RD#
2
No Connection
27
No Connection
52
HLDA#/P2.6
77
WR#/WRL#
3
RESET#
28
EXTINT3/P3.7
53
No Connection
78
EPORT.3/A19
4
NMI
29
EPA0/P1.0
54
CLKOUT/P2.7
79
EPORT.2/A18
5
EA#
30
VCC
55
VSS
80
VSS
6
A0
31
EPA1/P1.1
56
XTAL2
81
VCC
7
A1
32
EPA2/P1.2
57
XTAL1
82
EPORT.1/A17
8
V CC
33
EPA3/P1.3
58
VSS
83
EPORT.0/A16
9
VSS
34
T1CLK/P1.4
59
A15
84
AD15
10
A2
35
T1DIR/P1.5
60
A14
85
AD14
11
A3
36
VCC
61
A13
86
AD13
12
A4
37
T2CLK/P1.6
62
A12
87
AD12
13
A5
38
VSS
63
A11
88
AD11
14
A6
39
T2DIR/P1.7
64
A10
89
AD10
15
A7
40
PWM0/P4.0
65
A9
90
AD9
16
VCC
41
PWM1/P4.1
66
A8
91
VSS
17
VSS
42
PWM2/P4.2
67
VSS
92
AD8
18
No Connection
43
P4.3
68
VCC
93
VCC
19
CS0#/P3.0
44
VCC
69
VSS
94
AD7
20
CS1#/P3.1
45
VSS
70
ONCE
95
AD6
21
CS2#/P3.2
46
TXD/P2.0
71
RPD
96
AD5
22
CS3#/P3.3
47
RXD/P2.1
72
READY
97
AD4
23
VSS
48
EXTINT0/P2.2
73
INST
98
AD3
24
CS4#/P3.4
49
BREQ#/P2.3
74
ALE
99
AD2
25
CS5#/P3.5
50
EXTINT1/P2.4
75
BHE#/WRH#
100
AD1
9
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 7. 100-pin QFP Pin Assignment Arranged by Functional Categories
Address & Data
Name
A0
Address & Data (cont)
Pin
Name
Input/Output
Pin
Name
Pin
Name
Pin
VCC
8
20
VCC
16
21
VCC
30
22
VCC
36
24
VCC
44
CS5#/P3.5
25
VCC
68
EPA0/P1.0
29
VCC
81
31
VCC
93
32
VSS
9
33
VSS
17
83
VSS
23
EPORT.1
82
VSS
38
EPORT.2
79
VSS
45
72
EPORT.3
78
VSS
55
77
P2.2
48
VSS
58
6
AD13
86
CS0#/P3.0
A1
7
AD14
85
CS1#/P3.1
A2
10
AD15
84
CS2#/P3.2
A3
11
CS3#/P3.3
A4
12
Bus Control & Status
CS4#/P3.4
A5
13
Pin
A6
14
ALE
74
A7
15
BHE#/WRH#
75
EPA1/P1.1
A8
66
BREQ#
49
EPA2/P1.2
A9
65
HOLD#
51
EPA3/P1.3
A10
64
HLDA#
52
EPORT.0
A11
63
INST
73
A12
62
RD#
76
A13
61
READY
A14
60
WR#/WRL#
A15
59
A16
83
Name
Power & Ground
Processor Control
19
P2.3
49
VSS
67
P2.4
50
VSS
69
Pin
P2.5
51
VSS
80
54
P2.6
52
VSS
91
EA#
5
P2.7
54
EXTINT0
48
P3.6
26
A17
82
A18
79
CLKOUT
A19
78
AD0
1
AD1
100
EXTINT1
50
P3.7
28
AD2
99
EXTINT2
26
P4.3
43
AD3
98
EXTINT3
28
PWM0/P4.0
40
NC
18
AD4
97
NMI
4
PWM1/P4.1
41
NC
27
AD5
96
ONCE
70
PWM2/P4.2
42
NC
53
AD6
95
RESET#
RXD/P2.1
47
AD7
94
RPD
71
T1CLK/P1.4
34
AD8
92
XTAL1
57
T1DIR/P1.5
35
AD9
90
XTAL2
56
T2CLK/P1.6
37
AD10
89
T2DIR/P1.7
39
AD11
88
TXD/P2.0
46
AD12
87
10
Name
3
No Connection
Name
NC
Pin
2
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
PIN DESCRIPTIONS
Table 8. Pin Descriptions
Name
A15:0
Type
I/O
Description
System Address Bus
Multiplexed
with
—
These address lines provide address bits 0–15 during the entire
external memory cycle during both multiplexed and demultiplexed
bus modes.
A19:16
I/O
Address Lines 16–19
These address lines provide address bits 16–19 during the entire
external memory cycle, supporting extended addressing of the 1Mbyte address space.
EPORT.3:0
Internally, there are 24 address bits; however, only 20 address lines
(A19:0) are bonded out. The external address space is 1 Mbyte
(00000–FFFFFH) and the internal address space is 16 Mbytes
(000000–FFFFFFH). The 8XC196NP resets to internal address
FF2080H (FF2080H in internal ROM or F2080H in external
memory).
AD15:0
I/O
Address/Data Lines
—
The function of these pins depends on the bus size and mode.
16-bit Multiplexed Bus Mode:
AD15:0 drive address bits 0–15 during the first half of the bus cycle
and drive or receive data during the second half of the bus cycle.
8-bit Multiplexed Bus Mode:
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0
drive address bits 0–7 during the first half of the bus cycle and drive
or receive data during the second half of the bus cycle.
16-bit Demultiplexed Mode:
AD15:0 drive or receive data during the entire bus cycle.
8-bit Demultiplexed Mode:
AD7:0 drive or receive data during the entire bus cycle. AD15:8
drive the data that is currently on the high byte of the internal bus.
ALE
O
Address Latch Enable
—
This active-high output signal is asserted only during external
memory cycles. ALE signals the start of an external bus cycle and
indicates that valid address information is available on the system
address/data bus (A19:16 and AD15:0 for a multiplexed bus; A19:0
for a demultiplexed bus). ALE differs from ADV# in that it does not
remain active during the entire bus cycle.
An external latch can use this signal to demultiplex the address bits
0–15 from the address/data bus in multiplexed mode.
11
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued)
Name
BHE#
Type
O
Description
Byte High Enable
Multiplexed
with
WRH#
The chip configuration register 0 (CCR0) determines whether this
pin functions as BHE# or WRH#. CCR0.2=1 selects BHE#;
CCR0.2=0 selects WRH#.
During 16-bit bus cycles, this active-low output signal is asserted for
word reads and writes and high-byte reads and writes to external
memory. BHE# indicates that valid data is being transferred over
the upper half of the system data bus. Use BHE#, in conjunction
with A0, to determine which memory byte is being transferred over
the system bus:
BHE#
A0
Byte(s) Accessed
0
0
1
0
1
0
both bytes
high byte only
low byte only
BREQ#
O
Bus Request
This active-low output signal is asserted during a hold cycle when
the bus controller has a pending external memory cycle.
The device can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD#
is removed.
You must enable the bus-hold protocol before using this signal.
P2.3
CLKOUT
O
Clock Output
P2.7
Output of the internal clock generator. The CLKOUT frequency is ½
the internal operating frequency (FXTAL1). CLKOUT has a 50% duty
cycle.
CS5#:0
O
EA#
I
Chip-select Lines 0–5
The active-low output CSx# is asserted during an external memory
cycle when the address to be accessed is in the range programmed
for chip select x. If the external memory address is outside the
range assigned to the six chip selects, no chip-select output is
asserted and the bus configuration defaults to the CS5# values.
Immediately following reset, CS0# is automatically assigned to the
range FF2000–FF20FFH (F2000–F20FFH if external).
P3.5:0
External Access
—
This input determines whether memory accesses to specialpurpose and program memory partitions (FF2000–FF2FFFH) are
directed to internal or external memory. These accesses are
directed to internal memory if EA# is held high and to external
memory if EA# is held low. For an access to any other memory
location, the value of EA# is irrelevant.
EA# is not latched and can be switched dynamically during normal
operating mode. Be sure to thoroughly consider the issues, such as
different access times for internal and external memory, before
using this dynamic switching capability.
On devices with no internal nonvolatile memory, always connect
EA# to VSS.
12
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued)
Name
EPA3:0
Type
I/O
Description
Event Processor Array (EPA) Input/Output pins
Multiplexed
with
P1.3:0
These are the high-speed input/output pins for the EPA
capture/compare channels. For high-speed PWM applications, the
outputs of two EPA channels (either EPA0 and EPA1 or EPA2 and
EPA3) can be remapped to produce a PWM waveform on a shared
output pin.
EPORT.3:0
EXTINT0
EXTINT1
EXTINT2
EXTINT3
I/O
I
Extended Addressing Port
This is a 4-bit, bidirectional, memory-mapped I/O port. The pins are
shared with the extended address bus A19:16.
A19:16
External Interrupts
P2.2
P2.4
P3.6
P3.7
In normal operating mode, a rising edge on EXTINTx sets the
EXTINTx interrupt pending bit. EXTINTx is sampled during phase 2
(CLKOUT high). The minimum high time is one state time.
In powerdown mode, asserting the EXTINTx signal for at least 1
state time causes the device to resume normal operation. The
interrupt need not be enabled, but the pin must be configured as a
special-function input. If the EXTINTx interrupt is enabled, the CPU
executes the interrupt service routine. Otherwise, the CPU executes
the instruction that immediately follows the command that invoked
the power-saving mode.
In idle mode, asserting any enabled interrupt causes the device to
resume normal operation.
HLDA#
O
Bus Hold Acknowledge
P2.6
This active-low output indicates that the CPU has released the bus
as the result of an external device asserting HOLD#.
HOLD#
I
Bus Hold Request
P2.5
An external device uses this active-low input signal to request
control of the bus. This pin functions as HOLD# only if the pin is
configured for its special function and the bus-hold protocol is
enabled. Setting bit 7 of the window selection register enables the
bus-hold protocol.
INST
O
Instruction Fetch
—
This active-high output signal is valid only during external memory
bus cycles. When high, INST indicates that an instruction is being
fetched from external memory. The signal remains high during the
entire bus cycle of an external instruction fetch. INST is low for data
accesses, including interrupt vector fetches and chip configuration
byte reads. INST is low during internal memory fetches.
NMI
I
Nonmaskable Interrupt
—
In normal operating mode, a rising edge on NMI generates a
nonmaskable interrupt. NMI has the highest priority of all prioritized
interrupts. Assert NMI for greater than one state time to guarantee
that it is recognized.
13
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued)
Name
ONCE
Type
I
Description
On-circuit Emulation
Multiplexed
with
—
Holding ONCE high during the rising edge of RESET# places the
device into on-circuit emulation (ONCE) mode. This mode puts all
pins into a high-impedance state, thereby isolating the device from
other components in the system. The value of ONCE is latched
when the RESET# pin goes inactive. While the device is in ONCE
mode, you can debug the system using a clip-on emulator. To exit
ONCE mode, reset the device by pulling the RESET# signal low.
To prevent accidental entry into ONCE mode, connect the ONCE
pin to VSS.
P1.3:0
P1.4
P1.5
P1.6
P1.7
I/O
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
I/O
P3.5:0
P3.6
P3.7
I/O
Port 3
This is an 8-bit, bidirectional, standard I/O port.
CS5:0#
EXTINT2
EXTINT3
P4.2:0
P4.3
I/O
Port 4
This is a 4-bit, bidirectional, standard I/O port with high-current drive
capability.
PWM2:0
PWM2:0
O
Pulse Width Modulator Outputs
P4.2:0
Port 1
This is a standard, bidirectional port that is multiplexed with individually selectable special-function signals.
Port 2
This is a standard, bidirectional port that is multiplexed with individually selectable special-function signals.
EPA3:0
T1CLK
T1DIR
T2CLK
T2DIR
TXD
RXD
EXTINT0
BREQ#
EXTINT1
HOLD#
HLDA#
CLKOUT
These are PWM output pins with high-current drive capability. The
duty cycle and frequency-pulse-widths are programmable.
RD#
O
Read
Read-signal output to external memory. RD# is asserted only during
external memory reads.
—
READY
I
Ready Input
—
This active-high input signal is used to lengthen external memory
cycles for slow memory by generating wait states in addition to the
wait states that are generated internally.
When READY is high, CPU operation continues in a normal manner
with wait states inserted as programmed in the chip configuration
registers, Register 0, or the chip-select x bus control register.
READY is ignored for all internal memory accesses.
14
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued)
Name
RESET#
Type
I/O
Description
Reset
Multiplexed
with
—
A level-sensitive reset input to and open-drain system reset output
from the microcontroller. Either a falling edge on RESET# or an
internal reset turns on a pull-down transistor connected to the
RESET# pin for 16 state times. In the powerdown, standby, and idle
modes, asserting RESET# causes the chip to reset and return to
normal operating mode. After a device reset, the first instruction
fetch is from FF2080H (or F2080H in external memory). For the
80C196NP, the program and special-purpose memory locations
(FF2000–FF2FFFH) reside in external memory. For the 83C196NP,
these locations can reside either in external memory or in internal
ROM.
RPD
I
Return from Powerdown
—
Timing pin for the return-from-powerdown circuit.
If your application uses powerdown mode, connect a capacitor
between RPD and VSS if the internal oscillator is the clock source.
The capacitor causes a delay that enables the oscillator to stabilize
before the internal CPU and peripheral clocks are enabled.
The capacitor is not required if your application uses powerdown
mode and if an external clock input is the clock source.
If your application does not use powerdown mode, leave this pin
unconnected.
RXD
I/O
Receive Serial Data
P2.1
In modes 1, 2, and 3, RXD receives serial port input data. In mode
0, it functions as either an input or an open-drain output for data.
T1CLK
I
Timer 1 External Clock
P1.4
External clock for timer 1. Timer 1 increments (or decrements) on
both rising and falling edges of T1CLK. Also used in conjunction
with T1DIR for quadrature counting mode.
and
External clock for the serial I/O baud-rate generator input (program
selectable).
T2CLK
I
Timer 2 External Clock
P1.6
External clock for timer 2. Timer 2 increments (or decrements) on
both rising and falling edges of T2CLK. Also used in conjunction
with T2DIR for quadrature counting mode.
T1DIR
I
Timer 1 External Direction
P1.5
External direction (up/down) for timer 1. Timer 1 increments when
T1DIR is high and decrements when it is low. Also used in
conjunction with T1CLK for quadrature counting mode.
T2DIR
I
Timer 2 External Direction
P1.7
External direction (up/down) for timer 2. Timer 2 increments when
T2DIR is high and decrements when it is low. Also used in
conjunction with T2CLK for quadrature counting mode.
15
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. Pin Descriptions (Continued)
Name
Type
TXD
O
VCC
PWR
Description
Multiplexed
with
Transmit Serial Data
In serial I/O modes 1, 2, and 3, TXD is used to transmit serial port
data. In mode 0, it is used as the serial clock output.
P2.0
Digital Supply Voltage
—
Connect each VCC pin to the digital supply voltage.
VSS
GND
Digital Circuit Ground
—
Connect each VSS pin to ground through the lowest possible
impedance path.
WR#
O
Write
WRL#
This active-low output indicates that an external write is occurring.
This signal is asserted only during external memory writes.
The chip configuration register 0 (CCR0) determines whether this
pin functions as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0
selects WRL#.
WRH#
O
Write High
BHE#
During 16-bit bus cycles, this active-low output signal is asserted for
high-byte writes and word writes to external memory. During 8-bit
bus cycles, WRH# is asserted for all write operations.
The chip configuration register 0 (CCR0) determines whether this
pin functions as BHE# or WRH#. CCR0.2=1 selects BHE#;
CCR0.2=0 selects WRH#.
WRL#
O
Write Low
WR#
During 16-bit bus cycles, this active-low output signal is asserted for
low-byte writes and word writes. During 8-bit bus cycles, WRL# is
asserted for all write operations.
The chip configuration register 0 (CCR0) determines whether this
pin functions as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0
selects WRL#.
XTAL1
I
Input Crystal/Resonator or External Clock Input
—
Input to the on-chip oscillator and the internal clock generators. The
internal clock generators provide the peripheral clocks, CPU clock,
and CLKOUT signal. When using an external clock source instead
of the on-chip oscillator, connect the clock input to XTAL1. The
external clock signal must meet the VIH specification for XTAL1.
XTAL2
O
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when
the design uses an external clock source instead of the on-chip
oscillator.
ELECTRICAL CHARACTERISTICS
16
—
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This document contains information on
Storage Temperature .................................. –60°C to +150°C products in the design phase of development. The
Supply Voltage with Respect to VSS .............. –0.5 V to +7.0 V specifications are subject to change without notice.
Power Dissipation .......................................................... 1.5 W Do not finalize a design with this information.
Revised information will be published when the
product is available. Verify with your local Intel
TA (Ambient Temperature Under Bias)................ 0°C to +70°C sales office that you have the latest datasheet
VCC (Digital Supply Voltage) ............................. 4.5 V to 5.5 V before finalizing a design.
OPERATING CONDITIONS*
FXTAL 1 (Input frequency for VCC = 4.5–5.5 V)
(Note 1) ................................................. 8 MHz to 25 MHz
*WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
This device is static and should operate below 1 Hz, but Conditions” is not recommended and extended exposure
has been tested only down to 8 MHz.
beyond the “Operating Conditions” may affect device reliability.
NOTES:
1.
17
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
DC Characteristics
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Note 1)
Symbol
Parameter
Min
Ty
p
Max
Units
Test Conditions
ICC
VCC Supply Current
80
120
mA
XTAL1 = 25 MHz
VCC = 5.5 V
Device in Reset
IIDLE
Idle Mode Current
24
36
mA
XTAL1 = 25 MHz
VCC = 5.5 V
IPD
Powerdown Mode Current
(Note 2)
50
75
µA
VCC = 5.5 V
ILI
Input Leakage Current
(all input pins except RESET)
±10
µA
VSS < VIN < VCC
VIL
Input Low Voltage (all pins)
–0.5
0.8
V
VIH
Input High Voltage
0.2 VCC +1
VCC + 0.5
V
VIL1
Input Low Voltage XTAL1
–0.5
0.3 VCC
V
VIH1
Input High Voltage XTAL1
0.7 VCC
VCC + 0.5
V
VOL
Output Low Voltage (output
configured as complementary)
(Note 3,6)
0.3
0.45
1.5
V
V
V
IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
VOH
Output High Voltage (output
configured as complementary)
(Note 6)
V
V
V
IOH = –200 µA
IOH = –3.2 mA
IOH = –7.0 mA
VOL1
Output Low Voltage on P4.x
(output configured as complementary)
V
V
IOL = 10 mA
IOL = 15 mA
VCC – 0.3
VCC – 0.7
VCC – 1.5
0.45
0.6
NOTES:
1. Typical values are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature with VCC = 5.0 V.
2. For temperatures below 100°C, typical is 10 µA.
3. For all pins except P4.3:0, which have higher drive capability (see VOL1).
4. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which
were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3).
5. Pin capacitance is not tested. CS is based on design simulations.
6. During normal (non-transient) conditions, the following maximum current limits apply for pin groups
and individual pins:
Group
IOL(mA)
IOH(mA)
P1
P2
P3
P4
EPORT
42
42
42
45
21
42
42
42
21
21
10
18
10
10
Individual
P1, P2, P3
P4
18
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Note 1) (Continued)
Symbol
Parameter
Min
Ty
p
Max
Units
Test Conditions
0.45
V
IOL = 3 µA
V
IOH = –3 µA
VOL2
Output Low Voltage in RESET
on ALE, INST, and NMI
VOH1
Output High Voltage in RESET
(Note 4)
VOL3
Output Low Voltage in RESET
for ONCE pin
0.45
V
IOL = 30 µA
VOL4
Output Low Voltage on XTAL2
0.3
0.45
1.5
V
V
V
IOL = 100 µA
IOL = 700 µA
IOL = 3 mA
VOH2
Output High Voltage on XTAL2
V
V
V
IOH = –100 µA
IOH = –700 µA
IOH = –3 mA
VTH+ –VTH–
Hysteresis voltage width on
RESET# pin
CS
Pin Capacitance (any pin to
VSS) (Note 5)
RRST
RESET Pull-up Resistor
VCC – 0.7
VCC – 0.3
VCC – 0.7
VCC – 1.5
0.3
9
V
10
pF
95
kΩ
VCC = 5.5 V,
VIN = 4.0 V
NOTES:
1. Typical values are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature with VCC = 5.0 V.
2. For temperatures below 100°C, typical is 10 µA.
3. For all pins except P4.3:0, which have higher drive capability (see VOL1).
4. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which
were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3).
5. Pin capacitance is not tested. CS is based on design simulations.
6. During normal (non-transient) conditions, the following maximum current limits apply for pin groups
and individual pins:
Group
IOL(mA)
IOH(mA)
P1
P2
P3
P4
EPORT
42
42
42
45
21
42
42
42
21
21
10
18
10
10
Individual
P1, P2, P3
P4
19
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
ICC, IIDLE vs. Frequency
ICC, IIDLE (mA)
100
90
[email protected] = 5.0 V
80
[email protected] = 5.0 V
70
60
50
40
30
20
10
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Frequency (MHz)
A3080-01
Figure 5. ICC, IIDLE versus Frequency
20
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
AC Characteristics — Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 10. AC Characteristics, Multiplexed Bus Mode
Symbol
Parameter
VCC = 4.5 V – 5.5 V
Min
Max
Units
The 8XC196NP Will Meet These Specifications
FXTAL1
Input frequency on XTAL1
8
25
MHz
TXTAL1
Period, 1/FXTAL1
40
125
ns
TXHCH
XTAL1 High to CLKOUT High/Low
10
TCLCL
CLKOUT Cycle Time
TCHCL
CLKOUT High Period
TXTAL1 – 10
TAVRL
AD15:0 Valid to RD# Low
2TXTAL1 – 20
ns
TAVWL
AD15:0 Valid to WR# Low
2TXTAL1 – 10
ns
TWHSH
A19:16, CSx# Hold after WR# Rising Edge
TRHSH
A19:16, CSx# Hold after RD# Rising Edge
TCLLH
CLKOUT Low to ALE High
TLLCH
ALE Low to CLKOUT High
TLHLH
ALE Cycle Time
4TXTAL1
TLHLL
ALE High Period
TXTAL1 – 10
TAVLL
AD15:0 Valid to ALE Low
TXTAL1 –15
ns
TLLAX
AD15:0 Hold after ALE Low
TXTAL1 – 25
ns
TLLRL
ALE Low to RD# Low
TXTAL1 – 15
TRLCL
RD# Low to CLKOUT Low
TRLRH
RD# Low Period
TRHLH
RD# High to ALE High
TRLAZ
RD# Low to Address Float
TLLWL
ALE Low to WR# Low
TCLWL
CLKOUT Low to WR# Low
TQVWH
Data Valid before WR# High
TCHWH
CLKOUT High to WR# High
TWLWH
WR# Low Period
110
2TXTAL1
ns
ns
TXTAL1 + 10
ns
0
0
–10
10
–15
10
0
TXTAL1 + 10
ns (3)
ns
ns
10
TXTAL1 – 15
–10
ns
ns (2)
TXTAL1 + 15
5
TXTAL1 – 5
ns
ns
20
TXTAL1 – 15
–15
ns
ns (2)
TXTAL1
TXTAL1 – 5
ns
ns
ns (2)
10
ns
ns (2)
NOTES:
1. Exceeding the maximum specification causes additional wait states.
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
21
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 10. AC Characteristics, Multiplexed Bus Mode (Continued)
Symbol
Parameter
VCC = 4.5 V – 5.5 V
Min
Max
Units
The 8XC196NP Will Meet These Specifications
TWHQX
Data Hold after WR# High
TXTAL1 – 20
TWHLH
WR# High to ALE High
TXTAL1 – 12
ns
TXTAL1 + 20
ns (3)
TWHBX
BHE#, INST Hold after WR# High
TXTAL1 – 10
ns
TWHAX
AD15:8 Hold after WR# High
TXTAL1 – 10
ns (4)
TRHBX
BHE#, INST Hold after RD# High
TXTAL1 – 10
ns
TRHAX
AD15:8 Hold after RD# High
TXTAL1 – 10
ns (4)
NOTES:
1. Exceeding the maximum specification causes additional wait states.
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
Table 11. AC Characteristics, Multiplexed Bus Mode
Symbol
Parameter
VCC = 4.5 V – 5.5 V
Min
Max
Units
The External Memory System Must Meet These Specifications
TAVYV
AD15:0 Valid to READY Setup
TYLYH
Non READY Time
No Upper Limit
0
TCLYX
READY Hold after CLKOUT Low
TAVDV
AD15:0 Valid to Input Data Valid
TRLDV
TSLDV
2TXTAL1 – 50
ns
ns
TXTAL1 – 10
ns (1)
3TXTAL1 – 40
ns (2)
RD# Active to Input Data Valid
TXTAL1 – 20
ns (2)
Chip-select Low, A19:16 Valid to Data Valid
4TXTAL1 – 50
TCLDV
CLKOUT Low to Input Data Valid
TXTAL1 – 35
ns
TRHDZ
End of RD# to Input Data Float
TXTAL1 – 5
ns
TRXDX
Data Hold after RD# Inactive
0
NOTES:
1. Exceeding the maximum specification causes additional wait states.
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
22
ns
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
SYSTEM BUS TIMINGS, MULTIPLEXED BUS
TXTAL1
XTAL1
TCLCL
TCHCL
TXHCH
CLKOUT
TRLCL
TCLLH
TLLCH
TLHLH
ALE
TLHLL
TLLRL
TAVLL
TLLAX
TRLRH
TRHLH
RD#
TRHDZ
TRLDV
TRLAZ
AD15:0
(read)
Address Out
Data
TAVDV
TWHLH
TWLWH
TLLWL
WR#
TWHQX
TQVWH
AD15:0
(write)
Address Out
Data Out
Address Out
TRHBX
TWHBX
BHE#,
INST
Valid
TRHAX
TWHAX
AD15:8
Address Out
TSLDV
A19:16
CSx#
Address Out
TWHSH
TRHSH
A2844-01
Figure 6. System Bus Timing Diagram (Multiplexed Bus Mode)
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
READY TIMING, MULTIPLEXED BUS
TCLYX (max)
CLKOUT
TCLYX (min)
TAVYV
READY
TLHLH + 2TXTAL1
ALE
TRLRH + 2TXTAL1
RD#
TRLDV + 2TXTAL1
TAVDV + 2TXTAL1
AD15:0
(read)
Address Out
Data In
TWLWH + 2TXTAL1
WR#
TQVWH + 2TXTAL1
AD15:0
(write)
BHE#, INST
A19:16
CSx#
Address Out
Data Out
Valid
Extended Address Out
Valid
T0016-02
Figure 7. READY Timing Diagram (Multiplexed Bus Mode)
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
AC Characteristics — Demultiplexed Bus Mode
Test Coditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 12. AC Characteristics, Demultiplexed Bus Mode
Symbol
Parameter
VCC = 4.5 V – 5.5 V
Min
Max
Units
The 8XC196NP Will Meet These Specifications
FXTAL1
Input frequency on XTAL1
8
25
MHz
TXTAL1
Period, 1/FXTAL1
40
125
ns
TXHCH
XTAL1 High to CLKOUT High/Low
10
TCLCL
CLKOUT Cycle Time
110
2TXTAL1
ns
ns
TCHCL
CLKOUT High Period
TXTAL1 – 10
TAVRL
A19:0, CSx# Valid to RD# Low
2TXTAL1 – 30
TAVWL
A19:0, CSx# Valid to WR# Low
2TXTAL1 – 25
TCLLH
CLKOUT Low to ALE High
TLLCH
ALE Low to CLKOUT High
TLHLH
ALE Cycle Time
4TXTAL1
TLHLL
ALE High Period
TXTAL1 – 10
TAVLL
Address Valid to ALE Low
NA
ns
TLLAX
Address Hold after ALE Low
NA
ns
TLLRL
ALE Low to RD# Low
NA
TRLCH
RD# Low to CLKOUT High
TRLRH
RD# Low Period
TRHLH
RD# High to ALE High
TRLAZ
RD# Low to Address Float
TLLWL
ALE Low to WR# Low
TWLCH
WR# Low to CLKOUT High
–5
TQVWH
Data Valid before WR# High
3TXTAL1 – 37
– 15
10
TXTAL1 – 5
WR# Low Period
2TXTAL1 – 10
TXTAL1 – 20
Data Hold after WR# High
WR# High to ALE High
TWHBX
BHE#, INST Hold after WR# High
TXTAL1 + 10
– 15
TXTAL1 – 5
TXTAL1 – 10
ns
ns
ns
15
ns
TXTAL1 + 20
ns (3)
NA
ns
ns (2)
NA
CLKOUT High to WR# High
ns
ns (2)
2TXTAL1 – 10
TCHWH
TWHQX
ns
10
0
ns
ns
– 10
TWLWH
TWHLH
TXTAL1 + 10
ns
10
ns
ns (2)
5
ns
ns (2)
ns
TXTAL1 + 20
ns (3)
ns
NOTES:
1. Exceeding the maximum specification causes additional wait states.
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
3. Assuming back-to-back bus cycles.
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 12. AC Characteristics, Demultiplexed Bus Mode (Continued)
Symbol
Parameter
VCC = 4.5 V – 5.5 V
Min
Max
Units
The 8XC196NP Will Meet These Specifications
TWHAX
A19:0, CSx# Hold after WR# High
0
ns
TRHBX
BHE#, INST Hold after RD# High
TXTAL1 – 10
ns
TRHAX
A19:0, CSx# Hold after RD# High
0
ns
NOTES:
1. Exceeding the maximum specification causes additional wait states.
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
3. Assuming back-to-back bus cycles.
Table 13. AC Characteristics, Demultiplexed Bus Mode
Symbol
Parameter
VCC = 4.5 V – 5.5 V
Min
Max
Units
The External Memory System Must Meet These Specifications
TAVYV
A19:0, CSx# Valid to READY Setup
3TXTAL1 – 60
TYLYH
Non READY Time
No Upper Limit
TCLYX
READY Hold after CLKOUT Low
0
TAVDV
TRLDV
ns
ns
TXTAL1 – 10
ns (1)
A19:0, CSx# Valid to Input Data Valid
4TXTAL1 – 50
ns (2)
RD# Active to Input Data Valid
2TXTAL1 – 25
ns (2)
TCLDV
CLKOUT Low to Input Data Valid
TXTAL1 – 35
ns
TRHDZ
End of RD# to Input Data Float
TXTAL1 – 5
ns
TRXDX
Data Hold after RD# Inactive
0
NOTES:
1. Exceeding the maximum specification causes additional wait states.
2. If wait states are used, add 2TXTAL1 × n, where n = number of wait states.
26
ns
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
SYSTEM BUS TIMINGS, DEMULTIPLEXED BUS
TXTAL1
XTAL1
TCLCL
TCHCL
TXHCH
CLKOUT
TCLDV
TLLCH
TCLLH
TLHLH
ALE
TLHLL
TRLRH
TRHLH
TRLCH
RD#
TRHDZ
TRLDV
AD15:0
(read)
Valid
TAVDV
TCHWH
TWHLH
TWLWH
WR#
TWLCH
TQVWH
AD15:0
(write)
TWHQX
Valid
TRHBX
TWHBX
BHE#,
INST
Valid
TRHAX
A19:0
CSx#
Address Out
TWHAX
Address
A2845-01
Figure 8. System Bus Timing Diagram (Demultiplexed Bus Mode)
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
READY TIMING, DEMULTIPLEXED BUS
TCLYX (max)
CLKOUT
TAVYV
TCLYX (min)
READY
TLHLH + 2TXTAL1
ALE
TRLRH + 2TXTAL1
RD#
TRLDV + 2TXTAL1
TAVDV + 2TXTAL1
AD15:0
(read)
Data
TWLWH + 2TXTAL1
WR#
TQVWH + 2TXTAL1
AD15:0
(write)
BHE#, INST
Data Out
Valid
A19:0
Extended Address Out
CSx#
Valid
T0015-02
Figure 9. READY Timing Diagram (Demultiplexed Bus Mode)
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
HOLD#/HLDA# Timing
Table 14. HOLD#/HLDA# Timings
Symbol
V CC = 4.5 V – 5.5 V
Parameter
Min
Max
Units
THVCH
HOLD# Setup Time
65
TCLHAL
CLKOUT Low to HLDA# Low
–15
15
ns (1)
ns
TCLBRL
CLKOUT Low to BREQ# Low
–15
15
ns
THALAZ
HLDA# Low to Address Float
33
ns
THALBZ
HLDA# Low to BHE#, INST, RD#, WR# Weakly Driven
25
ns
TCLHAH
CLKOUT Low to HLDA# High
–25
15
ns
TCLBRH
CLKOUT Low to BREQ# High
–25
25
ns
THAHAX
HLDA# High to Address No Longer Float
–20
ns
THAHBV
HLDA# High to BHE#, INST, RD#, WR# Valid
–20
ns
NOTE:
1. To guarantee recognition at next clock.
CLKOUT
THVCH
THVCH
Hold Latency
HOLD#
TCLHAL
TCLHAH
HLDA#
TCLBRL
TCLBRH
BREQ#
THALAZ
THAHAX
A19:0, AD15:0
CSx#, BHE#,
INST, RD#, WR#
WRL#, WRH#
THALBZ
THAHBV
Weakly held inactive
TCLLH
ALE
Start of strongly driven ALE
A2460-03
Figure 10. HOLD#/HLDA# Timing Diagram
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
AC Characteristics — Serial Port, Shift Register Mode
Table 15. Serial Port Timing — Shift Register Mode
Symbol
VCC = 4.5 V – 5.5 V
Parameter
Min
Units
Max
Serial Port Clock period
(SP_BAUD ≥ x002H)
(SP_BAUD = x001H) (Note 1)
6TXTAL1
4TXTAL1
ns
ns
TQVXH
Output data setup to clock high
3TXTAL1
ns
TXHQX
Output data hold after clock high
TXHQV
Next output data valid after
clock high
TDVXH
Input data setup to clock high
2TXTAL1 + 200
TXHDX
Input data hold after clock high
0
TXHQZ
Last clock high to output float
TXLXL
2TXTAL1 – 50
ns
2TXTAL1 + 50
ns
ns
ns
5TXTAL1
ns
NOTE:
1. The minimum baud-rate register (SP_BAUD) value for receive is x002H and the minimum baud-rate
register value for transmit is x001H.
TXLXL
TXD
TXHQV
TXLXH
RXD
(Out)
0
1
2
Valid
4
3
TDVXH
RXD
(In)
TXHQZ
TXHQX
TQVXH
7
6
5
TXHDX
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A2080-02
Figure 11. Serial Port Waveform — Shift Register Mode
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
External Clock Drive
Table 16. External Clock Drive
Symbol
Parameter
Min
Max
Units
1/TXLXL
Input frequency
8
25
MHz
TXLXL
Period (TXTAL1)
40
125
ns
TXHXX
High Time
0.35TXTAL1
0.65TXTAL1
ns
TXLXX
Low Time
0.35TXTAL1
0.65TXTAL1
ns
TXLXH
Rise Time
10
ns
TXHXL
Fall Time
10
ns
TXHXX
TXHXL
TXLXH
0.7 VCC + 0.5 V
0.7 VCC + 0.5 V
T
XLXX
0.3 VCC – 0.5 V
0.3 VCC – 0.5 V
T
XLXL
A2119-02
Figure 12. External Clock Drive Waveforms
3.5 V
0.45 V
2.0 V
0.8 V
Test Points
2.0 V
0.8 V
AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for
a logic "0". Timing measurements are made at 2.0 V for a logic
"1" and 0.8 V for a logic "0".
A2120-02
Figure 13. AC Testing Output Waveforms During 5.0 Volt Testing
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
VLOAD + 0.15 V
VOH – 0.15 V
Timing Reference
Points
VLOAD
VOL + 0.15 V
VLOAD – 0.15 V
For timing purposes, a port pin is no longer floating when a
150 mV change from load voltage occurs and begins to float
when a 150 mV change from the loading VOH/VOL level occurs
with IOL/IOH ≤15 mA.
A2121-01
Figure 14. Float Waveforms During 5.0 Volt Testing
EXPLANATION OF AC SYMBOLS
Each AC timing symbol is two pairs of letters prefixed by “T” for time. The characters in a pair indicate a signal
and its condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
Signals:
H — High
A — Address
L — ALE/ADV#
L — Low
AD — Address/Data Bus for
Multiplexed Bus Mode
BR — BREQ#
V — Valid
B — BHE#
R — RD#
X — No Longer Valid
C — CLKOUT
W — WR#/WRH#/WRL#
Z — Floating
32
D — DATA
X — XTAL1
G — Buswidth
Y — READY
H — HOLD#
Q — Data Out
HA — HLDA#
S — Chip Select
8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
8XC196NP ERRATA
4.
Change identifiers have been used on embedded
products since 1990. The change identifier is the
last character in the FPO number. The FPO number
is typically a nine character number located on the
second line of the topside package mark. The
following errata listing is applicable to the B–step
(denoted by a “B” or “C” at the end of the topside
tracking number):
1.
Any jump, conditional jump, or call instruction
located within six bytes of the top of a page,
i.e., 0FFFA–0FFFFH, may cause a jump to the
wrong page. To ensure this problem does not
occur, place at least six NOPs at the top of
each page.
The following errata listing is applicable to the A–
step (denoted by an “A” at the end of the topside
tracking number):
1.
Any jump, conditional jump, or call instruction
located within six bytes of the top of a page,
i.e., 0FFFA–0FFFFH, may cause a jump to the
wrong page. To ensure this problem does not
occur, place at least six NOPs at the top of
each page.
2.
The illegal opcode interrupt vector is not taken
when an illegal opcode is encountered. A
branch to an unknown location occurs.
3.
(1-Mbyte mode only.) If an interrupt is aborted,
intentionally or unintentionally, an undesired
branch to the lowest priority interrupt vector
(FF2000H) may occur even if the lowest
priority interrupt is not enabled. This may occur
if any bit in the INT_MASK, INT_MASK1,
INT_PEND, or INT_PEND1 register is cleared
after the corresponding INT_PEND or
INT_PEND1 bit is set.
(1-Mbyte mode only.) If a standard interrupt
occurs at approximately the same time (this
time is code dependent and therefore cannot
be stated as an exact number of state times)
as a PTS serviced interrupt, the PTS interrupt
may be processed as a standard interrupt. The
standard interrupt service routine for a PTS
serviced interrupt (End-of-PTS) is typically
used to modify the PTS control block and reenable the PTS by setting the corresponding
bit in the PTSSEL register. When this anomaly
occurs, the End-of-PTS service routine will
execute regardless of the value in
PTSCOUNT. As a result, an undetermined
number of PTS cycles will not occur. This
applies to all PTS interrupts.
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a “B” at the
end of the topside tracking number. Data sheets are
changed as new device information becomes
available. Verify with your local Intel sales office that
you have the latest version before finalizing a
design or ordering devices.
The following are important changes to the 272459005 datasheet:
1.
2.
3.
4.
5.
6.
Revised Tables 8 through 15 and Figures 5, 6,
7, and 13 to reflect new or changed information.
Added Table 3 and Figure 9.
The input frequency on XTAL1, formerly called
FOSC, is now denoted by FXTAL1.
The AC characteristics tables have been
divided into the following: the timing specifications met by the device, and the timing specifications that must be met by the external
memory system.
Maximum IOL and IOH specifications added to
the DC characteristics tables.
AC timings TAVWL and TAVRL added to the AC
characteristics–multiplexed bus mode tables.
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
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8XC196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
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