STMICROELECTRONICS ST10R172LT6

ST10R172L
16-BIT LOW VOLTAGE ROMLESS MCU
PRODUCT PREVIEW
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High Performance 16-bit CPU
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OSC
WDT
Programmable external bus characteristics
for different address ranges
8-bit or 16-bit external data bus
Multiplexed or demultiplexed external
address/data buses
Five programmable chip-select signals
Hold and hold-acknowledge bus arbitration
support
One Channel PWM Unit
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Fail Safe Protection
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8-channel interrupt-driven single-cycle data
transfer facilities via peripheral event
controller (PEC)
16-priority-level interrupt system with 17
sources, sample-rate down to 40 ns
Timers
P.0
XSSP
Interrupt Controller
&PEC
ASC
GPT1/2
P.3
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P.5
PWM
P.7
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Two multi-functional general purpose timer
units with 5 timers
Clock Generation via on-chip PLL, or via
direct or prescaled clock input
Synchronous/asynchronous
High-speed-synchronous serial port SSP
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Up to 77 general purpose I/O lines
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No bootstrap loader
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Electrical Characteristics
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5V Tolerant I/Os
5V Fail-Safe Inputs (Port 5)
Power: 3.3 Volt +/-0.3V
Idle and power down modes
Support
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Po.2
Serial Channels
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Programmable watchdog timer
Oscillator Watchdog
Interrupt
P.1
ST10 CORE
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P.4
DPRAM
1KByte on-chip RAM
Up to 16 MBytes linear address space for
code and data (1 MByte with SSP used)
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P.6
PLL
External Memory Interface
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Dedicated
pins
Memory Organisation
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CPU Frequency: 0 to 50 MHz
40ns instruction cycle time at 50-MHz CPU
clock
4-stage pipeline
Register-based design with multiple
variable register banks
Enhanced boolean bit manipulation
facilities
Additional instructions to support HLL and
operating systems
Single-cycle context switching support
1024 bytes on-Chip special function
register area
C-compilers, macro-assembler packages,
emulators, evaluation boards, HLLdebuggers, simulators, logic analyser
disassemblers, programming boards
Package
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100-Pin Thin Quad Flat Pack (TQFP)
Rev. 1.1
April 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
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1
Table of Contents
1 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 MEMORY MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 INTERRUPT AND TRAP FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 INTERRUPT SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 HARDWARE TRAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 PARALLEL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 EXTERNAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 PWM MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 GENERAL PURPOSE TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10 SERIAL CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12 SYSTEM RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13 POWER REDUCTION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14 SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.2 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
15.3 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
15.3.1 Cpu Clock Generation Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
15.3.2 Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
15.3.3 Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
. . . . 43
15.3.4 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Table of Contents
15.3.5 CLKOUT and READY/READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15.3.6 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15.3.7 External Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
15.3.8 Synchronous Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
16 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
17 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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P5.13/T5IN
P5.14/T4EUD
P5.15/T2EUD
VSS
XTAL1
XTAL2
VDD
P3.0
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3EUD
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
P3.8
P3.9
P3.10/TxD0
P3.11/RxD0
P3.12/BHE/WRH
P3.13
P3.15/CLKOUT
P4.0/A16
P4.1/A17
P4.2/A18
100999897969594939291908988878685848382818079787776
ST10R172L
RPD
26272829303132333435363738394041424344454647484950
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
VDD
VSS
Figure 1 TQFP-100 pin configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN DESCRIPTION
ST10R172L - PIN DESCRIPTION
1
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1
P5.12/T6IN
P5.11/T5EUD
P5.10/T6EUD
P7.3/POUT3
P7.2
P7.1
P7.0
P2.11/EX3IN
P2.10/EX2IN
P2.9/EX1IN
P2.8/EX0IN
P6.7/BREQ
P6.6/HLDA
P6.5/HOLD
P6.4/CS4
P6.3/CS3
P6.2/CS2
P6.1/CS1
P6.0/CS0
NMI
RSTOUT
RSTIN
VDD
VSS
P1H.7/A15
P4.3/A19
VSS
VDD
P4.4/A20/SSPCE1
P4.5/A21/SSPCE0
P4.6/A22/SSPDAT
P4.7/A23/SSPCLK
RD
WR/WRL
READY/READY
ALE
EA
VDD
VSS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P1H.6/A14
P1H.5/A13
P1H.4/A12
P1H.3/A11
P1H.2/A10
VSS
VDD
P1H.1/A9
P1H.0/A8
P1L.7/A7
P1L.6/A6
P1L.5/A5
P1L.4/A4
P1L.3/A3
P1L.2/A2
P1L.1/A1
P1L.0/A0
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
P0H.2/AD10
P0H.1/AD9
P0H.0/AD8
Pin Number
(TQFP)
Input (I)
Output (O)
Kind1)
P5.10
98-100
I
5S
–P5.15
1- 3
I
5S
6-bit input-only port with Schmitt-Trigger characteristics.
Port 5 pins also serve as timer inputs:
98
I
5S
P5.10
T6EUD
GPT2 Timer T6 Ext.Up/Down
Ctrl.Input
99
I
5S
P5.11
T5EUD
GPT2 Timer T5 Ext.Up/Down
Ctrl.Input
100
I
5S
P5.12
T6IN
GPT2 Timer T6 Count Input
1
I
5S
P5.13
T5IN
GPT2 Timer T5 Count Input
2
I
5S
P5.14
T4EUD
GPT1 Timer T4 Ext.Up/Down
Ctrl.Input
3
I
5S
P5.15
T2EUD
GPT1 Timer T2 Ext.Up/Down
Ctrl.Input
XTAL1
5
I
3T
XTAL1:
Input to the oscillator amplifier and internal clock
generator
XTAL2
6
O
3T
XTAL2:
Output of the oscillator amplifier circuit.
Function
Symbol
ST10R172L - PIN DESCRIPTION
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Observe minimum and maximum high/low and
rise/fall times specified in the AC Characteristics.
Table 1 Pin definitions
5/68
1
Kind1)
8-21
I/O
5T
P3.15
22
I/O
5T
A 15-bit (P3.14 is missing) bidirectional I/O port. Port 3 is bitwise programmable for input or output via direction bits. For a
pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The following pins have alternate
functions:
9
O
5T
P3.1
T6OUT
GPT2 Timer T6 toggle latch output
10
I
5T
P3.2
CAPIN
GPT2 Register CAPREL capture
input
11
O
5T
P3.3
T3OUT
GPT1 Timer T3 toggle latch output
12
I
5T
P3.4
T3EUD
GPT1 Timer T3 ext.up/down ctrl.input
13
I
5T
P3.5
T4IN
GPT1 Timer T4 input for count/gate/
reload/capture
14
I
5T
P3.6
T3IN
GPT1 Timer T3 count/gate input
15
I
5T
P3.7
T2IN
GPT1 Timer T2 input for count/gate/
reload/capture
18
O
5T
P3.10
TxD0
ASC0 clock/data output (asyn./syn.)
19
I/O
5T
P3.11
RxD0
ASC0 data input (asyn.) or I/O (syn.)
20
O
5T
P3.12
BHE
Ext. Memory High Byte Enable Signal
O
5T
WRH
Ext. Memory High Byte Write Strobe
O
5T
CLKOUT
System clock output (=CPU clock)
22
Function
Input (I)
Output (O)
P3.0 –
P3.13
Symbol
Pin Number
(TQFP)
ST10R172L - PIN DESCRIPTION
P3.15
Table 1 Pin definitions
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1
Pin Number
(TQFP)
Input (I)
Output (O)
Kind1)
P4.0–
P4.7
23-26
29-32-
I/O
5T
An 8-bit bidirectional I/O port. Port 8 is bit-wise programmable
for input or output via direction bits. For a pin configured as
input, the output driver is put into high-impedance state.
Port 4 can be used to output the segment address lines for
external bus configuration.
23
O
5T
P4.0
A16
Least Significant Segment Addr. Line
...
...
...
...
...
...
26
O
5T
P4.3
A19
Segment Address Line
29
O
5T
P4.4
A20
Segment Address Line
O
5T
SSPCE1
Chip Enable Line 1
O
5T
A21
Segment Address Line
O
5T
SSPCE0
SSPChip Enable Line 0
O
5T
A22
Segment Address Line
I/O
5T
SSPDAT
SSP Data Input/Output Line
O
5T
A23
Most Significant Segment Addr. Line
O
5T
SSPCLK
SSP Clock Output Line
30
31
32
Function
Symbol
ST10R172L - PIN DESCRIPTION
P4.5
P4.6
P4.7
RD
33
O
5T
External Memory Read Strobe. RD is activated for every external instruction or data read access.
WR/
WRL
34
O
5T
External Memory Write Strobe. In WR-mode, this pin is activated for every external data write access. In WRL-mode, this
pin is activated for low byte data write accesses on a 16-bit
bus, and for every data write access on an 8-bit bus.
See WRCFG in the SYSCON register for mode selection.
READY/
READY
35
I
5T
Ready Input. Active level is programmable. When the Ready
function is enabled, the selected inactive level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to the selected
active level. Polarity is programmable.
Table 1 Pin definitions
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1
Pin Number
(TQFP)
Input (I)
Output (O)
Kind1)
ALE
36
O
5T
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the multiplexed bus modes.
EA
37
I
5T
External Access Enable pin. Low level at this pin during and
after reset forces the ST10R172L to begin instruction execution out of external memory. A high level forces execution out
of the internal ROM. The ST10R172L must have this pin tied
to ‘0’.
I/O
5T
PORT0 has two 8-bit bidirectional I/O ports P0L and P0H. It is
bit-wise programmable for input or output via direction bits. For
a pin configured as input, the output driver is put into highimpedance state.
For external bus configuration, PORT0 acts as address (A)
and address/data (AD) bus in multiplexed bus modes and as
the data (D) bus in demultiplexed bus modes.
PORT0:
P0L.0–
P0L.7,
41 - 48
P0H.0 P0H.7
51 - 58
Function
Symbol
ST10R172L - PIN DESCRIPTION
Demultiplexed bus modes
Data Path Width:
8-bit
16-bit
P0L.0 – P0L.7:
D0 – D7
D0 - D7
P0H.0 – P0H.7:
I/O
D8 - D15
Multiplexed bus modes
Data Path Width:
PORT1:
I/O
P1L.0–
P1L.7,
59- 66
P1H.0 P1H.7
67, 68
71-76
5T
8-bit
P0L.0 – P0L.7:
AD0 – AD7
AD0 - AD7
P0H.0 – P0H.7:
A8 – A15
AD8 – AD15
PORT1 has two 8-bit bidirectional I/O ports P1L and P1H. It is
bit-wise programmable for input or output via direction bits. For
a pin configured as input, the output driver is put into highimpedance state. PORT1 acts as a 16-bit address bus (A) in
demultiplexed bus modes and also after switching from a
demultiplexed bus mode to a multiplexed bus mode.
Table 1 Pin definitions
8/68
1
16-bit
Pin Number
(TQFP)
Input (I)
Output (O)
Kind1)
RSTIN
79
I
5T
Reset Input with Schmitt-Trigger characteristics. Resets the
device when a low level is applied for a specified duration while
the oscillator is running. An internal pullup resistor enables
power-on reset using only a capacitor connected to VSS. With
a bonding option, the RSTIN pin can also be pulled-down for
512 internal clock cycles for hardware, software or watchdog
timer triggered resets
RSTOUT
80
O
5T
Internal Reset Indication Output. This pin is set to a low level
when the part is executes hardware-, software- or watchdog
timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed.
NMI
81
I
5S
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine.
If it is not used, NMI should be pulled high externally.
P6.0P6.7
82-89
I/O
5T
An 8-bit bidirectional I/O port. Port 6 is bit-wise programmable
for input or output via direction bits. For a pin configured as
input, the output driver is put into high-impedance state. Port 6
outputs can be configured as push/pull or open drain drivers.
Function
Symbol
ST10R172L - PIN DESCRIPTION
The following Port 6 pins have alternate functions:
82
O
5T
P6.0
CS0
Chip Select 0 Output
...
...
...
...
...
...
86
O
5T
P6.4
CS4
Chip Select 4 Output
87
I
5T
P6.5
HOLD
External Master Hold Request Input
(Master mode: O, Slave mode: I)
88
I/O
5T
P6.6
HLDA
Hold Acknowledge Output
89
O
5T
P6.7
BREQ
Bus Request Output
Table 1 Pin definitions
9/68
1
Kind1)
90 - 93
I/O
5T
Function
Input (I)
Output (O)
P2.8 –
P2.11
Pin Number
(TQFP)
Symbol
ST10R172L - PIN DESCRIPTION
Port 2 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as
input, the output driver is put into high-impedance state. Port 2
outputs can be configured as push/pull or open drain drivers.
The following Port 2 pins have alternate functions:
P7.0 –
P7.3
90
I
5T
P2.8
EX0IN
Fast External Interrupt 0 Input
...
...
...
...
...
...
93
I
5T
P2.11
EX3IN
Fast External Interrupt 3 Input
94 - 97
I/O
5T
Port 7 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as
input, the output driver is put into high-impedance state. Port
7outputs can be configured as push/pull or open drain drivers.
The following Port 7 pins have alternate functions:
97
O
5T
P7.3
POUT3
PWM (Channel 3) Output
RPD
40
I/O
5T
Input timing pin for the return from powerdown circuit and
power-up asynchronous reset.
VDD
7, 28,
38, 49,
69, 78
-
PO
Digital supply voltage.
VSS
4, 27,
39, 50,
70, 77
-
PO
Digital ground.
Table 1 Pin definitions
1) The following I/O kinds are used. Refer to ELECTRICAL CHARACTERISTICS on
page 31 for a detailed description.
PO: Power pin
3T: 3 V tolerant pin (voltage max. respect to Vss is -0.5 to VDD + 0.5)
5V: 5 V tolerant pin (voltage max. respect to Vss is -0.5 to 5.5 only if chip is powered)
5S: 5 V tolerant and fail-safe pin (-0.5-5.5 max. voltage w.r.t. Vss even if chip is not powered).
10/68
1
ST10R172L - FUNCTIONAL DESCRIPTION
2
FUNCTIONAL DESCRIPTION
ST10R172L architecture combines the advantages of both RISC and CISC processors with
an advanced peripheral subsystem. The following block diagram overviews the different onchip components and the internal bus structure.
I/O
CS(4:0)
HOLD
HLDA
BREQ
I/O
A(23:16),
SSPCLK,
SSPDAT,
SSPCE(1:0)
dedicated
pins
Port 6
8-bit
Port 4
8-bit
OSC
WDT
EA, ALE, RD,
WR/WRL,
READY, NMI,
RSTIN,
RSTOUT
I/O
I/O, D(7:0)
D(15:8), D(7:0)
I/O
A(15:8), AD(7:0)
A(15:0) AD(15:8), AD(7:0)
Port 1
2x8-bit
Port 0
2x8-bit
XTAL1
XSSP
4-bit
XTAL2
PLL
1KByte
ST10 CORE
DPRAM
Interrupt Controller
& PEC
ASC
Port 3
15-bit
I/O
CLKOUT,
BHE/WRH, RxD0,
TxD0, T2IN, T3IN,
T4IN,
T3EUD,
T3OUT, CAPIN,
T6OUT
GPT1/2
PWM
Port 7
4-bit
Port 2
4-bit
I/O
POUT3
I/O
EXIN(3:0)
Port 5
6-bit
I
T2EUD,
T4EUD, T5IN,
T6IN, T5EUD,
T6EUD
Figure 2 Block diagram
11/68
1
ST10R172L - MEMORY MAPPING
3
MEMORY MAPPING
The ST10R172L is a ROMless device, the internal RAM space is 1 KByte. The RAM address
space is used for variables, register banks, the system stack, the PEC pointers (in 00’FCE0h
- 00’FCFFh) and the bit-addressable space (in 00’FD00h - 00’FDFFh).
RAM/SFR
00’EFFFh
256 Byte
00’EF00h
00’FFFFh
00’F000h
XSSP
Data Page 3
00’FFFFh
00’FF3Fh
00’FF20h
SFR Area
(reserved)
00’FE3Fh
00’FE20h
00’FE00h
External
memory
00’F000h
RAM
1K-Byte
Data Page 2
00’FA00h
00’8000h
Data Page 1
internal
memory
Block 1
00’4000h
00’F200h
00’FF3Fh
00’FF20h
00’1FFFh
Data Page 0
8K-byte
Block 0
ESFR Area
(reserved)
00’F03Fh
00’F020h
00’0000h
00’0000h
System Segment 0
64 K-Byte
Figure 3 Memory map
12/68
1
00’F000h
DPRAM / SFR Area
4 K-Byte
ST10R172L - CENTRAL PROCESSING UNIT
4
CENTRAL PROCESSING UNIT
The main core of the CPU contains a 4-stage instruction pipeline, a separate multiply and
divide unit, a bit-mask generator and a barrel shifter. Most instructions can be executed in one
machine cycle requiring 40ns at 50MHz CPU clock.
The CPU includes an actual register context consisting of 16 wordwide GPRs physically
located in the on-chip RAM area. A Context Pointer (CP) register determines the base
address of the active register bank to be accessed by the CPU. The number of register banks
is only restricted by the available internal RAM space. For easy parameter passing, one
register bank may overlap others.
A system stack of up to 1024 bytes is provided as a storage for temporary data. The system
stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer
(SP) register. Two separate SFRs, STKOV and STKUN, are compared against the stack
pointer value during each stack access to detect stack overflow or underflow.
CPU
16
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr
Instr. Reg
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
Data Pg. Ptrs
MDH
MDL
Mul./Div.-HW
Bit-Mask Gen.
ALU
R15
Internal
General
RAM
Purpose
1KByte
Registers
R15
16-Bit
Barrel-Shift
Context Ptr
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Code Seg. Ptr.
R0
IDX0
QX0
QR0
IDX1
QX1
QR1
16
R0
Figure 4 CPU block diagram
13/68
1
ST10R172L - INTERRUPT AND TRAP FUNCTIONS
5
INTERRUPT AND TRAP FUNCTIONS
The architecture of the ST10R172L supports several mechanisms for fast and flexible
response to the service requests that can be generated from various sources, internal or
external to the microcontroller. Any of these interrupt requests can be programmed to be
serviced, either by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In a standard interrupt service, program execution is suspended and a branch to the interrupt
service routine is performed. For a PEC service, just one cycle is ‘stolen’ from the current
CPU activity. A PEC service is a single, byte or word data transfer between any two memory
locations, with an additional increment of either the PEC source or the destination pointer. An
individual PEC transfer counter is decremented for each PEC service, except in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is performed
to the corresponding source-related vector location. PEC services are very well suited, for
example, to the transmission or reception of blocks of data. The ST10R172L has 8 PEC
channels, each of which offers fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag
and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related
register, each source can be programmed to one of sixteen interrupt priority levels. Once
having been accepted by the CPU, an interrupt service can only be interrupted by a higher
priority service request. For standard interrupt processing, each of the possible interrupt
sources has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs, feature programmable edge detection (rising edge,
falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
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1
ST10R172L - INTERRUPT AND TRAP FUNCTIONS
5.1
Interrupt Sources
Source of Interrupt or PEC
Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
External Interrupt 0
CC8IR
CC8IE
CC8INT
60h
18h
External Interrupt 1
CC9IR
CC9IE
CC9INT
64h
19h
External Interrupt 2
CC10IR
CC10IE
CC10INT
68h
1Ah
External Interrupt 3
CC11IR
CC11IE
CC11INT
6Ch
1Bh
GPT1 Timer 2
T2IR
T2IE
T2INT
88h
22h
GPT1 Timer 3
T3IR
T3IE
T3INT
8Ch
23h
GPT1 Timer 4
T4IR
T4IE
T4INT
90h
24h
GPT2 Timer 5
T5IR
T5IE
T5INT
94h
25h
GPT2 Timer 6
T6IR
T6IE
T6INT
98h
26h
GPT2 CAPREL Register
CRIR
CRIE
CRINT
9Ch
27h
ASC0 Transmit
S0TIR
S0TIE
S0TINT
A8h
2Ah
ASC0 Transmit Buffer
S0TBIR
S0TBIE
S0TBINT
11Ch
47h
ASC0 Receive
S0RIR
S0RIE
S0RINT
ACh
2Bh
ASC0 Error
S0EIR
S0EIE
S0EINT
B0h
2Ch
PWM Channel 3
PWMIR
PWMIE
PWMINT
FCh
3Fh
SSP Interrupt
XP1IR
XP1IE
XP1INT
104h
41h
PLL Unlock
XP3IR
XP3IE
XP3INT
10Ch
43h
Table 2 List of possible interrupt sources, flags, vector and trap numbers
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ST10R172L - INTERRUPT AND TRAP FUNCTIONS
5.2
Hardware traps
Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware
traps cause immediate non-maskable system reaction similar to a standard interrupt service
(branching to a dedicated vector table location). The occurrence of a hardware trap is
additionally signified by an individual bit in the trap flag register (TFR). Except when another
higher prioritized trap service is in progress, a hardware trap will interrupt any actual program
execution. In turn, hardware trap services can not normally be interrupted by standard or PEC
interrupts. The following table shows all of the possible exceptions or error conditions that can
arise during run-time:
Trap Vector
Vector
Location
Trap
Number
Trap
Priority
Hardware Reset
RESET
00’0000h
00h
III
Software Reset
RESET
00’0000h
00h
III
Watchdog Timer Overflow
RESET
00’0000h
00h
III
Exception Condition
Trap Flag
Reset Functions:
Class A Hardware Traps:
Non-Maskable Interrupt
NMI
NMITRAP
00’0008h
02h
II
Stack Overflow
STKOF
STOTRAP
00’0010h
04h
II
Stack Underflow
STKUF
STUTRAP
00’0018h
06h
II
Undefined opcode
UNDOPC
BTRAP
00’0028h
0Ah
I
Protected instruction fault
PRTFLT
BTRAP
00’0028h
0Ah
I
Illegal word operand access ILLOPA
BTRAP
00’0028h
0Ah
I
Illegal instruction access
ILLINA
BTRAP
00’0028h
0Ah
I
Illegal external bus access
ILLBUS
BTRAP
00’0028h
0Ah
I
[2Ch – 3Ch]
[0Bh – 0Fh]
Class B Hardware Traps:
Reserved
Software Traps
TRAP Instruction
Any [00’0000h Any
Current
– 00’01FCh]
[00h – 7Fh] CPU
steps of 4h
Priority
Table 3 Exceptions or error conditions
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1
ST10R172L - PARALLEL PORTS
6
PARALLEL PORTS
The ST10R172L provides up to 77 I/O lines organized into 7 input/output ports and one input
port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs by direction registers. The I/O ports are true bidirectional
ports which are switched to high impedance state when configured as inputs. The output
drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain
operation by control registers. During the internal reset, all port pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with them.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems
where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides
optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes
alternate functions of timers, serial interfaces, the optional bus control signal BHE and the
system clock output (CLKOUT). Port 5 is used for timer control signals. Port 2 lines can be
used as fast external interrupt lines. Port 7 includes alternate function for the PWM signal. All
port lines that are not used for these alternate functions may be used as general purpose I/O
lines.
7
EXTERNAL BUS CONTROLLER
All external memory accesses are performed by the on-chip External Bus Controller which
can be programmed either to single chip mode when no external memory is required, or to the
following external memory access modes:
16-bit data, demultiplexed
16-/18-/20-/24-bit addresses
16-bit data, multiplexed
16-/18-/20-/24-bit addresses
8-bit data, multiplexed
16-/18-/20-/24-bit addresses
8-bit data, demultiplexed
16-/18-/20-/24-bit addresses
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on
PORT0/P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0
for input/output.
Memory cycle time, memory tri-state time, length of ALE and read write delay are
programmable so that a wide range of different memory types and external peripherals can be
used. Up to 4 independent address windows can be defined (via ADDRSELx / BUSCONx
register pairs) to access different resources with different bus characteristics. These address
windows are arranged hierarchically where BUSCON4 overrides BUSCON3 etc. All accesses
to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5
external CS signals (4 windows plus default) can be generated to reduce external glue logic.
Access to very slow memories is supported by the READY function.
A HOLD/HLDA protocol is available for bus arbitration so that external resources can be
shared with other bus masters. In slave mode, the slave controller can be connected to another master controller without glue logic. For applications which require less than 16 MBytes
17/68
1
ST10R172L - PWM MODULE
of external memory space, the address space can be restricted to 1 MByte, 256 KByte or to 64
KByte.
8
PWM MODULE
A 1-channel Pulse Width Modulation (PWM) Module operates on channel 3. The pulse width
modulation module can generate up to four PWM output signals using edge-aligned or centrealigned PWM. In addition, the PWM module can generate PWM burst signals and single shot
outputs. The table below shows the PWM frequencies for different resolutions. The level of
the output signals is selectable and the PWM module can generate interrupt requests.
Mode 0
edge aligned
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CPU clock/1
20ns
195.3 KHz
48.83KHz
12.21KHz
3.052KHz
762.9Hz
CPU clock/64
1.28ns
3.052KHz
762.9Hz
190.7Hz
47.68Hz
11.92Hz
Mode 1
center aligned
Resolution
8-bit
10-bit
12-bit
14-bit
16-bit
CPU clock/1
20ns
97.66KHz
24.41KHz
6.104KHz
1.525KHz
381.5Hz
CPU clock/64
1.28ns
1.525Hz
381.5 Hz
95.37Hz
23.84Hz
0Hz
Table 4 PWM unit frequencies and resolution at 50MHz CPU clock
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1
ST10R172L - GENERAL PURPOSE TIMERS
9
GENERAL PURPOSE TIMERS
The GPTs are flexible multifunctional timer/counters used for time-related tasks such as event
timing and counting, pulse width and duty cycle measurements, pulse generation or pulse
multiplication. The GPT unit contains five 16-bit timers, organized in two separate modules,
GPT1 and GPT2. Each timer in each module may operate independently in a number of
different modes, or may be concatenated with another timer of the same module.
9.1
GPT1
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one
of four basic modes of operation: timer, gated timer, counter mode and incremental
interface mode. In timer mode, the input clock for a timer is derived from the CPU clock,
divided by a programmable prescaler. In counter mode, the timer is clocked in reference to
external events. Pulse width or duty cycle measurement is supported in gated timer mode
where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For
these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. Table 5 GPT1 timer input frequencies, resolution and periods lists the timer input
frequencies, resolution and periods for each pre-scaler option at 50MHz CPU clock. This also
applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and
Gated Timer Mode
The count direction (up/down) for each timer is programmable by software or may additionally
be altered dynamically by an external signal on a port pin (TxEUD).
In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals so that the
contents of the respective timer Tx corresponds to the sensor position. The third position
sensor signal TOP0 can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/
underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out
monitoring of external hardware components, or may be used internally to clock timers T2 and
T4 for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or
capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are
stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their
associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered
either by an external signal or by a selectable state transition of its toggle latch T3OTL. When
both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL
with the low and high times of a PWM signal, this signal can be constantly generated without
software intervention.
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1
ST10R172L - GENERAL PURPOSE TIMERS
Timer input selection
FCPU=50MHz
000b
001b
010b
011b
100b
101b
110b
111b
Prescaler
Factor
8
16
32
64
128
256
512
1024
Input
Frequency
6.25 MHz 3.125
MHz
1.5625
MHz
781
KHz
391
KHz
195
KHz
97.5
KHz
48.83
KHz
Resolution
160ns
320ns
640ns
1.28 us
2.56 us
5.12 us
10.24 us 20.48 us
Period
10.49ms
20.97ms
41.94ms
83.88ms
168ms
336ms
672ms
1.342s
Table 5 GPT1 timer input frequencies, resolution and periods
U/D
T2EUD
Interrupt
Request
GPT1 Timer T2
CPU Clock
n
2 n=3...10
Mode
T2IN
CPU Clock
T2
2n n=3...10
T3OUT
T3
Mode
T3EUD
Reload
Capture
GPT1 Timer T3
T3OTL
U/D
T3IN
Capture
Reload
T4
T4IN
CPU Clock
T4EUD
Interrupt
Request
Mode
2n n=3...10
GPT1 Timer T4
U/D
Figure 5 GPT1 block diagram
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1
Interrupt
Request
ST10R172L - GENERAL PURPOSE TIMERS
9.2
GPT2
The GPT2 module provides precise event control and time measurement. It includes two
timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an
input clock derived from the CPU clock via a programmable prescaler or with external signals.
The count direction (up/down) for each timer is programmable by software or altered
dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is
supported by the output toggle latch (T6OTL) of timer T6, which changes its state on each
timer overflow/underflow.
The state of T6OTL may be used to clock timer T5, or may be output on a port pin T6OUT. The
overflows/underflows of timer T6 reload the CAPREL register. The CAPREL register captures
the contents of T5 based on an external signal transition on the corresponding port pin
(CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows
absolute time differences to be measured or pulse multiplication to be performedwithout
software overhead.
Timer input selection
FCPU=50MHz
000b
001b
010b
011b
100b
101b
110b
111b
Prescaler
Factor
4
8
16
32
64
128
256
512
Input
Frequency
12.5 MHz 6.25 MHz 3.125
MHz
1.563
MHz
781
KHz
391
KHz
195
KHz
97.6
KHz
Resolution
80ns
160ns
320ns
640ns
1.28 us
2.56 us
5.12 us
10.24 us
Period
5.24ms
10.49ms
20.97ms
41.94ms
83.88ms
167.7ms
335.5ms
671ms
Table 6 GPT2 timer input frequencies, resolution and periods
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ST10R172L - SERIAL CHANNELS
T5EUD
CPU Clock
U/D
2n n=2...9
T5IN
T5
Interrupt
Request
GPT2 Timer T5
Mode
Clear
Capture
Interrupt
Request
CAPIN
GPT2 CAPREL
Reload
T6IN
CPU Clock
Toggle FF
T6
2n n=2...9
Interrupt
Request
Mode
GPT2 Timer T6
T60TL
T6OUT
U/D
T6EUD
Figure 6 GPT2 block diagram
10
SERIAL CHANNELS
Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP).
ASC0
A dedicated baud rate generator sets up standard baud rates without oscillator tuning. 3
separate interrupt vectors are provided for transmission, reception, and erroneous reception.
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start
bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism
to distinguish address from data bytes has been included (8-bit data + wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift
clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back
option is available for testing purposes.
A number of optional hardware error detection capabilities have been included to increase the
reliability of data transfers. A parity bit can be generated automatically on transmission, or
checked on reception. Framing error detection recognizes data frames with missing stop bits.
An overrun error is generated if the last character received was not read out of the receive
buffer register at the time the reception of a new character is complete.The table below lists
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1
ST10R172L - SERIAL CHANNELS
various commonly used baud rates together with the required reload values and the deviation
errors compared to the intended baudrate.
S0BRS = ‘0’, fCPU = 50MHz
S0BRS = ‘1’, f CPU = 50MHz
Baud Rate
Deviation Error
(Baud)
Reload Value
Baud Rate
Deviation Error
(Baud)
Reload Value
1562500
0.0%
/ 0.0%
0000H / 0000H
1041666
0.0%
/ 0.0%
0000H / 0000H
56000
+3.3%
/ -0.4%
001AH / 001BH
56000
+3.3%
/ -2.1%
0011H / 0012H
38400
+1.7%
/ -0.8%
0027H / 0028H
38400
+0.5%
/ -3.1%
001AH / 001BH
19200
+0.5%
/ -0.8%
0050H / 0051H
19200
+0.5%
/-1.4%
0035H / 0036H
9600
+0.5%
/ -0.1%
00A1H/ 00A2H
9600
+0.5%
/ -0.5%
006BH / 006CH
4800
+0.2%
/ -0.1%
0144H / 0145H
4800
0.0%
/ -0.5%
00D8H / 00D9H
2400
0.0%
/ -0.1%
028AH / 028BH
2400
0.0%
/ -0.2%
01B1H / 01B2H
1200
0.0%
/ -0.1%
0515H / 0516H
1200
0.0%
/ -0.1%
0363H / 0364H
600
0.0%
/ 0.0%
0A2BH / 0A2CH
600
0.0%
/ -0.1%
06C7H / 06C8H
190
+0.4%
/+0.4%
1FFFH / 1FFFH
75
0.0%
/ 0.0%
363FH / 3640H
127
+0.1%
/ +0.1% 1FFFH / 1FFFH
Table 7 Commonly used baud rates, required reload values and deviation errors
SSP transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift
clock which is generated by the SSP. The SSP can start shifting with the LSB or with the MSB
and is used to select shifting and latching clock edges, and clock polarity. Up to two chip select
lines may be activated in order to direct data transfers to one or both of two peripheral devices.
When the SSP is enabled, the four upper pins of Port4 can not be used as general purpose
IO. Note that the segment address selection done via the system start-up configuration during
reset has priority and overrides the SSP functions on these pins.
SSPCKS Value
Synchronous baud rate
000
SSP clock = CPU clock divided by 2
25 MBit/s
001
SSP clock = CPU clock divided by 4
12.5 MBit/s
010
SSP clock = CPU clock divided by 8
6.25 MBit/s
Table 8 Synchronous baud rate and SSPCKS reload values
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1
ST10R172L - WATCHDOG TIMER
SSPCKS Value
Synchronous baud rate
011
SSP clock = CPU clock divided by 16
3.13 MBit/s
100
SSP clock = CPU clock divided by 32
1.56 MBit/s
101
SSP clock = CPU clock divided by 64
781 KBit/s
110
SSP clock = CPU clock divided by 128
391 KBit/s
111
SSP clock = CPU clock divided by 256
195 KBit/s
Table 8 Synchronous baud rate and SSPCKS reload values
11
WATCHDOG TIMER
The Watchdog Timer is a fail-safe mechanism which limits the malfunction time of the
controller. The Watchdog Timer is always enabled after device reset and can only be disabled
in the time interval until the EINIT (end of initialization) instruction has been executed. In this
way, the chip’s start-up procedure is always monitored. The software must be designed to
service the Watchdog Timer before it overflows. If, due to hardware or software related
failures, the software fails to maintain the Watchdog Timer, it will overflow generating an
internal hardware reset and pulling the RSTOUT pin low to reset external hardware
components.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by
128. The high byte of the Watchdog Timer register can be set to a pre-specified reload value
(stored in WDTREL) in order to allow further variation of the monitored time interval. Each
time it is serviced by the application software, the high byte of the Watchdog Timer is
reloaded. The table below shows the watchdog time range which for a 50MHz CPU clock
rounded to 3 significant figures.
Reload value
Prescaler for fCPU
in WDTREL
2 (WDTIN = ‘0’)
128 (WDTIN = ‘1’)
FFH
10.24 µs
655 µs
00H
2.62 ms
168 ms
Table 9 Watchdog timer range
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1
ST10R172L - SYSTEM RESET
12
SYSTEM RESET
The following type of reset are implemented on the ST10R172L:
Asynchronous hardware reset: Asynchronous reset does not require a stabilized clock
signal on XTAL1 as it is not internally resynchronized, it resets the microcontroller into its
default reset state. Asynchronous reset is required on chip power-up and can be used during
catastrophic situations. The rising edge of the RSTIN pin is internally resynchronized before
exiting the reset condition, therefore, only the entry to hardware reset is asynchronous.
Synchronous hardware reset (warm reset): A warm synchronous hardware reset is
triggered when the reset input signal RSTIN is latched low and Vpp pin is high. The I/Os are
immediately (asynchronously) set in high impedance, RSTOUT is driven low. After RSTIN
negation is detected, a short transition period elapses, during which pending internal hold
states are cancelled and any current internal access cycles are completed, external bus
cycles are aborted. Then, the internal reset sequence is active for 1024 TCL (512 CPU clock
cycles). During this reset sequence, if bit BDRSTEN was previously set by software (bit 5 in
SYSCON register), RSTIN pin is driven low and internal reset signal is asserted to reset the
microcontroller in its default state. Note that after all reset sequence, bit BDRSTEN is cleared.
After the reset sequence has been completed, the RSTIN input is sampled. When the reset
input signal is active at that time the internal reset condition is prolonged until RSTIN
becomes inactive.
Software reset: The reset sequence can be triggered at any time by the protected
instruction SRST (software reset). This instruction can be executed deliberately within a
program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals a system
failure. As for a synchronous hardware reset, the reset sequence lasts 1024 TCL (512 CPU
clock cycles), and drives the RSTIN pin low.
Watchdog timer reset: When the watchdog timer is not disabled during the initialization or
serviced regularly during program execution it will overflow and trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle does not use READY, or if READY is sampled active (low) after the
programmed waitstates. When READY is sampled inactive (high) after the programmed
waitstates the running external bus cycle is aborted. Then the internal reset sequence is
started. The watchdog reset cannot occur while the ST10R172L is in bootstrap loader mode.
Bidirectional reset: This reset makes the watchdog timer reset and software reset
externally visible. It is active for the duration of an internal reset sequences caused by a
watchdog timer reset and software reset. Therefore, the bidirectional reset transforms an
internal watchdog timer reset or software reset into an external hardware reset with a
minimum duration of 1024 TCL.
13
POWER REDUCTION MODES
Two different power reduction modes with different levels of power reduction can be entered
under software control.
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ST10R172L - SPECIAL FUNCTION REGISTERS
In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode
can be terminated by any reset or interrupt request.
In Power Down mode both the CPU and the peripherals are stopped. Power Down mode can
now be configured by software in order to be terminated only by a hardware reset or by an
external interrupt source on fast external interrupt pins.
All external bus actions are completed before Idle or Power Down mode is entered. However,
Idle or Power Down mode is not entered if READY is enabled, but has not been activated
(driven low for negative polarity, or driven high for positive polarity) during the last bus access.
14
SPECIAL FUNCTION REGISTERS
The following table lists all ST10R172L SFRs in alphabetical order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.
An SFR can be specified by its individual mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed by its physical address (using the Data Page
Pointers), or by its short 8-bit address (without using the Data Page Pointers).
Name
Physical
Address
8-Bit
Description
Address
Reset
Value
ADDRSEL1
FE18h
0Ch
Address Select Register 1
0000h
ADDRSEL2
FE1Ah
0Dh
Address Select Register 2
0000h
ADDRSEL3
FE1Ch
0Eh
Address Select Register 3
0000h
ADDRSEL4
FE1Eh
0Fh
Address Select Register 4
0000h
BUSCON0
b
FF0Ch
86h
Bus Configuration Register 0
0XX0h
BUSCON1
b
FF14h
8Ah
Bus Configuration Register 1
0000h
BUSCON2
b
FF16h
8Bh
Bus Configuration Register 2
0000h
BUSCON3
b
FF18h
8Ch
Bus Configuration Register 3
0000h
BUSCON4
b
FF1Ah
8Dh
Bus Configuration Register 4
0000h
FE4Ah
25h
GPT2 Capture/Reload Register
0000h
CAPREL
CC8IC
b
FF88h
C4h
EX0IN Interrupt Control Register
0000h
CC9IC
b
FF8Ah
C5h
EX1IN Interrupt Control Register
0000h
CC10IC
b
FF8Ch
C6h
EX2IN Interrupt Control Register
0000h
Table 10 Special functional registers
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ST10R172L - SPECIAL FUNCTION REGISTERS
Name
CC11IC
b
CP
CRIC
b
CSP
Physical
Address
8-Bit
Description
Address
Reset
Value
FF8Eh
C7h
EX3IN Interrupt Control Register
0000h
FE10h
08h
CPU Context Pointer Register
FC00h
FF6Ah
B5h
GPT2 CAPREL Interrupt Control Register
0000h
FE08h
04h
CPU Code Segment Pointer Register (read only)
0000h
DP0L
b
F100h
E
80h
P0L Direction Control Register
00h
DP0H
b
F102h
E
81h
P0h Direction Control Register
00h
DP1L
b
F104h
E
82h
P1L Direction Control Register
00h
DP1H
b
F106h
E
83h
P1h Direction Control Register
00h
DP2
b
FFC2h
E1h
Port 2 Direction Control Register
-0--h
DP3
b
FFC6h
E3h
Port 3 Direction Control Register
0000h
DP4
b
FFCAh
E5h
Port 4 Direction Control Register
00h
DP6
b
FFCEh
E7h
Port 6 Direction Control Register
00h
DP7
b
FFD2h
E9h
Port 7 Direction Control Register
-0h
DPP0
FE00h
00h
CPU Data Page Pointer 0 Register (10 bits)
0000h
DPP1
FE02h
01h
CPU Data Page Pointer 1 Register (10 bits)
0001h
DPP2
FE04h
02h
CPU Data Page Pointer 2 Register (10 bits)
0002h
DPP3
FE06h
03h
CPU Data Page Pointer 3 Register (10 bits)
0003h
EBUSCON b
F10Eh
E
87H
Extended BUSCON register
0000h
EXICON
F1C0h
E
E0h
External Interrupt Control Register
0000h
IDCHIP
F07Ch
E
3Eh
Device Identifier Register
1101h
IDMANUF
F07Eh
E
3Fh
Manufacturer/Process Identifier Register
0201h
IDMEM
F07Ah
E
3Dh
On-chip Memory Identifier Register
0000h
IDPROG
F078h
E
3Ch
Programming Voltage Identifier Register
0000h
FF0Eh
87h
CPU Multiply Divide Control Register
0000h
MDH
FE0Ch
06h
CPU Multiply Divide Register – High Word
0000h
MDL
FE0Eh
07h
CPU Multiply Divide Register – Low Word
0000h
MDC
b
b
Table 10 Special functional registers
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ST10R172L - SPECIAL FUNCTION REGISTERS
Physical
Address
Name
8-Bit
Description
Address
Reset
Value
ODP2
b
F1C2h
E
E1h
Port 2 Open Drain Control Register
-0--h
ODP3
b
F1C6h
E
E3h
Port 3 Open Drain Control Register
0000h
ODP6
b
F1CEh
E
E7h
Port 6 Open Drain Control Register
00h
ODP7
b
F1D2h
E
E9h
Port 7 Open Drain Control Register
-0h
FF1Eh
8Fh
Constant Value 1’s Register (read only)
FFFFh
ONES
P0L
b
FF00h
80h
Port 0 Low Register (Lower half of PORT0)
00h
P0H
b
FF02h
81h
Port 0 High Register (Upper half of PORT0)
00h
P1L
b
FF04h
82h
Port 1 Low Register (Lower half of PORT1)
00h
P1H
b
FF06h
83h
Port 1 High Register (Upper half of PORT1)
00h
P2
b
FFC0h
E0h
Port 2 Register (4 bits)
-0--h
P3
b
FFC4h
E2h
Port 3 Register
0000h
P4
b
FFC8h
E4h
Port 4 Register (8 bits)
00h
P5
b
FFA2h
D1h
Port 5 Register (read only)
XXXXh
P6
b
FFCCh
E6h
Port 6 Register (8 bits)
00h
P7
b
FFD0h
E8h
Port 7Register (4 bits)
-0h
PECC0
FEC0h
60h
PEC Channel 0 Control Register
0000h
PECC1
FEC2h
61h
PEC Channel 1 Control Register
0000h
PECC2
FEC4h
62h
PEC Channel 2 Control Register
0000h
PECC3
FEC6h
63h
PEC Channel 3 Control Register
0000h
PECC4
FEC8h
64h
PEC Channel 4 Control Register
0000h
PECC5
FECAh
65h
PEC Channel 5 Control Register
0000h
PECC6
FECCh
66h
PEC Channel 6 Control Register
0000h
PECC7
FECEh
67h
PEC Channel 7 Control Register
0000h
PP3
F03Eh
1Fh
PWM Module Period Register 3
0000h
FF10h
88h
CPU Program Status Word
0000h
FE36h
1Bh
PWM Module Pulse Width Register 3
0000h
PSW
PW3
b
E
Table 10 Special functional registers
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ST10R172L - SPECIAL FUNCTION REGISTERS
Name
Physical
Address
8-Bit
Description
Address
Reset
Value
PWMCON0 b
FF30h
98h
PWM Module Control Register 0
0000h
PWMCON1 b
FF32h
99h
PWM Module Control Register 1
0000h
PWMIC
b
F17Eh
E
BFh
PWM Module Interrupt Control Register
0000h
RP0H
b
F108h
E
84h
System Start-up Configuration Register (Rd. only) XXh
FEB4h
5Ah
Serial Channel 0 baud rate generator reload reg
0000h
S0BG
S0CON
b
FFB0h
D8h
Serial Channel 0 Control Register
0000h
S0EIC
b
FF70h
B8h
Serial Channel 0 Error Interrupt Control Register
0000h
FEB2h
59h
Serial Channel 0 receive buffer reg. (rd only)
XXh
B7h
Serial Channel 0 Receive Interrupt Control Reg.
0000h
CEh
Serial Channel 0 transmit buffer interrupt control
reg
0000h
FEB0h
58h
Serial Channel 0 transmit buffer register (wr only)
00h
FF6Ch
B6h
Serial Channel 0 Transmit Interrupt Control Regis- 0000h
ter
SP
FE12h
09h
CPU System Stack Pointer Register
FC00h
SSPCON0
EF00h
X
---
SSP Control Register 0
0000h
SSPCON1
EF02h
X
---
SSP Control Register 1
0000h
SSPRTB
EF04h
X
---
SSP Receive/Transmit Buffer
XXXXh
SSPTBH
EF06h
X
---
SSP Transmit Buffer High
XXXXh
STKOV
FE14h
0Ah
CPU Stack Overflow Pointer Register
FA00h
STKUN
FE16h
0Bh
CPU Stack Underflow Pointer Register
FC00h
FF12h
89h
CPU System Configuration Register
0xx0h1)
FE40h
20h
GPT1 Timer 2 Register
0000h
S0RBUF
S0RIC
b
FF6Eh
S0TBIC
b
F19Ch
S0TBUF
S0TIC
SYSCON
b
b
T2
E
T2CON
b
FF40h
A0h
GPT1 Timer 2 Control Register
0000h
T2IC
b
FF60h
B0h
GPT1 Timer 2 Interrupt Control Register
0000h
FE42h
21h
GPT1 Timer 3 Register
0000h
FF42h
A1h
GPT1 Timer 3 Control Register
0000h
T3
T3CON
b
Table 10 Special functional registers
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ST10R172L - SPECIAL FUNCTION REGISTERS
Name
T3IC
b
T4
Physical
Address
8-Bit
Description
Address
Reset
Value
FF62h
B1h
GPT1 Timer 3 Interrupt Control Register
0000h
FE44h
22h
GPT1 Timer 4 Register
0000h
T4CON
b
FF44h
A2h
GPT1 Timer 4 Control Register
0000h
T4IC
b
FF64h
B2h
GPT1 Timer 4 Interrupt Control Register
0000h
FE46h
23h
GPT2 Timer 5 Register
0000h
T5
T5CON
b
FF46h
A3h
GPT2 Timer 5 Control Register
0000h
T5IC
b
FF66h
B3h
GPT2 Timer 5 Interrupt Control Register
0000h
FE48h
24h
GPT2 Timer 6 Register
0000h
T6
T6CON
b
FF48h
A4h
GPT2 Timer 6 Control Register
0000h
T6IC
b
FF68h
B4h
GPT2 Timer 6 Interrupt Control Register
0000h
TFR
b
FFACh
D6h
Trap Flag Register
0000h
WDT
FEAEh
57h
Watchdog Timer Register (read only)
0000h
WDTCON
FFAEh
D7h
Watchdog Timer Control Register
000xh2)
XP1IC
b
F18Eh
E
C7h
SSP Interrupt Control Register
0000h
XP3IC
b
F19Eh
E
CFh
PLL unlock Interrupt Control Register
0000h
ZEROS
b
FF1Ch
8Eh
Constant Value 0’s Register (read only)
0000h
Table 10 Special functional registers
Note
1. The system configuration is selected during reset.
Note
2. Bit WDTR indicates a watchdog timer triggered reset.
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ST10R172L - ELECTRICAL CHARACTERISTICS
15
ELECTRICAL CHARACTERISTICS
15.1
Absolute Maximum Ratings
•
Ambient temperature under bias (TA): ......................................................-40°C to +85 °C
•
Storage temperature (TST):....................................................................... – 65 to +150 °C
•
Voltage on VDD pins with respect to ground (VSS):..................................... – 0.5 to +4.0 V
•
Voltage on any pin with respect to ground (VSS): ................................ –0.5 to VDD +0.5 V
•
Voltage on any 5V tolerant pin with respect to ground (VSS): .......................–0.5 to 5.5 V
•
Voltage on any 5V fail-safe pin with respect to ground (VSS): .......................–0.5 to 5.5 V
•
Input current on any pin during overload condition: .................................. –10 to +10 mA
•
Absolute sum of all input currents during overload condition: .............................|100 mA|
•
Power dissipation:.....................................................................................................1.0 W
Note
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not guaranteed. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. During
overload conditions (VIN>VDD or VIN<VSS) the voltage on pins with respect to ground
(VSS) must not exceed the values defined by the Absolute Maximum Ratings.
The parameters listed in this section represent both the ST10R172L controller characteristics
and the system requirements. To aid parameters interpretation in design evaluation, the a
symbol column is marked:
CC for Controller Characteristics: The ST10R172L logic provides signals with the
respective timing characteristics.
SR for System Requirement:
The external system must provide signals with the
respective timing characteristics to the ST10R172L.
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ST10R172L - ELECTRICAL CHARACTERISTICS
Remarks on 5 volt tolerant (5T) and 5 volt fail-safe (5S) pins
The 5V tolerant input and output pins can sustain an absolute maximum external voltage of
5.5V.
However, signals on unterminated bus lines might have overshoot above 5.5V, presenting
latchup and hot carrier risks. While these risks are under evaluation, observe the following security recommendations:
•
Maximum peak voltage on 5V tolerant pin with respect to ground (VSS)= +6 V
•
If the ringing of the external signal exceeds 6V, then clip the signal to the 5V supply.
Power supply failure condition
The power supply failure condition is a state where the chip is NOT supplied but is connected
to active signal lines. There are several cases:
•
3.3V external lines on 3.3V (3T) pin on the non powered chip: ...............NOT Acceptable
•
3.3V external lines on 5V tolerant (5T) pin on the non powered chip: ............. Acceptable
The 5V tolerant buffer do not leak: external signals not altered. No reliability problem.
•
3.3V external lines on 5V fail-safe (5S) pin on the non powered chip: ............ Acceptable
The 5V tolerant buffer do not leak: external signals not altered. No reliability problem.
•
5.5V external lines on 5V tolerant (5T) pin on the non powered chip: ............. Acceptable
For VERY SHORT times only: the buffers do not leak (external signals not altered) but
there is a fast degradation of the gate oxides in the buffers. The total maximum time under
this stress condition is 2 days. This limits this configuration to short power-up/down
sequences. For 10 year life time, the maximum duty factor is 1/1800 allowing e.g. a
maximum stress duration of 48 seconds per day.
•
5.5V external lines on 5V fail-safe (5S) pin on the non powered chip: ............ Acceptable
•
6V transient signals on 5V tolerant (5T) pin on the non powered chip: ...NOT Acceptable
•
6V transient signals on 5V fail-safe (5S) pin on the non powered chip:.......... Acceptable
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ST10R172L - ELECTRICAL CHARACTERISTICS
15.2
DC Characteristics
VDD = 3.3V ± 0.3V
VSS = 0 V
Reset active
TA = -40°C to +85 °C°
Limit Values
Parameter
Symbol
min.
max.
Unit
Test Condition
Input low voltage
VIL
SR
– 0.3
0.8
V
–
Input high voltage
(all except RSTIN and XTAL1)
VIH
SR
2.0
VDD + 0.3
V
–
Input high voltage RSTIN, RPD
VIH1
SR
0.6 VDD
VDD + 0.3
V
–
Input high voltage XTAL1
VIH2
SR
0.7 VDD
VDD + 0.3
V
–
Output low voltage
(ALE, RD, WR, BHE, CLKOUT,
RSTIN,RSTOUT, CSX)
VOL
CC
–
0.4
V
IOL = 4 mA
Output low voltage
(all other outputs)
VOL1
CC
–
0.4
V
IOL1 = 2 mA
Output high voltage
ALE, RD, WR, BHE, CLKOUT,
RSTIN,RSTOUT, CSX)
VOH
CC
2.4
–
V
IOH = –4 mA
Output high voltage1)
(all other outputs)
VOH1
CC
2.4
–
V
IOH = – 2mA
Input leakage current (3T pins)
IOZ
CC
–
±10
µA
0 V<VIN<VDD
Input leakage current (5T, 5S
pins)
IOZ1
CC
–
±10
µA
µA
0 V<VIN<VDD
±1007)
RSTIN pull-up resistor 2)
RRST
20
300
kΩ
VIN = 0 V
Read/Write pullup current3)
IRWH 4)
–
-40
µA
VOUT = 2.4 V
Read/Write pullup current3
IRWL5)
-500
–
µA
VOUT = 0.4 V
ALE pulldown current3
IALEL4
40
–
µA
VOUT = 0.4 V
ALE pulldown current3
IALEH5
–
500
µA
VOUT = 2.4 V
Port 6 (CS) pullup current3
IP6H4
–
-40
µA
VOUT = 2.4 V
Port 6 (CS) pullup current3
IP6L 5
-500
–
µA
VOUT = 0.4 V
CC
VDD<VIN<5.0V7)
Table 11 DC characteristics
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ST10R172L - ELECTRICAL CHARACTERISTICS
Limit Values
Parameter
Symbol
Unit
Test Condition
-4
µA
VIN = V IHmin
-50
–
µA
VIN = V ILmax
100
500
µA
VOUT = V DD
CC
–
±20
µA
0 V < VIN < VDD
CC
–
10
pF
f = 1 MHz
TA = 25 °C
ICC
–
15 +
2.5 * fCPU
mA
fCPU in [MHz] 7))
IID
–
10 +
0.9 * fCPU
mA
RSTIN = VIH1
200
µA
min.
max.
IP0H4
–
IP0L 5
RPD pulldown current2
IRPD5
XTAL1 input current
IIL
Pin capacitance6)
(digital inputs/outputs)
CIO
Power supply current
Idle mode supply current
PORT0 configuration current3
Power-down mode supply current I 8
PD
–
fCPU in [MHz] 7
VDD = 3.6 V 9
Table 11 DC characteristics
1) This specification is not valid for outputs which are switched to open drain mode. In this case
the respective output will float and the resulting voltage comes from the external circuitry.
2) This specification is only valid during reset, or interruptible power-down mode, after reception of an external interrupt signal that will wake up the CPU.
3) This specification is only valid during reset, hold or adapt-mode. Port 6 pins are only affected
if they are used for CS output and the open drain function is not enabled.
4) The maximum current may be drawn while the signal line remains inactive.
5) The minimum current must be drawn in order to drive the signal line active.
6) Not 100% tested, guaranteed by design characterization.
7) Supply current is a function of operating frequency as illustrated in Figure 7 on page 35.
This parameter is tested at V DDmax and 50 MHz CPU clock with all outputs disconnected
and all inputs at VIL or V IH with an infinite execution of NOP instruction fetched from external
memory (16-bit demux bus mode, no waitstates, no memory tri-state waitstates, normal
ALE).
8) Typical value at 25°C = 20µA.
9) This parameter is tested including leakage currents. All inputs (including pins configured as
inputs) at 0 V to 0.1 V or at VDD – 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
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1
Supply/idle current [mA]
ST10R172L - ELECTRICAL CHARACTERISTICS
200
ICCmax
150
100
IIDmax
15
10
20
30
40
50 f
CPU [MHz]
Figure 7 Supply/idle current vs operating frequency
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ST10R172L - ELECTRICAL CHARACTERISTICS
15.3
AC Characteristics
Test conditions
•
Input pulse levels: ........................................................................................... 0 to +3.0 V
•
Input rise and fall times (10%-90%):........................................................................ 2.5 ns
•
Input timing reference levels: ................................................................................. +1.5 V
•
Output timing reference levels: .............................................................................. +1.5 V
•
Output load: ................................................................................................... seeFigure 9
3V
0V
90%
1.5V
10%
90%
1.5V
10%
timing ref. points
≤ 2.5 ns
≤ 2.5ns
Figure 8 Input waveforms
~ 3.3 V
IOL = 1mA
From output
under test
Vref
IOH = 1mA
CL = 50pF
VOH
1.5V
1.5V
VOL
timing reference points
Figure 9 Output load circuit waveform
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ST10R172L - ELECTRICAL CHARACTERISTICS
~ 3.3 V
IOL = 5 mA
From output
under test
Vref
IOH = 5 mA
CL = 5 pF
VOH
VLOAD
VOL
VLOAD +0.15 V
VLOAD - 0.15 V
VOH - 0.15 V
timing reference
points
VOL + 0.15 V
For timing purposes a port pin is no longer floating when a 150 mV change from load
voltage occurs, but begins to float when a 150 mV change from the loaded VOH/VOL
level occurs.
CL is 5 pF for floating measurements only.
Figure 10 Float waveforms
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ST10R172L - ELECTRICAL CHARACTERISTICS
15.3.1 Cpu Clock Generation Mechanisms
ST10R172L internal operation is controlled by the CPU clock f CPU. Both edges of the CPU
clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external
timing (AC Characteristics) specification therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see figure below).
The CPU clock signal can be generated by different mechanisms. The duration of TCLs and
their variation (and also the external timing) depends on the f CPU generation mechanism. This
must be considered when calculating ST10R172L timing.
The CPU clock generation mechanism is set during reset by the logic levels on pins P0.15-13
(P0H.7-5).
Phase Locked Loop Operation (PLL factor=4)
fXTAL
fCPU
TCL TCL
Direct Clock Drive
fXTAL
fCPU
TCL TCL
Prescaler Operation
fXTAL
fCPU
TCL
TCL
Figure 11 CPU clock generation mechanisms
P0.15-13 (P0H.7-5)
CPU frequency
fCPU = f XTAL * F
External clock
input range 1050MHz
Notes
1
1
1
FXTAL * 4
2.5 to 12.5 MHz
Default configuration
1
1
0
FXTAL * 3
3.33 to 16.66 MHz
1
0
1
FXTAL * 2
5 to 25 MHz
Table 12 CPU clock generation mechanisms
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ST10R172L - ELECTRICAL CHARACTERISTICS
P0.15-13 (P0H.7-5)
CPU frequency
fCPU = f XTAL * F
External clock
input range 1050MHz
1
0
0
FXTAL * 5
2 to 10 MHz
0
1
1
FXTAL * 1
1 to 50 MHz
0
1
0
FXTAL * 1.5
6.66 to 33.33 MHz
0
0
1
FXTAL / 2
2 to 100 MHz
FXTAL * 2.5
4 to 20 MHz
0
0
0
Notes
Direct drive 1)
CPU clock via 2:1 prescaler
Table 12 CPU clock generation mechanisms
1) The maximum depends on the duty cycle of the external clock signal. The maximum input frequency is 25 MHz when using an external crystal oscillator, but
higher frequencies can be applied with an external clock source.
Prescaler operation
Set when pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the
duration of an individual TCL) is defined by the period of the input clock fXTAL .
The timings listed in the AC characteristics that refer to TCLs therefore can be calculated
using the period of fXTAL for any TCL.
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
Direct drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset, the on-chip phase locked loop is
disabled and the CPU clock is driven from the internal oscillator with the input clock signal.
The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL.
The TCL timing below must be calculated using the minimum possible TCL which can be
calculated by the formula: TCL min = 1 ⁄ f XTAL × DCmin ( DC = duty cycle )
For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so
the duration of 2TCL is always 1/fXTAL. Therefore, the minimum value TCLmin has to be used
only once for timings that require an odd number of TCLs (1,3,...). Timings that require an
even number of TCLs (2,4,...) may use the formula: 2TCL = 1 ⁄ fXTAL .
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ST10R172L - ELECTRICAL CHARACTERISTICS
Note
The address float timings in Multiplexed bus mode (t11 and t45 ) use
TCL max = 1 ⁄ f XTAL × DC max instead of TCL min .
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
Oscillator Watchdog (OWD)
When the clock option selected is direct drive or direct drive with prescaler, in order to provide
a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is
implemented as an additional functionality of the PLL circuitry. This oscillator watchdog
operates as follows:
After a reset, the Oscillator Watchdog is enabled by default. To disable the OWD, set bit 4 of
SYSCON register OWDDIS.
When the OWD is enabled, the PLL runs on its free-running frequency and increments the
Oscillator Watchdog counter. On each transition of the XTAL1 pin, the Oscillator Watchdog is
cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows
(after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running
clock signal, and the Oscillator Watchdog Interrupt Request (XP3INT) is flagged. The CPU
clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin.
Only a hardware reset can switch the CPU clock source back to direct clock input.
When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL
is switched off to decrease power supply current.
Phase locked loop
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by the
factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fXTAL * F). With
every F’th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. In
this way, fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter
of fCPU which affects individual TCL duration.Therefore, AC characteristics that refer to TCLs
must be calculated using the minimum possible TCL.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL constantly
adjusts its output frequency, it corresponds to the applied input frequency (crystal or
oscillator). The relative deviation for periods of more than one TCL is lower than for one single
TCL. For a period of N * TCL the minimum value is computed using the corresponding
deviation DN:
TCL min = TCL NOM × ( 1 – D N ⁄ 100 )
D N = ± ( 4 – N ⁄ 15 ) [ % ]
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ST10R172L - ELECTRICAL CHARACTERISTICS
where N = number of consecutive TCLs and 1 ≤ N ≤ 40. So for a period of 3 TCLs (i.e. N = 3):
D 3 = 4 – 3 ⁄ 15
= 3.8%
and
3TCL min = 3TCL NOM × ( 1 – 3.8 ⁄ 100 )
= 3TCL NOM × 0.962 ( 36.07nsec @fcpu=50MHz )
PLL jitter is an important factor for bus cycles using waitstates and for the operation of timers,
serial interfaces, etc. For slower operations and longer periods (e.g. pulse train generation or
measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible.
Max.jitter [%]
This formula is valid for 1<N<40 and 10<fcpu<50
±4
±3
±2
±1
2
4
8
16
32 N
Figure 12 Approximated maximum PLL jitter
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15.3.2 Memory Cycle Variables
The timing tables below use three variables derived from the BUSCONx registers and
represent programmed memory cycle characteristics. Table 13 describes how these variables
are computed.
Description
Symbol
Values
ALE Extension
tA
TCL * <ALECTL>
Memory Cycle Time Waitstates
tC
2TCL * (15 - <MCTC>)
Memory Tristate Time
tF
2TCL * (1 - <MTTC>)
Table 13 Memory cycle variables
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15.3.3 Multiplexed Bus
VDD = 3.3 V ± 0.3 V
VSS = 0 V
TA = -40°C to +85 °C
CL = 50 pF
Parameter
Symbol
Max. CPU Clock
= 50 MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
Unit
ALE cycle time = 6 TCL + 2tA + tC + tF (60 ns at 50-MHz CPU clock without waitstates)
ALE high time
t5
CC 7 + t A
–
TCL - 3 + t A
–
ns
Address (P1, P4), BHE
setup to ALE
t6
CC 3 + t A
–
TCL - 7 + t A
–
ns
Address (P0) setup to ALE t6m
CC 5 + t A
–
TCL - 5 + t A
–
ns
Address hold after ALE
t7
CC 5 + t A
–
TCL - 5 + t A
–
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC 5 + t A
–
TCL - 5 + t A
–
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC -5 + tA
–
-5 + tA
–
ns
Address float after RD,
t10
CC –
51
–
51
ns
t11
CC –
151
–
TCL + 51
ns
RD, WR low time
(with RW-delay)
t12
CC 13 + t C
–
2TCL - 7+ tC
–
ns
RD, WR low time
(no RW-delay)
t13
CC 23 + t C
–
3TCL - 7 + tC
–
ns
RD to valid data in
(with RW-delay)
t14
SR
–
5 + tC
–
2TCL - 15
+ tC
ns
RD to valid data in
(no RW-delay)
t15
SR
–
15 + tC
–
3TCL - 15
+ tC
ns
ALE low to valid data in
t16
SR
–
15
+ t A + tC
–
3TCL - 15
+ tA + tC
ns
Address to valid data in
t17
SR
–
20
+ 2tA + tC
–
4TCL - 20
+ 2t A + t C
ns
(with RW-delay)
1)
Address float after RD,
(no RW-delay)
1
Table 14 Multiplexed bus
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1
Parameter
Symbol
Max. CPU Clock
= 50 MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
Unit
ST10R172L - ELECTRICAL CHARACTERISTICS
Data hold after RD
rising edge
t18
SR
0
–
0
–
ns
Data float after RD rising
t19
SR
–
15 + tF2
–
2TCL - 5 + tF2
ns
Data valid to WR
t22
CC 13 + t C
–
2TCL - 7 + tC
–
ns
Data hold after WR
t23
CC 13 + t F
–
2TCL - 7+ tF
–
ns
ALE rising edge after RD,
WR
t25
CC 10 + t F
–
2TCL - 10 + tF
–
ns
Address hold after RD, WR t27
CC 10 + t F
–
2TCL - 10 + tF
–
ns
Latched CS setup to ALE
t38
CC -7 + tA
3 + tA
-7 + tA
3 + tA
ns
Unlatched CS setup to
ALE
t38u
CC 3 + tA
–
TCL - 7 + tA
–
ns
Latched CS low to Valid
Data In
t39
SR
13
–
3TCL - 17
+ t C + 2t A
ns
–
4TCL - 17
+ t C + 2t A
ns
edge
12))
–
+ t C + 2tA
Unlatched CS low to Valid t39u
Data In
SR
Latched CS hold after RD, t40
WR
CC 20 + t F
–
3TCL - 10 + tF
–
ns
Unlatched CS hold after
RD, WR
t40u
CC 10 + t F
–
2TCL - 10 + tF
–
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
t42
CC 7 + t A
–
TCL - 3 + t A
–
ns
ALE fall. edge to RdCS,
WrCS (no RW delay)
t43
CC -3 + tA
–
-3 + tA
–
ns
Address float after RdCS
t44
CC –
31
–
31
ns
t45
CC –
131
–
TCL + 31
ns
–
23
+ t C + 2tA
1
(with RW delay)
Address float after RdCS
(no RW
delay)1
Table 14 Multiplexed bus
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1
Parameter
Symbol
Max. CPU Clock
= 50 MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
Unit
ST10R172L - ELECTRICAL CHARACTERISTICS
RdCS to Valid Data In
(with RW delay)
t46
SR
–
3 + tC
–
2TCL - 17
+ tC
ns
RdCS to Valid Data In
(no RW delay)
t47
SR
–
13 + tC
–
3TCL - 17
+ tC
ns
RdCS, WrCS Low Time
(with RW delay)
t48
CC 13 + t C
–
2TCL - 7+ tC
–
ns
RdCS, WrCS Low Time
(no RW delay)
t49
CC 23 + t C
–
3TCL - 7+ tC
–
ns
Data valid to WrCS
t50
CC 10 + t C
–
2TCL - 10 + tC
–
ns
Data hold after RdCS
t51
SR
0
–
0
–
ns
Data float after RdCS 1 2
t52
SR
–
13 + tF2
–
2TCL - 7 + tF2
ns
Address hold after
RdCS, WrCS
t54
CC 10 + t F
–
2TCL - 10 + tF
–
ns
Data hold after WrCS
t56
CC 10 + t F
–
2TCL - 10 + tF
–
ns
Table 14 Multiplexed bus
1) Output loading is specified using Figure 10 (CL = 5 pF).
2) This delay assumes that the following bus cycle is a multiplexed bus cycle. If next bus cycle
is demultiplexed, refer to demuxultiplexed equivalent AC timing.
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CLKOUT
t5
t25
t16
ALE
t38u
t38
t39u
CSx
t6
t40
t39
t40u
t27
t17
A23-A16
(A15-A8)
BHE
Address
t16
Read Cycle
BUS
P0
t6m
t7
t18
Address
t10
t8
t19m
t14
RD
t13
t9
t12
t11
t15
Write Cycle
BUS
P0
t23
Address
Data Out
t8
WR,
WRL, WRH
Address
Data In
t22
t9
t12
t13
Figure 13 External memory cycle:
multiplexed bus, with/without read/write delay, normal ALE
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CLKOUT
t16
t5
t25
ALE
t38u
t38
t40
t39u
t39
CSx
t6d/b
t40u
t17
A23-A16
(A15-A8)
BHE
Address
t27
Read Cycle
t6m
BUS
P0
t7
Data In
Address
t8
t9
t18
t10
t19m
t11
t14
RD
t15
t12
t13
Write Cycle
BUS
P0
Address
Data Out
t23
t8
t9
WR
WRL,
WRH
t10
t11
t13
t22
t12
Figure 14 External memory cycle:
multiplexed bus, with/without read/write delay, extended ALE
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CLKOUT
t5
t25
t16
ALE
t6b/d
t27
t17
A23-A16
(A15-A8)
BHE
Address
t16
Read Cycle
BUS
P0
t6m
t7
t51
Address
t44
t42
t52m
t46
RdCSx
t49
t43
t48
t45
t47
Write Cycle
BUS
P0
Address
Data In
t56
Address
Data Out
t42
t50
WrCSx
t43
t48
t49
Figure 15 External memory cycle:
multiplexed bus, with/without read/write delay, normal ALE, read/write chip select
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CLKOUT
t16
t5
t25
ALE
A23-A16
(A15-A8)
BHE
t6d/b
t17
Address
t54
Read Cycle
t6m
BUS
P0
t7
Data In
Address
t42
t43
t18
t44
t19m
t45
t46
RdCSx
t48
t47
t49
Write Cycle
BUS
P0
Address
Data Out
t42
t43
WR
WRL,
WRH
t56
t44
t45
t50
t48
t49
Figure 16 External memory cycle:
multiplexed bus, with/without read/write delay, extended ale, read/write chip select
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15.3.4 Demultiplexed Bus
VDD = 3.3 V ± 0.3 V
VSS = 0 V
TA = -40°C to +85 °C
CL = 50 pF
Parameter
Max CPU Clock 50MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
Symbol
Unit
ALE cycle time = 4 TCL + 2tA + tC + tF (40 ns at 50 MHz CPU clock without waitstates)
ALE high time
t5
CC
7 + tA
–
TCL - 3 + tA
–
ns
Address (P1, P4), BHE
setup to ALE
t6
CC
3 + tA
–
TCL - 7 + tA
–
ns
Address setup to RD, WR
(with RW-delay)
t80
CC
13 + 2tA
–
2TCL - 7 + 2tA –
ns
Address setup to RD, WR
(no RW-delay)
t81
CC
3 + 2tA
–
TCL - 7 + 2tA
–
ns
RD, WR low time
(with RW-delay)
t12
CC
13 + tC
–
2TCL - 7 + tC
–
ns
RD, WR low time
(no RW-delay)
t13
CC
23 + tC
–
3TCL - 7 + tC
–
ns
RD to valid data in
(with RW-delay)
t14
SR
–
5 + tC
–
2TCL - 15
+ tC
ns
RD to valid data in
(no RW-delay)
t15
SR
–
15 + tC
–
3TCL - 15
+ tC
ns
ALE low to valid data in
t16
SR
–
15 + tA + tC –
3TCL - 15
+ tA + tC
ns
Address to valid data in
t17
SR
–
20 + 2tA +
–
4TCL - 20
+ 2tA + tC
ns
ns
tC
Data hold after RD
rising edge
Data float after RD rising
edge (with RW-delay)
t18
SR
0
–
0
–
t20
SR
–
15
–
2TCL - 5
1) 2)
Data float after RD rising
t21
SR
–
edge (no RW-delay)
Data valid to WR
+ t F + 2t A
+ tF + 2tA2
12
5 + tF +
2tA
t22
CC
13 + tC
–
–
1
TCL - 5
ns
2
+ t F + 2t A
2
2TCL - 7 + tC
Table 15 Demultiplexed bus
50/68
ns
2
–
ns
Parameter
Max CPU Clock 50MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
Symbol
Unit
ST10R172L - ELECTRICAL CHARACTERISTICS
Data hold after WR
t24
CC
5 + tF
–
TCL - 5 + tF
–
ns
ALE rising edge after RD,
WR
t26
CC
-5 + tF
–
-5 + tF
–
ns
Address hold after RD, WR
t28
CC
0 (no tF)
–
0 (no tF)
–
ns
–
ns
-9+tF (tF>0)
Address hold after WRH
t28h CC
-1 (no tF)
-9+ tF (tF>0)
–
-8 +tF (t F>0)
Latched CS setup to ALE
-8 + tF (tF>0)
-7 + tA
3 + tA
-7 + tA
3 + tA
ns
Unlatched CS setup to ALE t38u CC
3 + tA
–
TCL - 7 + tA
–
ns
Latched CS low to Valid
Data In
t39
SR
–
13
+ tC + 2tA
–
3TCL - 17
+ tC + 2tA
ns
Unlatched CS low to Valid
Data In
t39u SR
–
23
+ tC + 2tA
–
4TCL - 17
+ tC + 2tA
ns
Latched CS hold after RD,
WR
t41
3 + tF
–
TCL - 7 + tF
–
ns
0 (no tF)
–
0 (no tF)
–
ns
t38
CC
-1 (no tF)
CC
Unlatched CS hold after RD, t41u CC
WR
-7 +tF (t F>0)
-7 + tF (tF>0)
Address setup to RdCs,
WrCs (with RW-delay)
t82
CC
13 + 2tA
–
2TCL - 7 + 2tA –
ns
Address setup to RdCs,
WrCs (no RW-delay)
t83
CC
3 + 2tA
–
TCL - 7 + 2tA
–
ns
RdCS to Valid Data In
(with RW-delay)
t46
SR
–
3 + tC
–
2TCL - 17 + tC ns
RdCS to Valid Data In
(no RW-delay)
t47
SR
–
13 + tC
–
3TCL - 17 + tC ns
RdCS, WrCS Low Time
(with RW-delay)
t48
CC
11 + tC
–
2TCL - 9 + tC
–
ns
RdCS, WrCS Low Time
(no RW-delay)
t49
CC
21 + tC
–
3TCL - 9 + tC
–
ns
Data valid to WrCS
t50
CC
13 + tC
–
2TCL - 7 + tC
–
ns
Table 15 Demultiplexed bus
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1
Parameter
Max CPU Clock 50MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
Symbol
Unit
ST10R172L - ELECTRICAL CHARACTERISTICS
Data hold after RdCS
t51
SR
0
–
0
–
Data float after RdCS
t53
SR
–
13 + tF +
–
2TCL - 7
(with RW-delay)
12
Data float after RdCS
(no
t68
SR
–
RW-delay)1 2
2
2tA
+ tF + 2tA
3 + tF+ 2tA2 –
TCL - 7
+ tF + 2tA
ns
ns
2
ns
2
Address hold after
RdCS, WrCS
t55
CC
-5 + tF
–
-5 + tF
–
ns
Data hold after WrCS
t57
CC
3 + tF
–
TCL - 7 + tF
–
ns
Table 15 Demultiplexed bus
1) Output loading is specified using Figure 10 with CL = 5 pF.
2) This delay assumes that the following bus cycle is a demultiplexed bus cycle and that the
data bus will only be driven externally when the RD or RdCs signal becomes active. RWdelay and tA refer to the following bus cycle. If the following bus cycle is a muxtiplexed bus
cycle, refer to equivalent multiplexed AC timing (which are still applicable due to automatic
insertion an idle state (2TCL) when switching from Demultiplexed to Multiplexed Bus Mode.
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CLKOUT
t5
t26
t16
ALE
t38u
t38
t41
t39u
t41u
t39
CSx
t6
A23-A16
(A15-A8)
BHE
t17
t28, t28h
Address
t18
Read Cycle
P0 BUS
(D15-D8)
D7-D0
Data In
t80
t81
t20d
t14
t21d
t15
RD
t12
t13
Write Cycle
P0 BUS
(D15-D8)
D7-D0
Data Out
t80
t22
t81
t24
WR(L),
WRH
t12
t13
Figure 17 External memory cycle:
demultiplexed bus, with/without read/write delay, normal ALE
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CLKOUT
t5
t26
t16
ALE
t38u
t38
t41
t39u
t39
CSx
t6
A23-A16
(A15-A8)
BHE
t41u
t28,t28h
t17
Address
Read Cycle
t18
P0 BUS
(D15-D8)
D7-D0
Data In
t20d
t14
t80
t15
t81
t21d
RD
t12
t13
Write Cycle
P0 BUS
(D15-D8)
D7-D0
Data Out
t80
t81
t22
t24
WR(L),
WRH
t12
t13
Figure 18 External memory cycle:
demultiplexed bus, with/without read/write delay, extended ALE
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CLKOUT
t5
t26
t16
ALE
t6
A23-A16
(A15-A8)
BHE
t17
t55
Address
t51
Read Cycle
P0 BUS
(D15-D8)
D7-D0
Data In
t82
t83
t53d
t46
t68d
t47
RdCsx
t48
t49
Write Cycle
P0 BUS
(D15-D8)
D7-D0
Data Out
t82
t50
t83
t57
WrCSx
t48
t49
Figure 19 External memory cycle:
demultiplexed bus, with/without read/write delay, normal ALE, read/write chip select
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ST10R172L - ELECTRICAL CHARACTERISTICS
CLKOUT
t5
t26
t16
ALE
A23-A16
(A15-A8)
BHE
t6
t55
t17
Address
Read Cycle
t51
P0 BUS
(D15-D8)
D7-D0
Data In
t53d
t46
t82
t47
t83
t68d
RdCSx
t48
t49
Write Cycle
P0 BUS
(D15-D8)
D7-D0
Data Out
t82
t83
t50
t57
WrCSx
t48
t49
Figure 20 External memory cycle:
demultiplexed bus, no read/write delay, extended ALE, read/write chip select
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ST10R172L - ELECTRICAL CHARACTERISTICS
15.3.5 CLKOUT and READY/READY
Parameter
VSS = 0 V
Symbol
TA = -40°C to +85 °C
CL = 50 pF
Max. CPU Clock
= 50 MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
Unit
VDD = 3.3 V ± 0.3 V
CLKOUT cycle time
t29
CC 20
20
2TCL
2TCL
ns
CLKOUT high time
t30
CC 5
–
TCL – 5
–
ns
CLKOUT low time
t31
CC 5
–
TCL – 5
–
ns
CLKOUT rise time1)
t32
CC –
31
–
31
ns
CLKOUT fall time1
t33
CC –
31
–
31
ns
CLKOUT rising edge to
ALE falling edge
t34
CC -3 + tA
5 + tA
-3 + tA
5 + tA
ns
Synchronous READY
setup time to CLKOUT
t35
SR 9
–
9
–
ns
Synchronous READY
hold time after CLKOUT
t36
SR 0
–
0
–
ns
Asynchronous READY
low time
t37
SR 27
–
2TCL + 7
–
ns
Asynchronous READY
t58
SR 9
–
9
–
ns
t59
SR 0
–
0
–
ns
Async. READY hold time
t60
after RD, WR high (Demulti-
SR 0
0
0
TCL - 10
setup time2)
Asynchronous READY
hold time
2
plexed Bus)3)2
+ 2tA+ tc+ tF
3
+ 2tA+ tc+ tF
ns
3
Table 16 CLKOUT and READY/READY
1) Measured between 0.3 and 2.7 volts
2) These timings assure recognition at a specific clock edge for test purposes only.
3) Demultiplexed bus is the worst case. For multiplexed bus, 2TCL should be added
to the maximum values. This adds even more time for deactivating READY.
2tA and tC refer to the following bus cycle, tF refers to the current bus cycle.
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ST10R172L - ELECTRICAL CHARACTERISTICS
READY
waitstate
Running cycle 1)
CLKOUT
t32
MUX/Tristate 6)
t33
t30
t29
t31
t34
ALE
7)
Command
2)
RD, WR
t36
t35
t35
Sync
3)
3)
READY
t58
Async
t59
t58
3)
READY
t59
t35
t37
t36
Sync
Async
4)
t59
t60
4)
t58
3)
t36
t35
3)
3)
READY
READY
t60
3)
5)
t58
t36
t59
3)
5)
t37
see 6)
Figure 21 CLKOUT and READY/READY
1
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2
The leading edge of the respective command depends on RW-delay.
3
READY (or READY) sampled HIGH (resp. LOW) at this sampling point generates a
READY controlled waitstate, READY (resp. READY) sampled LOW (resp. HIGH) at this
sampling point terminates the currently running bus cycle.
4
READY (resp. READY) may be deactivated in response to the trailing (rising) edge of the
corresponding command (RD or WR).
5
If the Asynchronous READY (or READY) signal does not fulfill the indicated setup and
hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t
37 in order to be safely synchronized. This is guaranteed, if READY is removed in
response to the command (see Note 4)).
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ST10R172L - ELECTRICAL CHARACTERISTICS
6
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional
MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this
delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is
zero.
7
The next external bus cycle may start here.
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ST10R172L - ELECTRICAL CHARACTERISTICS
15.3.6 External Bus Arbitration
Parameter
VSS = 0 V
TA = -40°C to +85 °C
Symbol
CL = 50 pF
Max. CPU Clock
= 50 MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
Unit
VDD = 3.3 V ± 0.3 V
HOLD input setup time
to CLKOUT
t61
SR
15
–
15
–
ns
CLKOUT to HLDA high
or BREQ low delay
t62
CC
–
10
–
10
ns
CLKOUT to HLDA low
or BREQ high delay
t63
CC
–
10
–
10
ns
CSx release
t64
CC
–
15
–
15
ns
CSx drive
t65
CC
-3
15
-3
15
ns
Other signals release
t66
CC
–
15
–
15
ns
Other signals drive
t67
CC
-3
15
-3
15
ns
Table 17 External bus arbitration
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ST10R172L - ELECTRICAL CHARACTERISTICS
CLKOUT
t61
HOLD
t63
HLDA
1)
t62
BREQ
2)
t64
3)
CSx
(On P6.x)
t66
Other
Signals
1)
Figure 22 External bus arbitration, releasing the bus
1
The ST10R172L will complete the running bus cycle before granting bus access.
2
This is the first opportunity for BREQ to become active.
3
The CS outputs will be resistive high (pullup) after t64.
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ST10R172L - ELECTRICAL CHARACTERISTICS
2)
CLKOUT
t61
HOLD
t62
HLDA
t62
BREQ
t62
t63
1)
t65
CSx
(On P6.x)
t67
Other
Signals
Figure 23 External bus arbitration, (regaining the bus)
1
This is the last chance for BREQ to trigger the regain-sequence indicated.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be de-activated without the ST10R172L requesting the
bus.
2
The next ST10R172L driven bus cycle may start here.
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ST10R172L - ELECTRICAL CHARACTERISTICS
15.3.7 External Hardware Reset
Parameter
VSS = 0 V
Symbol
TA = -40°C to +85 °C CL = 50 pF
Max. CPU Clock
= 50 MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
Unit
VDD = 3.3 V ± 0.3 V
Sync. RSTIN low time1)
t70
SR
50
–
4 TCL + 10
–
ns
RSTIN low to internal
reset sequence start
t71
CC
4
16
4
16
TCL
internal reset sequence,
(RSTIN internally pulled
low)
t72
CC
1024
1024
1024
1024
TCL
RSTIN rising edge to inter- t73
nal reset condition end
CC
4
6
4
6
TCL
PORT0 system start-up
configuration setup to
t74
SR
100
–
100
–
ns
PORT0 system start-up
configuration hold after
RSTIN rising edge
t75
SR
1
6
1
6
TCL
Bus signals drive from
internal reset end
t76
CC
0
20
0
20
ns
RSTIN low to signals
release
t77
CC
–
50
–
50
ns
ALE rising edge from inter- t78
nal reset condition end
CC
8
8
8
8
TCL
t79
SR
1500
–
1500
–
ns
RSTIN rising edge 2))
Async. RSTIN low time1
Table 18 External hardware reset
1) On power-up reset, the RSTIN pin must be asserted until a stable clock signal is available
(about 10...50 ms to allow the on-chip oscillator to stabilize) and until System Start-up Configuration is correct on PORT0 (about 50 µs for internal pullup devices to load 50 pF from
VILmin to VIHmin).
2) The value of bits 0 (EMU), 1 (ADAPT), 13 to 15 (Clock Configuration) are loaded during
hardware reset as long as internal reset signal is active, and have an immediate effect on
the system.
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ST10R172L - ELECTRICAL CHARACTERISTICS
1)
t792)
RSTIN
t73 t76
Internal
Reset
Signal
t78
ALE
RD, WR
3)
t74
t75
4)
PORT0
PORT1
(Demux Bus)
RSTOUT 5)
Other IOs
6)
t77
Figure 24 External asynchronous hardware reset (power-up reset): Vpp low
1
The ST10R172L is reset in its default state asynchronously with RSTIN. The internal
RAM content may be altered if an internal write access is in progress.
2
On power-up, RSTIN must be asserted t79 after a stabilized CPU clock signal is available.
3
Internal pullup devices are active on the PORT0 lines, so - input level is high if the respective pin is left open - or is low if the respective pin is connected to an external pulldown
device.
4
The ST10R172L starts execution here at address 00’0000h.
5
RSTOUT stays active until execution of the EINIT (end of initialization) instruction.
6
Activation of the IO pins is controlled by software
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ST10R172L - ELECTRICAL CHARACTERISTICS
.
t722)
t70
RSTIN
t73 t76
t711)
Internal
Reset
Signal
3)
t78
ALE
RD, WR
4)
t74
t75
5)
PORT0
PORT1
(Demux Bus)
RSTOUT 6)
Other IOs
7)
t77
Figure 25 External synchronous hardware reset (warm reset): Vpp high
1
The pending internal hold states are cancelled and the current internal access cycle (if
any) is completed.
2
RSTIN pulled low by internal device during internal reset sequence.
3
The reset condition may ends here if RSTIN pin is sampled high after t72.
4
Internal pullup devices are active on the PORT0 lines. Their input level is high if the
respective pin is left open, or is low if the respective pin is connected to an external pulldown device by resistive high (pullup) after t64 .
5
The ST10R172L starts execution here at address 00’0000h.
6
RSTOUT stays active until execution of the EINIT (End of Initialization) instruction.
7
Activation of the IO pins is controlled by software.
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ST10R172L - ELECTRICAL CHARACTERISTICS
15.3.8 Synchronous Serial Port Timing
VSS = 0 V
TA = -40°C to +85 °C
Max. Baudrate
Parameter
Variable Baudrate
= 0.2 to 25 MBd
= 25 MBd
Symbol
min.
CL = 50 pF
max.
min.
Unit
VCC = 3.3 V ± 0.3 V
max.
SSP clock cycle time
t200 CC
40
40
4 TCL
SSP clock high time
t201 CC
13
–
SSP clock low time
t202 CC
13
–
SSP clock rise time
t203 CC
–
3
SSP clock fall time
t204 CC
–
3
CE active before shift edge
t205 CC
13
–
t200/2 - 7
CE inactive after latch edge
t206 CC
33
47
t200 - 7
Write data valid after shift edge
t207 CC
–
7
–
7
ns
Write data hold after shift edge
t208 CC
0
–
0
–
ns
Write data hold after latch edge
t209 CC
15
25
t200/2 - 5
t200/2 + 5
ns
Read data active after latch edge
t210 SR
27
–
t200/2 + 7
–
ns
15
–
15
–
ns
0
–
0
–
ns
Read data setup time before latch edge t211
Read data hold time after latch edge
SR
t212 SR
512 TCL
ns
t200/2 - 7
–
ns
t200/2 - 7
–
ns
–
3
ns
–
3
ns
–
ns
Table 19 Synchronous serial port timing
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t200 + 7
ns
ST10R172L - ELECTRICAL CHARACTERISTICS
t200
t202
t201
2)
1)
SSPCLK
t203
t204
t205
t206
SSPCEx
3)
t207
SSPDAT
t207
1st Bit
t208
t207
t209
2nd Bit
Last Bit
Figure 26 SSP write timing
2)
1)
SSPCLK
t206
SSPCEx
3)
t210
t209
SSPDAT
last Wr. Bit
t211
1st.In Bit
t212
Lst.In Bit
Figure 27 SSP read timing
1
The transition of shift and latch edge of SSPCLK is programmable. This figure uses the
falling edge as shift edge (drawn bold).
2
The bit timing is repeated for all bits to be transmitted or received.
3
The active level of the chip enable lines is programmable. This figure uses an active low
CE (drawn bold). At the end of a transmission or reception the CE signal is disabled in single transfer mode. In continuous transfer mode it remains active.
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ST10R172L - PACKAGE MECHANICAL DATA
16
PACKAGE MECHANICAL DATA
Dim
mm
Min
Typ
A
inches
Max
Min
Typ
1.60
Max
0.063
A2
1.35
1.40
1.45
0.053
0.055
0.057
D
15.75
16.00
16.25
0.620
0.630
0.640
D1
13.90
14.00
14.10
0.547
0.551
0.555
D3
12.00
0.472
E
15.75
16.00
16.25
0.620
0.630
0.640
E1
13.90
14.00
14.10
0.547
0.551
0.555
E3
12.00
0.472
e
0.50
0.020
Number of Pins
ND
25
NE
25
N
100
Figure 28 Package outline TQFP100 (14 x 14 mm)
17
ORDERING INFORMATION
Sales type
Temperature range
ST10R172LT1
0°C to 70°C
ST10R172LT6
-40°C to +85 °C
Package
TQFP100 (14x 14)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved.
Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an
I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.
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