TI TMS320C206PZA80

TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
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High-Performance Static CMOS Technology
Includes the ’320C2xLP Core CPU
TMS320C206, TMS320LC206 are Members
of the ’C20x/’C2000 Platform Which Also
Includes the TMS320C203/LC203 and
TMS320F206 Devices
Instruction-Cycle Time 25 ns at 3.3 V
Source Code Compatible With TMS320C25
and other ’20x Devices
Upwardly Code-Compatible With
TMS320C5x Devices
Four External Interrupts
TMS320C206, 5-V I/O (3.3-V core)
TMS320LC206, 3.3-V core and I/O
TMS320C206, TMS320LC206 Integrated
Memory:
– 544 × 16 Words of On-Chip Dual-Access
Data RAM
– 32K × 16 Words of On-Chip ROM
– 4K × 16 Words of On-Chip Single-Access
Program/ Data RAM
224K × 16-Bit Maximum Addressable
External Memory Space
– 64K Program
– 64K Data
– 64K Input/Output (I/O)
– 32K Global
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32-Bit Arithmetic Logic Unit (ALU )
Accumulator
16 × 16-Bit Multiplier With a 32-Bit Product
Block Moves from Data and Program
Space
TMS320C206, TMS320LC206 Peripherals:
– On-Chip 20-Bit Timer
– On-Chip Software-Programmable
Wait-State (0 to 7) Generator
– On-Chip Oscillator
– On-Chip Phase-Locked Loop (PLL)
– Six General-Purpose I/O Pins
– Full-Duplex Asynchronous Serial Port
(UART)
– Enhanced Synchronous Serial Port
(ESSP) With Four-Level-Deep FIFOs
Input Clock Options
– Options: Multiply-by-One, -Two, or -Four,
and Divide-by-Two ( 1, 2, 4, and 2)
Support of Hardware Wait States
Power Down IDLE Mode
IEEE 1149.1†-Compatible Scan-Based
Emulation
TMS320C206, TMS320LC206 100-Pin PZ
Package, Small Thin Quad Flat Package
(TQFP)
Industrial Temperature Version Planned,
(– 40°C to 85°C)
description
The Texas Instruments (TI) TMS320C206‡ and TMS320LC206‡ digital signal processors (DSPs) are
fabricated with static CMOS integrated-circuit technology. The architectural design is based upon that of the
TMS320C20x series and is optimized for low-power operation. The combination of advanced Harvard
architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the
operational flexibility and speed of the ’C206.
The ’C206 offers these advantages:
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Enhanced TMS320 architectural design for increased performance and versatility
Advanced integrated-circuit processing technology for increased performance
’C206 devices are pin- and code-compatible with ’C203 and ’F206 devices.
Source code for the ’C206 DSPs is software-compatible with the ’C1x and ’C2x DSPs and is upwardly
compatible with fifth-generation DSPs (’C5x)
New static-design techniques for minimizing power consumption and increasing radiation tolerance
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† IEEE Standard 1149.1 - 1990, IEEE Standard Test-Access Port
‡ Device numbers are hereafter referred to in the data sheet as ’C206, unless otherwise specified.
TI is a trademark of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
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1
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
V DD
A15
A14
A13
A12
V SS
A11
A10
A9
A8
V SS
A7
VDD5
A6
A5
A4
V SS
A3
A2
A1
A0
V SS
PS
IS
DS
PZ PACKAGE
( TOP VIEW )
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
EMU0
EMU1 / OFF
TCK
TRST
TDI
TMS
TDO
VSS
CLKR
FSR
DR
CLKX
VSS
FSX
DX
VDD5
50
49
48
47
46
45
44
43
42
41
40
39
†
TMS320C206
38
37
36
35
34
33
32
31
30
29
28
27
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VDD5
READY
VSS
R/W
STRB
RD
WE
BR
VSS
D15
D14
D13
D12
VSS
D11
VDD5
D10
D9
D8
D7
VSS
D6
D5
D4
D3
EXT8
MP/MC
DIV1
V DD
DIV 2
HOLDA
V DD5
IO2
IO3
PLLRS
V DD
CLKIN/X2
X1
VSS
CLKOUT1
V DD5
NMI
HOLD/INT1
INT2
INT3
VSS
D0
D1
D2
VSS
TOUT
TX
VSS
RX
IO0
IO1
XF
BIO
RS
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
† VDD5 pins 7, 16, 35, 50, 63, and 91 represent I/O supply voltage.
V DD
A15
A14
A13
A12
V SS
A11
A10
A9
A8
V SS
A7
VDD
A6
A5
A4
V SS
A3
A2
A1
A0
V SS
PS
IS
DS
PZ PACKAGE
( TOP VIEW )
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
EMU0
EMU1 / OFF
TCK
TRST
TDI
TMS
TDO
VSS
CLKR
FSR
DR
CLKX
VSS
FSX
DX
VDD
50
49
48
47
46
45
44
43
42
41
40
39
TMS320LC206
38
37
36
35
34
33
32
31
30
29
28
27
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
EXT8
MP/MC
DIV1
V DD
DIV 2
HOLDA
V DD
IO2
IO3
PLLRS
V DD
CLKIN/X2
X1
VSS
CLKOUT1
V DD
NMI
HOLD/INTI
INT2
INT3
VSS
D0
D1
D2
VSS
TOUT
TX
VSS
RX
IO0
IO1
XF
BIO
RS
76
77
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79
80
81
82
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84
85
86
87
88
89
90
91
92
93
94
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96
97
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100
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VDD
READY
VSS
R/W
STRB
RD
WE
BR
VSS
D15
D14
D13
D12
VSS
D11
VDD
D10
D9
D8
D7
VSS
D6
D5
D4
D3
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
device features
Table 1 shows the capacity of on-chip RAM and ROM, the number of serial and parallel I/O ports, the execution
time of one machine cycle, and the type of package with total pin count of the TMS320C206 and TMS320LC206
devices.
Table 1. Characteristics of the TMS320C206 and TMS320LC206 Processors
ON-CHIP MEMORY (16-BIT WORDS)
RAM
’x206
DEVICES
TMS320C206
ROM
FLASH
EEPROM
I/O PORTS
DATA
DATA/
PROG
PROG
PROG
SERIAL
PARALLEL
288†
4K + 256‡
32K
–
2
64K
288†
4K + 256‡
POWER
SUPPLY
(V)
CYCLE
TIME
(ns)
PACKAGE
TYPE WITH
PIN COUNT
5 (3.3 core)
25
100-pin TQFP
TMS320LC206
32K
–
2
64K
3.3
25
100-pin TQFP
† On-chip RAM space B1 (256 words) and B2 (32 words) can be used as data memory only.
‡ On-chip RAM space B0 (256 words) can be used either in data space or program space depending on the value of the CNF bit in the ST1 register.
On-chip SARAM (4K) can be mapped in program space, data space, or both.
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3
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
TMS320C206, TMS320LC206 Terminal Functions
TERMINAL
NAME
NO.
TYPE†
DESCRIPTION
DATA AND ADDRESS BUSES
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
41
40
39
38
36
34
33
32
31
29
28
27
26
24
23
22
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
74
73
72
71
69
68
67
66
64
62
61
60
58
57
56
55
Parallel data bus D15 [most significant bit (MSB)] through D0 [least significant bit (LSB)]. D15–D0 are
used to transfer data between the ’C206 devices and external data / program memory or I / O devices.
Placed in the high-impedance state when not outputting (RD, WE high) or when RS asserted. They also
go into the high-impedance state when OFF is active low.
I/O/Z
Parallel address bus A15 (MSB) through A0 (LSB). A15–A0 are used to address external data / program
memory or I / O devices. These signals go into the high-impedance state when OFF is active low.
O/Z
MEMORY CONTROL SIGNALS
PS
53
O/Z
Program-select. PS is always high unless low-level asserted for communicating to off-chip program
space. PS goes into the high-impedance state when OFF is active low.
DS
51
O/Z
Data-select. DS is always high unless low-level asserted for communicating to off-chip data space. DS
goes into the high-impedance state when OFF is active low.
IS
52
O/Z
I / O space select. IS is always high unless low-level asserted for communicating to I/O ports. IS goes into
the high-impedance state when OFF is active low.
READY
49
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Data-ready. READY indicates that an external device is prepared for the bus transaction to be completed.
If the external device is not ready (the external device pulls READY low), the ’C206 waits one cycle and
checks READY again. If READY is not used, it should be pulled high.
R/W
47
O/Z
Read / write. R / W indicates data transfer direction when communicating with an external device. R/W is
normally in read mode (high), unless low level is asserted for performing a write operation. R / W goes
into the high-impedance state when OFF is active low.
† I = input, O = output, Z = high impedance, PWR = power, GND = ground
4
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
TMS320C206, TMS320LC206 Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†
DESCRIPTION
MEMORY CONTROL SIGNALS (CONTINUED)
RD
45
O/Z
Read-select indicates an active, external read cycle. RD is active on all external program, data, and I / O reads.
RD goes into the high-impedance state when OFF is active low. To implement a glueless zero wait-state
memory interface, the inverted R/W signal can be used as the “read” signal in place of RD. The function of the
RD pin can be programmed to provide an inverted R/W signal instead of RD. The FRDN bit (bit 15) in the PMST
register controls this selection. FRDN=1 chooses R/W as the new “read” signal. FRDN=0 (at reset) chooses
RD as the “read” signal on pin 45.
WE
44
O/Z
Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15 – D0). Data
can be latched by an external device on the rising edge of WE. WE is active on all external program, data, and
I / O writes. WE goes into the high-impedance state when OFF is active low.
STRB
46
O/Z
Strobe. STRB is always high unless asserted low to indicate an external bus cycle. STRB goes into the
high-impedance state when OFF is active low.
O/Z
Bus-request. BR is asserted when a global data-memory access is initiated. BR goes into the high-impedance
state when OFF is active low.
MULTI-PROCESSING SIGNALS
BR
43
HOLDA
6
O/Z
Hold-acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and memory control lines are in the high-impedance state so that they are available to the
external circuitry for access of local memory. HOLDA goes into the high-impedance state when OFF is active
low.
XF
98
O/Z
External flag output (latched software-programmable signal). XF is used for signalling other processors in
multiprocessing configurations or as a general-purpose output pin. XF goes into the high-impedance state
when OFF is active low.
BIO
99
I
IO0
IO1
IO2
IO3
96
97
8
9
I / O/Z
Branch control input. When polled by the BCND pma,BIO instruction, ’C206 executes a branch to the
specified program memory address if BIO is low.
Software-controlled input / output by way of the asynchronous serial-port control register (ASPCR). At reset,
IO0–IO3 are configured as inputs. These pins can be used as general-purpose input / output pins or as
handshake control for the UART. IO0 – IO3 go into the high-impedance state when OFF is active low.
INITIALIZATION, INTERRUPTS, AND RESET OPERATIONS
RS
PLLRS
100
10
I
Reset. RS causes the ’C206 and ’LC206 to terminate execution and forces the program counter to zero.
When RS is brought high, execution begins at location 0 of program memory after 16 cycles. RS affects
various registers and status bits.
I
Phase locked loop reset. PLLRS resets the PLL to initiate PLL locking. At power up, both PLLRS and RS
should be active (low) to reset the DSP core and the PLL circuitry. The PLL can only be reset along with
the core as shown in Table 2. The state of the PLLRS is not applicable for 2 mode and should always be
tied high or low.
EXT8
1
I
Bootloader mode pin. EXT8 is latched to bit 3 (LEVEXT8) in the PMST register. The bootloader located in
ROM uses EXT8 to determine the type of boot method. If EXT8 is high, the enhanced ’C206 bootloader is
used. If EXT8 is low, the ’C203 style bootloader is used. Refer to the TMS320C20x User’s Guide (literature
number SPRU127) for more details regarding the ’C203 style bootloader.
MP/MC
2
I
Microprocessor/microcomputer mode select. If MP/MC is low, the on-chip ROM memory is mapped into
program space. When MP/MC is high, the device accessess off-chip memory. This pin is only sampled at
RESET, and its value is latched into bit 0 of the PMST register.
NMI
17
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the interrupt-mode bit
(INTM) or the interrupt-mask register (IMR). When NMI is activated, the processor traps to the appropriate
vector location. If NMI is not used, it should be pulled high.
HOLD/INT1
18
I
HOLD and INT1 share the same pin. Both are treated as interrupt signals. If the MODE bit is 0 in the interrupt
control register (ICR), hold logic can be implemented in combination with the IDLE instruction in software. At
reset, the MODE bit in ICR is zero, enabling the HOLD mode for the pin.
INT2
19
External user interrupts. INT2 and INT3 are prioritized and maskable by the IMR and the INTM. INT2 and INT3
I
20
INT3
can be polled and reset by way of the interrupt flag register (IFR).
† I = input, O = output, Z = high impedance, PWR = power, GND = ground
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5
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
TMS320C206, TMS320LC206 Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†
DESCRIPTION
OSCILLATOR, PLL, AND TIMER SIGNALS
TOUT
92
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT1
cycle wide. TOUT goes into the high-impedance state when OFF is active low.
CLKOUT1
15
O/Z
Master clock ouput. The CLKOUT1 high pulse signifies the logic phase while the low pulse signifies the latch
phase.
CLKIN/X2
X1
12
13
I
O
Input clock. CLKIN/X2 is the input clock to the device. As CLKIN, the pin operates as the external oscillator
clock input and as X2, the pin operates as the internal oscillator input with X1 being the internal oscillator output.
DIV1
DIV2
3
5
I
DIV1 and DIV2 are used to configure the on-chip PLL options, providing four clock modes (÷2, ×1, ×2, and ×4)
for a given input clock frequency. Refer to clock options in electrical characteristics section. Note that in the
divide-by-2 mode, the PLL is bypassed. DIV1 – DIV2 should not be changed unless the RS signal is active.
SERIAL PORT SIGNALS (SSP AND ASP)
CLKX
87
I/O
Transmit clock. CLKX is a clock signal for clocking data from the XSR (transmit shift register) to the DX
data-transmit pin. CLKX can be an input if the MCM bit in the synchronous serial-port control register (SSPCR)
is set to 0. CLKX can also be driven by the device at one-half of the CLKOUT1 frequency when
MCM = 1. If the serial port is not being used, CLKX goes into the high-impedance state when OFF is active
low. Value at reset is as an input.
CLKR
84
I
Receive clock. External clock signal for clocking data from the DR (data-receive) pin into the serial-port receive
shift register (RSR). CLKR must be present during serial-port transfers. If the serial port is not being used,
CLKR can be sampled as an input by IN0 bit of the SSPCR.
FSX
89
I/O
Frame synchronization pulse for transmit. The falling edge of the FSX pulse initiates the data-transmit process,
beginning the clocking of the SR. Following reset, FSX is an input. FSX can be selected by software to be an
output when the TXM bit in the serial control register, SSPCR, is set to 1. FSX goes into the high-impedance
state when OFF is active low.
FSR
85
I
Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive
process, beginning the clocking of the RSR. FSR goes into the high-impedance state when OFF is active low.
DX
90
O
Synchronous serial port (SSP) data transmit output. Serial data is transmitted from the transmit shift register
(XSR) through the DX pin. DX is in the high-impedance state when OFF is active low.
DR
86
I
Synchronous serial port (SSP) data receive input. Serial data is received in the receive shift register (RSR)
through the DR pin.
TX
93
O
Asynchronous serial port (ASP/UART) data transmit output pin
RX
95
I
Asynchronous serial port (ASP/UART) data receive pin
TEST SIGNALS
TRST
79
I
IEEE Standard 1149.1 (JTAG) test reset. TRST, when active high, gives the scan system control of the
operations of the device. If TRST is driven low, the device operates in its functional mode, and the test signals
are ignored. If the TRST pin is not driven, an external pulldown resistor must be used.
TCK
78
I
JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the
test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction register,
or selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.
TMS
81
I
JTAG test-mode select. TMS is clocked into the TAP controller on the rising edge of TCK.
TDI
80
I
JTAG test-data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
TDO
82
O /Z
JTAG test-data output. The contents of the selected register (instruction or data) are shifted out of TDO on the
falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress.
EMU0
76
I/O/Z
Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as an input / output
through the JTAG scan.
† I = input, O = output, Z = high impedance, PWR = power, GND = ground
6
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
TMS320C206, TMS320LC206 Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†
DESCRIPTION
TEST SIGNALS (CONTINUED)
I/O/Z
Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1 / OFF is used as an
interrupt to or from the emulator system and is defined as an input / output through the JTAG scan. When TRST
is driven low, this pin is configured as OFF. EMU1 / OFF, when active low, puts all output drivers in the
high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = 0
EMU0 = 1
EMU1 / OFF = 0
EMU1 / OFF
77
VDD5
7
16
35
50
63
91
PWR
5-V I/O power supply (Applicable for TMS320C206 only‡)
VDD
7
16
35
50
63
91
PWR
3.3-V I/O power supply (Applicable for ’LC206 only)
VDD
4
11
75
PWR
3.3-V core power supply (Applicable for both ’C206 and ’LC206 devices‡)
VSS
14
21
25
30
37
42
48
54
59
65
70
83
88
94
GND
Ground
SUPPLY PINS
† I = input, O = output, Z = high impedance, PWR = power, GND = ground
‡ For the ’C206, the 3.3-V and 5-V power supplies may be sequenced in any order.
Table 2. Resetting the DSP Core and PLL Circuitry
RS
PLLRS
CORE STATUS
PLL STATUS
0
0
Reset
Reset
0
1
Reset
Normal Operation
1
0
Normal Operation
Normal Operation§
1
1
Normal Operation
§ The PLL can only be reset along with the DSP core and peripherals.
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• HOUSTON, TEXAS 77251–1443
7
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
functional block diagram of the ’C206 internal hardware
Program Bus
DIV1
DIV2
IS
DS
PS
16
PC
PAR
MSTACK
RD
WE
NMI
RS
MP/MC
INT[1–3]
NPAR
Data Bus
Control
X1
CLKOUT1
CLKIN/X2
Program Bus
MUX
R/W
STRB
READY
BR
XF
HOLD
HOLDA
MUX
STACK 8 x 16
3
ROM
(32K
16)
MUX
A15–A0
16
PCTRL
16
16
16
16
16
MUX
D15–D0
16
16
Timer
Data Bus
16
Data Bus
16
16
3
9
AR0(16)
TCR
DP(9)
AR1(16)
TOUT
PRD
16
7
LSB
from
IR
16
16
AR2(16)
ARP(3)
16
9
AR4(16)
3
AR5(16)
ARB(3)
TREG0(16)
AR6(16)
ASP
Multiplier
AR7(16)
3
ASPCR
ISCALE (0–16)
PREG(32)
16
32
ADTR
TX
PSCALE (–6, 0, 1, 4)
MUX
IOSR
RX
32
I/O[0–3]
16
MUX
MUX
AR3(16)
3
TIM
16
32
BRD
4
16
MUX
SSP
ARAU(16)
MUX
32
SSPCR
CALU(32)
16
SDTR
Memory Map
Register
IMR (16)
SSPST
SSPMC
32
Data/Prog
SARAM
(4K x 16)
IFR (16)
GREG (16)
32
MUX
MUX
Data/Prog
DARAM
B0 (256 x 16)
Data
DARAM
B2 (32 x16)
C ACCH(16)
ACCL(16)
32
B1 (256 x16)
SSPCT
MUX
MUX
OSCALE (0–7)
16
16
Reserved
16
16
16
16
I/O-Mapped Registers
NOTES: A. Symbol descriptions appear in Table 3 and Table 4.
B. For clarity, the data and program buses are shown as single buses although they include address and data bits.
8
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Program Bus
DX
CLKX
FSX
DR
FSR
CLKR
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
Table 3. Legend for the ’C206 Internal Hardware Functional Block Diagram
SYMBOL
NAME
DESCRIPTION
ACC
Accumulator
32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities. ACCH is the accumulator high word; ACCL is the accumulator low word.
ADTR
Asynchronous
Data Transmit and
Receive Register
16-bit read/write register used to transmit data from/receive data into the asynchronous serial port. Note
that the ASP works with 8-bit data.
ARAU
Auxiliary Register
Arithmetic Unit
An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as
inputs and outputs.
ARB
Auxiliary Register
Pointer Buffer
See Table 4 for status register field definitions.
ARP
Auxiliary Register
Pointer
See Table 4 for status register field definitions.
ASP
Universal
Asynchronous
Receive/Transmit
ASP is the asynchronous serial port (UART).
ASPCR
Asynchronous
Serial-Port Control
Register
ASPCR controls the asynchronous serial-port operation This register contains bits for setting port modes,
enabling/disabling automatic baud-rate detection, selecting the number of stop bits, and configuring I/O
pins, etc.
AUX REGS
(AR0–AR7)
Auxiliary Registers
0–7
These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR.
BR
Bus Request
Signal
BR is asserted during access of the external global data memory space. READY is asserted to the device
when the global data memory is available for the bus transaction. BR can be used to extend the data memory
address space by up to 32K words.
BRD
Baud-Rate Divisor
Used to set the baud rate of the UART
C
Carry
Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.
CALU
Central Arithmetic
Logic Unit
32-bit-wide main arithmetic logic unit for the TMS320C20x core. The CALU executes 32-bit operations in
a single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and
provides status results to PCTRL.
DARAM
Dual Access RAM
If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable dual-access RAM (DARAM)
block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2 are
mapped to data memory space only, at addresses 0300–03FF and 0060–007F, respectively. Blocks 0 and
1 contain 256 words, while Block 2 contains 32 words.
DP
Data Memory
Page Pointer
See Table 4 for status register field definitions.
GREG
Global Memory
Allocation
Register
GREG specifies the size of the global data memory space.
IFR
Interrupt Flag
g
Register
The 7-bit IFR indicates that the ’C206 has latched an interrupt pulse from one of the seven maskable
interrupt sources.
IMR
Interrupt Mask
Register
IMR individually masks or enables the seven interrupts.
INT#
Interrupt Traps
A total of 32 interrupts by way of hardware and/or software are available.
IOSR
I / O Status
Register
IOSR detects current levels (and changes with inputs) on pins IO0 – IO3 and the status of UART.
IR
Instruction
Register
IR is the instruction register.
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SPRS065B – JUNE 1998 – REVISED JANUARY 1999
Table 3. Legend for the ’C206 Internal Hardware Functional Block Diagram (Continued)
SYMBOL
NAME
DESCRIPTION
ISCALE
Input Data-Scaling
Shifter
16-bit to 32-bit barrel left-shifter. ISCALE (ISFL) shifts incoming 16-bit data 0 to16 positions left, relative to
the 32-bit output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.
MPY
Multiplier
16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.
MSTACK
Micro Stack
MSTACK provides temporary storage for the address of the next instruction to be fetched when
program-address-generation logic is used to generate sequential addresses in data space.
MUX
Multiplexer
Multiplexes buses to a common input
NPAR
Next Program
Address Register
NPAR holds the program address to be driven out on the PAB on the next cycle.
OSCALE
Output
Data-Scaling
Shifter
32-bit to 16-bit barrel left-shifter. OSCALE (OSFL) shifts the 32-bit accumulator output 0 to 7 bits left for
quantization management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the
Data-Write Data Bus (DWEB).
PAR
Program Address
Register
PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
operations scheduled for the current bus cycle.
PC
Program Counter
PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.
PCTRL
Program
Controller
PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
PRD
Timer-Period
Register
PRD contains the 16-bit period that is loaded into the timer counter when the counter borrows or when the
reload bit is activated. Reset initializes the PRD to FFFFh.
PREG
Product Register
32-bit register holds results of 16 × 16 multiply.
PSCALE
Product-Scaling
Shifter
0-, 1- or 4-bit left shift or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE (PSFL) resides in the path
from the 32-bit product shifter and from either the CALU or the DWEB, and requires no cycle overhead.
SDTR
Synchronous Data
Transmit and
Receive Register
16-bit read/write register used to transmit data from/receive data into the synchronous serial port. This
register functions as the path to the transmit and receive FIFOs of the SSP.
SSP
Synchronous
Serial-Port
SSP is the synchronous serial-port.
SSPCR
Synchronous
Serial-Port Control
Register
SSPCR is the control register for selecting the serial port’s mode of operation.
SSPCT
Synchronous
Serial-Port
Counter Register
SSPCT is the synchronous serial-port counter register.
SSPMC
Synchronous
Serial-Port
Multichannel
Register
SSPMC is the synchronous serial-port multichannel register.
SSPST
Synchronous
Serial-Port
Status Register
SSPST is the synchronous serial-port status register.
STACK
Stack
STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The ’C20x stack is 16-bit wide and eight-level deep.
TCR
Timer-Control
Register
TCR contains the control bits that define the divide-down ratio, start / stop the timer, and reload the period.
Also contained in TCR is the current count in the prescaler. Reset initializes the timer divide-down ratio
to 0 and starts the timer.
10
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Table 3. Legend for the ’C206 Internal Hardware Functional Block Diagram (Continued)
SYMBOL
NAME
DESCRIPTION
TIM
Timer-Counter
Register
TIM contains the current 16-bit count of the timer. Reset initializes the TIM to FFFFh.
TREG
Temporary
Register
16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.
architectural overview
The ’C206 advanced Harvard-type architecture maximizes the processing power by maintaining two separate
memory bus structures—program and data—for full-speed execution. The multiple buses allow data and
instructions to be read simultaneously. Instructions support data transfers between the two spaces. This
architecture permits coefficients stored in program memory to be read in RAM, eliminating the need for a
separate coefficient RAM. This, coupled with a four-instruction deep pipeline, allows the
TMS320C206/TMS320LC206 to execute most instructions in a single cycle.
status and control registers
Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved
and restored for subroutines.
The load-status register (LST) instruction is used to write to ST0 and ST1 (except the INTM bit which is not
affected by the LST instruction). The store-status register (SST) instruction is used to read from the ST0 and
ST1. The individual bits of these registers can be set or cleared by the SETC and CLRC instructions. Figure 1
shows the organization of status registers ST0 and ST1, indicating all status bits contained in each. Several bits
in the status registers are reserved and are read as logic 1s. See Table 4 for status-register field definitions.
ST0
ST1
15 – 13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARP
OV
OVM
1
INTM
15 – 13
12
11
10
9
8
7
6
5
4
3
2
1–0
ARB
CNF
TC
SXM
C
1
1
1
1
XF
1
1
PM
DP
Figure 1. Status and Control Register Organization
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DIGITAL SIGNAL PROCESSORS
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status and control registers (continued)
Table 4. Status Register Field Definitions
FIELD
FUNCTION
ARB
Auxiliary register pointer buffer. Whenever the ARP is loaded, the old ARP value is copied to the ARB except during an LST
instruction. When the ARB is loaded by an LST #1 instruction, the same value is also copied to the ARP.
ARP
Auxiliary register pointer. ARP selects the auxiliary register (AR) to be used in indirect addressing. When the ARP is loaded,
the old ARP value is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect
addressing, and by the LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST
#1 instruction is executed.
C
Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In
these cases, the ADD can only set and the SUB only reset the carry bit, but cannot affect it otherwise. The single-bit shift and
rotate instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided
to branch on the status of C. C is set to 1 on a reset.
CNF
On-chip RAM configuration-control bit. If CNF is set to 0, the reconfigurable data DARAM blocks are mapped to data space;
otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1
instructions. RS sets the CNF to 0.
DP
Data memory page pointer. The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct
memory address of 16 bits. DP can be modified by the LST and LDP instructions.
INTM
Interrupt-mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are
disabled. INTM is set and reset by the SETC INTM and CLRC INTM instructions. INTM has no effect on the nonmaskable RS
and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 when a maskable interrupt is
acknowledged or when RS is asserted.
OV
Overflow-flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the ALU. Once an overflow occurs, the
OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV.
OVM
Overflow-mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the
accumulator is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC
instructions set and reset this bit, respectively. LST also can be used to modify the OVM.
PM
Product-shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the
PREG output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is
left-shifted by four bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of six bits, sign-extended. Note that the PREG contents remain unchanged. The shift takes place when transferring the contents of the PREG
to the ALU. PM is loaded by the SPM and LST #1 instructions. PM is cleared by RS.
SXM
Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling
shifter. SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS
instruction suppresses sign extension regardless of SXM. SXM is set by the SETC SXM and reset by the CLRC SXM
instructions, and can be loaded by the LST #1. SXM is set to 1 by reset.
TC
Test /control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by
BIT or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function
of the two MSBs of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return
instructions can execute, based on the condition of TC.
XF
XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF and reset by
the CLRC XF instructions. XF is set to 1 by reset.
central processing unit
The TMS320C206/TMS320LC206 central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x16-bit
parallel multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at
the outputs of both the accumulator and the multiplier. This section describes the CPU components and their
functions. The functional block diagram shows the components of the CPU.
12
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input scaling shifter
The TMS320C206/TMS320LC206 provides a scaling shifter with a 16-bit input connected to the data bus and
a 32-bit output connected to the CALU. This shifter operates as part of the path of data coming from program
or data space to the CALU, and requires no cycle overhead. It is used to align the 16-bit data coming from
memory to the 32-bit CALU. This is necessary for scaling arithmetic as well as aligning masks for logical
operations.
The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;
the MSBs may either be filled with zeros or sign-extended, depending upon the value of the SXM bit
(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the
instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment
operations specific to that point in the code. The TREG base shift allows the scaling factor to adapt to the
performance of the system.
multiplier
The TMS320C206/TMS320LC206 uses a 16 x16-bit hardware multiplier that is capable of computing a signed
or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply
unsigned) instruction, perform a signed-multiply operation. That is, two numbers being multiplied are treated
as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers
associated with the multiplier:
D
D
a 16-bit temporary register (TREG) that holds one of the operands for the multiplier, and
a 32-bit product register (PREG) that holds the product.
Four product shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 5.
Table 5. PSCALE Product Shift Modes
PM
SHIFT
00
no shift
DESCRIPTION
01
left 1
Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
10
left 4
Removes the extra four sign bits generated in a 16 x13 2s-complement multiply to a produce a Q31
product when using the multiply by a 13-bit constant
11
right 6
Product fed to CALU or data bus with no shift
Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY). A four-bit shift is used in conjunction with the MPY instruction with a short
immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by
a 13-bit number. Finally, the output of PREG can be right-shifted six bits to enable the execution of up to
128 consecutive multiply/accumulates without the possibility of overflow.
The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the second operand (also from the data bus). A multiplication can also be
performed with a 13-bit immediate operand when using the MPY instruction. A product is then obtained every
two cycles. For efficient implementation of multiple products, or multiple sums of products, the CPU provides
pipelining of the TREG load operation with certain CALU operations which use the PREG. These operations
include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG to ACC and shift TREG input data
to next address in data memory (LTD); and subtract PREG from ACC (LTS).
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multiplier (continued)
Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle
multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient
addresses are generated by program-address generation (PAGEN), while the data addresses are generated
by data-address generation (DAGEN). This allows the repeated instruction to access the values sequentially
from the coefficient table and step through the data in any of the indirect addressing modes.
The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
discard the oldest sample.
The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision
arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed
data-memory location, with the result placed in PREG. This allows the operands of greater than 16 bits to be
broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The
SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the
multiplier for squaring a data-memory value.
After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register
(PREG). The product from PREG can be transferred to the CALU or to data memory through the SPH (store
product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data
memory passes through the PSCALE shifter and is therefore, affected by the product-shift mode value defined
by the PM bits in the ST1 register. This is important when saving PREG in an interrupt-service routine context
save as the PSCALE shift effects cannot be modeled in the restore operation. PREG can be cleared by
executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG
and executing a MPY #1 instruction. The high half is then loaded using the LPH instruction.
central arithmetic logic unit
The TMS320C206/TMS320LC206 CALU implements a wide range of arithmetic and logical functions, the
majority of which execute in a single clock cycle. This arithmetic/logic unit (ALU) is referred to as central to
differentiate it from a second ALU used for indirect address generation called the auxiliary register arithmetic
unit (ARAU). Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC)
where additional operations, such as shifting, may occur. Data that is input to the CALU can be scaled by
ISCALE when coming from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from
the multiplier.
The CALU is a general-purpose ALU unit that operates on 16-bit words taken from data memory or derived from
immediate instructions. In addition to arithmetic operations, the CALU can perform Boolean operations,
facilitating the bit-manipulation ability required for a high-speed controller. One input to the CALU is always
provided from the accumulator, and the other input can be provided from the product register (PREG) of the
multiplier or from the output of the scaling shifter (that has been read from data memory or from the ACC). After
the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.
The TMS320C206/TMS320LC206 supports floating-point operations for applications requiring a large dynamic
range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the
accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter
for the LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions.
These instructions are useful in floating-point arithmetic where denormalization of a number is required (that
is, floating-point to fixed-point conversion). They are also useful in the implementation of automatic-gain control
(AGC) at the input of a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data
memory based on the value contained in the four LSBs of TREG.
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central arithmetic logic unit (continued)
The CALU overflow-saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. Setting
the OVM status-register bit selects the overflow-saturation mode. When the CALU is in the overflow-saturation
mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive
or the most negative value representable in the accumulator, depending upon the direction of the overflow. The
value of the accumulator upon saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM
(overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the
accumulator without modification. (Logical operations cannot result in overflow.)
The CALU can execute a variety of branch instructions that depend on the status of the CALU and accumulator.
These instructions can be executed conditionally, based on various combinations of the associated status bits.
For overflow management, these conditions include the OV (branch on overflow) and EQ (branch on
accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the
ability to branch to an address specified by the accumulator (computed goto). Bit-test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
The CALU also has a carry bit (bit 9 of status register ST1) that facilitates efficient computation of
extended-precision products and additions or subtractions. The carry bit is also useful in overflow management.
The carry bit is affected by the following operations:
D
Additions to and subtractions from the accumulator:
C = 0: When the result of a subtraction generates a borrow.
When the result of an addition does not generate a carry. (Exception: When the ADD instruction is
used with a shift of 16 and no carry is generated, the ADD instruction has no effect on C.)
C = 1: When the result of an addition generates a carry.
When the result of a subtraction does not generate a borrow. (Exception: When the SUB instruction
is used with a shift of 16 and no borrow is generated, the SUB instruction has no effect on C.)
D
Single-bit shifts and rotations of the accumulator value. During a left shift or rotation, the most significant
bit of the accumulator is passed to C; during a right shift or rotation, the least significant bit is passed to C.
Note: the carry bit is set to “1” on a hardware reset.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use
the previous value of carry in their addition/subtraction operation.
accumulator
The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage
in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is
performed while the data is being transferred to the data bus for storage. The contents of the accumulator
remain unchanged. When the post-scaling shifter is used on the high word of the accumulator (bits 16–31), the
MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0–15). When the postscaling
shifter is used on the low word, the LSBs are zero-filled.
The SFL and SFR (in-place one-bit shift to the left / right) instructions and the ROL and ROR (rotate to the
left/right) instructions implement shifting or rotating of the accumulator contents through the carry bit. The SXM
bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an
arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift,
shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected
by the SXM bit and behaves the same way in both cases, shifting out the MSB and shifting in a zero. Repeat
(RPT) instructions can be used with the shift and rotate instructions for multiple-bit shifts.
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auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The ’C206 provides a register file containing eight auxiliary registers (AR0–AR7). The auxiliary registers are
used for indirect addressing of the data memory or for temporary data storage. For indirect data-memory
addressing, the address of the desired memory location is placed into the selected auxiliary register. These
registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0
through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from
data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents
of these registers can also be stored in data memory or used as inputs to the CALU.
The auxiliary register file (AR0 – AR7) is connected to the auxiliary register arithmetic unit (ARAU). The ARAU
can autoindex the current auxiliary register while the data-memory location is being addressed. Indexing either
by ±1 or by the contents of the AR0 register can be performed. As a result, accessing tables of information does
not require the CALU for address manipulation; thus, the CALU is free for other operations in parallel.
memory
The ’C206 implements three separate address spaces for program memory, data memory, and I/O. Each space
accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to 32K words at the
top of the address range can be defined to be external global-memory in increments of powers of two, as
specified by the contents of the global-memory allocation register (GREG). Access to global memory is
arbitrated using the global-memory bus request (BR) signal.
On the ’C206, the first 96 (0 – 5Fh) data-memory locations are allocated for memory-mapped registers or
reserved. This memory-mapped register space contains various control and status registers including those for
the CPU.
The on-chip memory of the ’C206 includes 544 x 16 words of dual-access RAM (DARAM), 4K x 16 single-access
RAM (SARAM), and 32K x 16 program ROM memory. Table 6 shows the mapping of these memory blocks and
the appropriate control bits and pins. Figure 2 shows the effects of the memory control pin MP/MC and the
control bit CNF on the mapping of the respective memory spaces to on-chip or off-chip. The PON and DON bits
select the SARAM (4K) mapping in program, data, or both. See Table 9 for details on the PMST register, the
PON bit, and the DON bit. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program
and data space. The SARAM addresses (800h in data and 8000h in program memory) are accessible in
external memory space, if the on-chip SARAM is not enabled.
At reset, if the MP/MC pin is held high, the device starts in microprocessor mode and branches to 0000h in
external program space. The MP/MC pin status is latched in the PMST register (bit 0). As long as this bit remains
high, the device is in microprocessor mode. PMST register bits can be read and modified in software. If bit 0
is cleared to 0, the device enters microcomputer mode and program memory addresses from 0000h to 7FFFh
map to on-chip ROM.
If the MP/MC pin is held low during reset, the device starts in microcomputer mode and branches to 0000h in
the on-chip ROM mapped in program space. The on-chip ROM could either contain the bootloader or
customer-specific application code which is then executed.
The on-chip data memory blocks B0 and B1 are 256 16 words each. When CNF = 0, B0 is mapped in data
space at addresses 0200–02FFh. When CNF = 1, B0 is mapped in program space at addresses
0FF00–0FFFFh. The B1 block is always mapped in data space at addresses 0300–03FFh, and B2 block is
always mapped in a data space at addresses 60–7Fh.
16
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
memory (continued)
Hex
PROGRAM
Hex
PROGRAM
Hex
DATA
Hex
0000
Interrupt Vectors
0000
Interrupt Vectors
0000
Memory-Mapped
0000
-------------
-------------
Registers and
Bootloader Code
-------------
External
I/O SPACE
005F
Reserved
Addresses
A-law table
0060
On-Chip
-------------
007F
DARAM B2
µ- law table
0080
Reserved
-------------
01FF
0200
7EFF
Unused
On-Chip DARAM
B0 (CNF = 0)
------------Reserved For
7FFF
ROM Test Code
02FF
8000
On-Chip
0300
On-Chip
SARAM 4K
SARAM 4K
03FF
DARAM B1
Internal
(PON = 1)
Internal
(PON = 1)
0400
7FFF
8000
8FFF
Reserved
7F00
On-Chip
External
(PON = 0)
9000
8FFF
(CNF = 1)
External
(PON = 0)
External
I/O Space
Reserved
07FF
9000
0800
On-Chip
SARAM 4K
Internal
(DON = 1)
External
17FF
External
FDFF
FE00
External
FDFF
Reserved
FE00
(DON = 0)
1800
External
Reserved
(CNF = 1)
(CNF = 1)
FEFF
External
External
FF00
Reserved
FEFF
(CNF = 0)
FEFF
(CNF = 0)
FF00
On-Chip DARAM
FF00
On-Chip DARAM
FF0F
Test
B0 (CNF = 1)
B0 (CNF = 1)
FF10
On-Chip I/O
External
External
FFFF
(CNF = 0)
Microprocessor Mode
(MP/MC = 1)
FFFF
for
Peripheral
(CNF = 0)
FFFF
FFFF
Registers
Microcomputer Mode
(MP/MC = 0)
On-chip ROM†
† Standard ROM devices will come with boot code and the A-law, µ-law table.
Figure 2. TMS320C206/TMS320LC206 Memory Map Configurations
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17
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
memory (continued)
Table 6. TMS320C206/TMS320LC206 Memory Map
DESCRIPTION OF MEMORY BLOCK
256 x 16 word dual-access RAM (DARAM) (B0)
DATA MEMORY
ADDRESS
PROG MEMORY
ADDRESS
MP/MC†
DON†
PON†
CNF
BIT†
200h – 2FFh
–
x
x
x
0
256 x 16 word DARAM (B0)
–
FF00h – FFFFh
x
x
x
1
256 x 16 word DARAM (B1)
300h – 3FFh
–
x
x
x
x
32 x 16 word DARAM (B2)
60h – 7Fh
–
x
x
x
x
32K x 16 word on-chip program memory (ROM)
–
0000h – 7FFFh
0
x
x
x
32K x 16 word external program memory
–
0000h – 7FFFh
1
x
x
x
32K x 16 word external program memory,
if CNF=0 and MP/MC =0
–
8000h – FFFFh
0
x
0
0
External program memory, if CNF=1
–
8000h – FDFFh
0
x
0
1
4K x 16 word on-chip SARAM (data)
800h – 17FFh
4K x 16 word on-chip SARAM (program)
4K x 16 word program and data on-chip SARAM‡
x
1
0
x
–
8000h – 8FFFh
x
0
1
x
800h – 17FFh
8000h – 8FFFh
x
1
1
x
x
0
0
x
4K x 16 word on-chip SARAM
not available
not available
† The “x” denotes a “don’t care” condition.
‡ The single 4K on-chip SARAM block is accessible from both data and program memory space.
on-chip ROM
The mask-programmable ROM is located in program memory space. Customers can arrange to have this ROM
programmed with contents unique to any particular application. The ROM is enabled or disabled by the state
of the MP/MC control input upon resetting the device. In microcomputer mode (MP/MC = 0), the ROM occupies
the block of program memory from addresses 0000–7FFFh. (Note: the last 100h words, 7F00–7FFFh, are
reserved for test.) When in microprocessor mode (MP/MC = 1), addresses 0000h–7FFFh are located in the
device’s external program memory space.
bootloader
A bootloader is available in the standard ’C206/’LC206 on-chip ROM. This bootloader can be used to
automatically transfer user code from an external source to program memory at power up. If MP/MC of the
device is sampled low during a hardware reset, execution begins at location 0000h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program. User code can be transferred to
the DSP program memory using any one of the following options:
D
D
D
D
D
8-bit transfer through the Synchronous Serial Port (SSP)
8-bit transfer through the Asynchronous Serial Port (ASP)
8/16-bit external EPROM
8/16-bit parallel port mapped to I/O space address 0001h of the DSP
Warm boot option
The standard ’C206/’LC206 on-chip ROM also contains the A-law, µ-law table in addition to the bootloader. (The
A-law table starts at 0400h, and the µ-law table starts at 0500h.)
18
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
bootloader (continued)
The required option is chosen by the state of the EXT8 pin during power up and with the help of a boot routine
selection (BRS) word, which is read from I/O address 0000h. The lower 8 bits of the word specify which
bootloader option is to be executed. The BRS word uses a 6-bit source address field (SRCE_AD) in parallel
EPROM mode and a 6-bit entry address field (ADDR_bb) in warm boot mode to arrive at the starting address
of the code. The state of the MP/MC and EXT8 pins is copied into the PMST register. Table 7 describes the
bootloader options that can be chosen by the EXT8 pin. Table 8 describes the options available in the ’C206
enhanced bootloader and the bit values of the BRS word to select modes.
Table 7. Bootloader Pin Configurations
MP/MC
EXT8
OPTION
MODES
0
0
Use ’C203 style bootloader
1
0
1
Use ’C206 enhanced bootloader
2 to 9
1
0
EXT8 has no effect
–
1
1
EXT8 has no effect
–
Table 8. ’C206 Bootloader Options
BOOTLOADER OPTION
MODE
xxxxxxxx
BRS WORD AT I/O 0000h
xxx0
0000
8-bit serial SSP, ext FSX, CLKX
2
xxxxxxxx
xxx0
0100
16-bit serial SSP, ext FSX, CLKX
3
xxxxxxxx
xxx0
1000
8-bit parallel I/O
4
xxxxxxxx
xxx0
1100
16-bit parallel I/O
5
xxxxxxxx
xxx1
0000
8-bit ASP/UART
6
xxxxxxxx
SRCE
AD01
8-bit EPROM
7
xxxxxxxx
SRCE
AD10
16-bit EPROM
8
xxxxxxxx
ADDR
bb11
Warm boot
9
Figure 3 shows the program flow of the ’C206 bootloader. See the TMS320C20x User’s Guide (literature
number SPRU127) for more information about the ’C206 bootloader.
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
bootloader (continued)
Start
C203
Style
Loader?
(LEVEXT8 = 0?)
Yes
Perform
C203 Style
Bootloading
Warm Boot
(2 LSBs = 11)
No
No
Serial/
Parallel
Load?
(2 LSBs of
BRS = 00?)
No
Yes
Perform UART/
Asynchronous
Serial Load
Yes
8-Bit
EPROM?
(2 LSBs = 01?)
No
Yes
UART/
Asynchronous
Serial Load?
(Bit 4 of
BRS = 1?)
16-Bit
EPROM?
(2 LSBs = 10?)
Yes
Perform
16-Bit
EPROM
Perform
8-Bit
EPROM
Yes
Parallel
I/O Load?
(Bit 3 of
BRS = 1?)
No
Perform 8-Bit
Synchronous
Serial Load
(Bit 2 of BRS = 0)
Yes
8-Bit
Synchronous
Serial Load?
(Bit 2 of
BRS = 0?)
Yes
8-Bit
Parallel I/O?
(Bit 2 of
BRS = 0?)
Yes
Perform
8-Bit
Parallel I/O
No
Perform 16-Bit
Synchronous
Serial Load
(Bit 2 of BRS = 1)
Figure 3. ’C206 Bootloader Program Flow
20
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No
Perform 16-Bit
Parallel I/O
(Bit 2 of BRS = 1)
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
on-chip registers
The TMS320C206/TMS320LC206 includes three registers mapped to internal data space and sixteen (16)
registers mapped to internal I/O space. Table 9 describes these registers and shows their respective addresses.
In the table, DS† refers to data space and IS† refers to I/O space.
Table 9. On-Chip Memory and I/O Mapped Registers
NAME
ADDRESS†
VALUE AT
RESET‡
DESCRIPTION
IMR
[email protected]
0000h
Interrupt-mask register. This seven-bit register individually masks or enables the seven
interrupts. Bit 0 shares external interrupt INT1 and HOLD. INT2 and INT3 share bit 1. Bit 2
ties to the timer interrupt, TINT. Bits 3 and 4, RINT and XINT, respectively, are for the
synchronous serial port, SSP. Bit 5, TXRXINT, shares the transmit and receive interrupts for
the asynchronous serial port, ASP. Bit 6 is reserved for monitor-mode-emulation operations
and must always be set to 0 except in conjunction with emulation-monitor operations. Bits
7 – 15 are not used in the TMS320C206/TMS320LC206. IMR is set to 0 at reset. A bit value
of 0 disables an interrupt, and a value of 1 enables an interrupt.
GREG
[email protected]
0000h
Global-memory allocation register. This 8-bit register specifies the size of the global memory
space. GREG is set to 0 at reset.
0000h
Interrupt-flag register. The seven-bit IFR indicates that the TMS320C206/TMS320LC206
has latched an interrupt from one of the seven maskable interrupts. Bit 0 shares external
interrupt INT1 and HOLD. INT2 and INT3 share bit 1. Bit 2 ties to the timer interrupt, TINT.
Bits 3 and 4, RINT and XINT, respectively, are for the SSP. Bit 5, TXRXINT, shares the
transmit and receive interrupts for the ASP. Bit 6 is reserved for monitor-mode-emulation
operations and must always be set to 0 except in conjunction with emulation-monitor
operations. Writing a 1 to the respective interrupt bit clears an active flag and the respective
pending interrupt. Writing a 1 to an inactive flag has no effect. Bits 7 – 15 are not used in the
TMS320C206/TMS320LC206. IFR is set to 0 at reset.
IFR
[email protected]
Bit 0 - Processor mode status bit (PMST). latches in the MP/MC pin at reset. This bit can
be written to configure microprocessor (1) or microcomputer mode (0). Bits 1 and 2
configure the SARAM mapping either in program memory, data memory, or both. At
reset, these bits are 11, the SARAM is mapped in both program and data space.
DON (bit 2)
PON (bit 1)
0
0
- SARAM not mapped, address in external
memory
0
1
- SARAM in on-chip program memory at 0x8000h
1
0
- SARAM in on-chip data memory at 0x800h
1
1
- SARAM in on-chip program and data memory
(reset value)
Bit 3 - LEVEXT8 bit. This bit captures the status of the EXT8 pin 1 at reset only.
Bit 15 – Fast RD, FRDN. This bit provides software control to select an inverted R/W
signal in place of the RD signal (pin 45). This is intended to help achieve zero wait-state
memory interface with slow memory devices. At reset, this bit is 0 and selects RD as the
signal at pin 45. If the FRDN bit is written with a 1, the read signal at pin 45 is replaced
with the inverted R/W signal.
PMST
[email protected]
0006h
CLK
[email protected]
0000h
CLKOUT1 on or off. At reset, this bit is configured as a zero for the CLKOUT1 pin to be active.
If this bit is a 1, CLKOUT1 pin is turned off.
0000h
Interrupt-control register. This register is used to determine which interrupt is active since
INT1 and HOLD share the same interrupt vector as INT2 and INT3. A portion of this register
is for mask/unmask (similar to IFR). At reset, all bits are zeroed, thereby allowing the HOLD
mode to be enabled. The MODE bit is used by the hold-generating circuit to determine if a
HOLD or INT1 is active.
ICR
[email protected]
† DS = data space and IS = input/output ports
‡ ‘x’ indicates undefined or value based on the pin levels at reset.
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
on-chip registers (continued)
Table 9. On-Chip Memory and I/O Mapped Registers (Continued)
NAME
ADDRESS†
VALUE AT
RESET‡
SDTR
[email protected]
xxxxh
Synchronous serial port (SSP) transmit and receive register
SSPCR
[email protected]
0030h
Synchronous serial-port control register. This register controls serial-port operation as
defined by the register bits.
DESCRIPTION
SSPST
[email protected]
0000h
Synchronous serial-port status register
SSPMC
[email protected]
0000h
Synchronous serial-port multichannel register
ADTR
[email protected]
xxxxh
Asynchronous serial port (ASP) transmit and receive register
ASPCR
[email protected]
0000h
Asynchronous serial-port control register. This register controls the asynchronous
serial-port operation.
IOSR
[email protected]
18xxh
I/O-status register. IOSR is used for detecting current levels on pins IO0 – IO3 when defined
as inputs.
BRD
[email protected]
0001h
Baud-rate generator. 16-bit register used to determine baud rate of UART. No data is
transmitted/received if BRD is zero.
TCR
[email protected]
0000h
Timer-control register. This ten-bit register contains the control bits that define the
divide-down ratio, start/stop the timer, and reload the period. Also contained in this register
is the current count in the prescaler. Reset initializes the timer divide-down ratio to 0 and
starts the timer.
PRD
[email protected]
FFFFh
Timer-period register. This 16-bit register contains the 16-bit period that is loaded into the
timer counter when the counter borrows or when the reload bit is activated. Reset initializes
the PRD to 0xFFFF.
TIM
[email protected]
FFFFh
Timer-counter register. This 16-bit register contains the current 16-bit count of the timer.
Reset initializes the TIM to 0xFFFF.
SSPCT
[email protected]
0000h
Synchronous serial-port counter register.
WSGR
[email protected]
0FFFh
Wait-state generator register. This register contains 12 control bits to enable 0 to 7 wait
states to program, data, and I/O space. Reset initializes WSGR to 0x0FFFh.
† DS = data space and IS = input/output ports
‡ ‘x’ indicates undefined or value based on the pin levels at reset.
external interface
The ’C206 devices can address up to 64K × 16 words of memory (or registers) in each of the program, data,
and I / O spaces. On-chip memory, when enabled, occupies some of this off-chip range. In data space, the high
32K words can be mapped dynamically either locally or globally using the GREG register as described in the
TMS320C20x User’s Guide (literature number SPRU127). A data-memory access that is mapped as global
asserts BR low ( with timing similar to the address bus).
The CPU of the ’C206 schedules a program fetch, data read, and data write on the same machine cycle. This
is because from on-chip memory, the CPU can execute all three of these operations in the same cycle. However,
the external interface multiplexes the internal buses to one address and one data bus. The external interface
sequences these operations to complete first the data write, then the data read, and finally the program read.
The ’C206 supports a wide range of system-interfacing requirements. Program, data, and I/O address spaces
provide interface to memory and I/O, thus maximizing system throughput. The full 16-bit address and data bus,
along with the PS, DS, and IS space-select signals, allow addressing of 64K 16-bit words in each of the three
spaces.
I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O
address space using the processor’s external address and data buses in the same manner as memory-mapped
devices.
22
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
external interface (continued)
The ’C206 external parallel interface provides various control signals to facilitate interfacing to the device. The
R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal
provides a timing reference for all external cycles. For convenience, the device also provides the RD and the
WE output signals, which indicate a read and a write cycle, respectively, along with timing information for those
cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to
the ’C206.
Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When
transactions are made with slower devices, the ’C206 processor waits until the other device completes its
function and then signals the processor via the READY line. Once a ready indication is provided back to the
’C206 from the external device, execution continues.
The bus request (BR) signal is used in conjunction with the other ’C206 interface signals to arbitrate external
global memory accesses. Global memory is external data-memory space in which the BR signal is asserted
at the beginning of the access. When an external global memory device receives the bus request, it responds
by asserting the READY signal after the global memory access is arbitrated and the global access is completed.
The TMS320C206/TMS320LC206 supports zero-wait-state reads on the external interface. However, to avoid
bus conflicts, writes take two cycles. This allows the TMS320C206/TMS320LC206 to buffer the transition of the
data bus from input to output (or from output to input) by a half cycle. In most systems,
TMS320C206/TMS320LC206 ratio of reads to writes is significantly large to minimize the overhead of the extra
cycle on writes.
Wait states can be generated when accessing slower external resources. The wait states operate on
machine-cycle boundaries and are initiated either by using READY or by using the software wait-state
generator. READY can be used to generate any number of wait states.
interrupts and subroutines
The ’C206 implements three general-purpose interrupts, INT3–INT1, along with reset (RS), and the
nonmaskable interrupt (NMI), which are available for external devices to request the attention of the processor.
Internal interrupts are generated by the synchronous serial port (RINT and XINT), by the timer (TINT), UART,
(TXRXINT), and by the software-interrupt (TRAP, INTR and NMI) instructions. Interrupts are prioritized, with RS
having the highest priority, (followed by NMI), and UART having the lowest priority. Additionally, any interrupt
except RS and NMI can be individually masked with a dedicated bit in the interrupt mask register (IMR) and can
be cleared, set, or tested using its own dedicated bit in the interrupt flag register (IFR). The reset and NMI
functions are not maskable.
All interrupt vector locations are on two-word boundaries so that branch instructions can be accommodated in
those locations if desired.
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction completes execution. This mechanism applies to
instructions that are repeated (using the RPT instruction) and to instructions that become multicycle because
of wait states.
Each time an interrupt is serviced or a subroutine is entered, the program counter (PC) is pushed onto an internal
hardware stack, providing a mechanism for returning to the previous context. The stack contains eight locations,
allowing interrupts or subroutines to be nested up to eight levels deep.
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
reset
The ’C206 utilizes an active-low reset (RS and PLLRS) input for the core, peripherals, and PLL.
A minimum pulse duration of six cycles ensures that an asynchronous reset signal properly resets the device.
The ’C206 fetches its first instruction approximately sixteen cycles after the rising edge of RS.
The reset action halts all operations whether they are complete or not; therefore, the state of the system and
its data cannot be maintained through the reset operation. For example, if the device is writing to an external
resource when the reset is initiated, the write is aborted; this may corrupt the contents or configuration of system
resources. Therefore, it is necessary to reinitialize the system after a reset.
power-down modes
The ’C206 implements a power-down mode in which the ’C206 core enters a dormant state and dissipates less
power. The power-down mode is invoked by executing an IDLE instruction. While the device is in power-down
mode, the on-chip peripherals continue to operate.
While the ’C206 is in a power-down mode, all of its internal contents are maintained; this allows operation to
continue unaltered when the power-down mode is terminated. All CPU activities are halted when the IDLE
instruction is executed, but the CLKOUT1 pin remains active depending on the status of the CLKOUT1-pin
control register (CLK). The peripheral circuits continue to operate, allowing peripherals such as serial ports and
timers to take the CPU out of its powered-down state. The power-down mode, when initiated by an IDLE
instruction, is terminated upon receipt of an interrupt.
software-controlled wait-state generator
Due to the fast cycle time of the ’C206 devices, it is often necessary to operate with wait states to interface with
external logic or memory. For many systems, one wait state is adequate.
The software wait-state generator can be programmed to generate between zero and seven wait states for a
given space. Software wait states are configured by way of the wait-state generator register (WSGR). The
WSGR includes four 3-bit fields to configure wait states for the following external memory spaces: data space
(DSWS), upper program space (PSUWS), lower program space (PSLWS), and I/O space (ISWS). The
wait-state generator enables wait states for a given memory space based on the value of the corresponding
three bits, regardless of the condition of the READY signal. The READY signal can be used to generate
additional wait states. All bits of the WSGR are set to 1 at reset, so that the device can operate from slow memory
immediately after reset.The WSGR register (shown in Figure 4) resides at I/O port FFFCh. See Table 7 for the
bit settings of the various fields in the WSGR for wait-state programming. See Table 8 for a description of the
various WSGR fields.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Reserved
ISWS
DSWS
PSUWS
PSLWS
0
R/W–111
R/W–111
R/W–111
R/W–111
LEGEND:
0 = Always read as zeros, R = Read Access, W= Write Access, – n = Value after reset
Figure 4. TMS320C206/TMS320LC206 Wait-State Generator Register ( WSGR)
24
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0
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
software-controlled wait-state generator (continued)
Table 10. TMS320C206/TMS320LC206 Wait-State(s) Programming
ISWS, DSWS, PSUWS, OR PSLWS BITS
WAIT STATES FOR I / O, DATA, OR PROGRAM
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Table 11. ’C206 Wait-State Generator Register ( WSGR)
BITS
NAME
DESCRIPTION
2–0
PSLWS
External program-space wait states (lower). PSLWS determines that between 0 to 7 wait states are applied to
all reads and writes to off-chip lower program-space address (0h–7FFFh). The memory cycle can be further
extended using the READY signal. The READY signal does not override the wait states generated by PSLWS.
These bits are set to 1 (active) by reset (RS).
5–3
PSUWS
External program-space wait states (upper). PSUWS determines that between 0 to 7 wait states are applied to
all reads and writes to off-chip upper program space address (8000h–0FFFFh). The memory cycle can be further
extended using the READY signal. The READY signal does not override the wait states generated by PSUWS.
These bits are set to 1 (active) by reset (RS).
8–6
DSWS
External data space wait states. DSWS determines that between 0 to 7 wait states are applied to all reads and
writes to off-chip data space. The memory cycle can be further extended using the READY signal. The READY
signal does not override the wait states generated by DSWS. These bits are set to 1 (active) by reset (RS).
11 – 9
ISWS
External input / output-space wait state. ISWS determines that between 0 to 7 wait states are applied to all reads
and writes to off-chip I / O space. The memory cycle can be further extended using the READY signal. The READY
signal does not override the wait states generated by ISWS. These bits are set to 1 (active) by reset (RS).
15 – 12
Reserved
Don’t care. Always read as 0.
timer
The TMS320C206/TMS320LC206 includes a 20-bit timer, implemented with a 16-bit main counter (TIM), and
a 4-bit prescaler counter (PSC). The count values are written into the 16-bit period register (PRD), and the 4-bit
timer divide-down register (TDDR). The TIM and the PRD are 16-bit registers mapped to I/O space, while the
PSC and the TDDR are 4-bit fields of the timer control register (TCR). The TCR is an I/O mapped register which
also includes other control bits for the timer (see Table 9).
When the timer is started, the TIM is loaded with the contents of PRD, and the PSC is loaded with the contents
of the TDDR. The PSC is decremented by one at each CLKOUT1 cycle. On the CLKOUT1 cycle after the PSC
decrements to zero, the PSC is reloaded with the contents of TDDR, and the TIM is decremented by one. That
is, every (TDDR+1) CLKOUT1 cycles, the TIM is decremented by one. When the TIM decrements to zero, it
is reloaded with the contents of the PRD on the following CLKOUT1 cycle, and a new timer interval begins.
Therefore, the timer interrupt rate is defined as follows: CLKOUT1 frequency/[(TDDR+1) (PRD+1)].
The timer can be used to generate periodic CPU interrupts based on CLKOUT1. Each time the TIM decrements
to zero, a timer interrupt (TINT) is generated, and a pulse equal to the duration of a CLKOUT1 cycle is generated
on the TOUT pin. The timer provides a convenient means of performing periodic I/O, context switching , or other
functions.
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
input clock options
The TMS320C206/TMS320LC206 provides multiple clock modes of divide-by-two and multiply-by-one, -two,
or -four. The clock mode configuration cannot be dynamically changed without executing another reset.
synchronous serial port
A full duplex (bidirectional) 8-bit or 16-bit on-chip synchronous serial port provides direct communication with
serial devices such as codecs, serial A / D (analog-to-digital) converters, and other serial systems. The interface
signals are compatible with codecs and many other serial devices. The serial port can also be used for
intercommunication between processors in multiprocessing applications.
For data transmission, three signals are necessary to connect the transmit pins of the transmitting device with
the receive pins of the receiving device. The transmitted serial data signal (DX) sends the actual data. The
transmit frame synchronization signal (FSX) initiates the transfer (at the beginning of the packet), and the
transmit clock signal (CLKX) clocks the bit transfer. The corresponding pins on the receive device are DR, FSR
and CLKR, respectively. When the serial port is not used, the device can be configured to shut off the serial port
internal clocks, allowing the device to run in a lower power mode of operation.
The continuous mode of the synchronous serial port (SSP) provides operation that, once initiated, requires no
further frame synchronization pulses when transmitting at maximum frequency. Both receive and transmit
operations have a four-word deep first-in first-out (FIFO) buffer. The advantage of having a FIFO is to alleviate
the CPU from being loaded with the task of servicing a receive- or transmit-data operation after each word,
allowing a continuous communications stream of 16-bit data packets. The maximum transmission rate for both
transmit and receive operations is CPU divided by two or CLKOUT1(frequency)/2. Therefore, the maximum rate
at 40 million instructions per second (MIPS) is 20 megabits per second (Mbps). The serial port is fully static and
functions at arbitrarily low clocking frequencies. When the serial ports are in reset, the device can be configured
to shut off the serial port internal clocks, allowing the device to run in a lower power mode of operation.
The synchronous serial port also has capabilities to facilitate a glueless interface with multiple codecs and other
peripherals. The SSP registers are complemented with three registers—status register (SSPST), multichannel
register (SSPMC), and counter register (SSPCT). The SSPST includes control and status bits. Additional
control bits are provided in the SSPMC to control the multichannel and prescaled clocks/frames features. The
SSPCT register contains the two 8-bit prescalers to provide variable synchronous shift clock (CLKX) and frame
syncs (FSX).
asynchronous serial port
The asynchronous serial port is full-duplexed and transmits and receives 8-bit data only. For transmit and
receive operations, there is one start bit and one or two configurable stop bits by way of the asynchronous
serial-port control register (ASPCR). Double-buffering of transmit / receive data is used in all modes. Baud rate
generation is accomplished via the baud rate divisor (BRD) register. This port also features an
auto-baud-detection logic.
scan-based emulation
TMS320C206/TMS320LC206 devices incorporate scan-based emulation logic for code-development and
hardware-development support. Scan-based emulation allows the emulator to control the processor in the
system without the use of intrusive cables to the full pinout of the device. The scan-based emulator
communicates with the ’C206 by way of the IEEE 1149.1 compatible (JTAG) interface. The TMS320C206 and
TMS320LC206 DSPS, like the TMS320F206, TMS320C203, and TMS320LC203, do not include boundary
scan. The scan chain of these devices is useful for emulation function only.
26
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DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
multiprocessing
The flexibility of the ’C206 allows configurations to satisfy a wide range of system requirements; the device can
be used in a variety of system configurations, including but not limited to the following:
D
D
D
D
A standalone processor
A multiprocessor with devices in parallel
A slave/host multiprocessor with global memory space
A peripheral processor interfaced via processor-controlled signals to another device
For multiprocessing applications, the ’C206 has the capability of allocating global memory space and
communicating with that space via the BR and ready control signals. Global memory is data memory shared
by more than one device. Global-memory access must be arbitrated. The 8-bit memory-mapped global memory
allocation register (GREG) specifies part of the ’C206’s data memory as global external memory. The contents
of the register determine the size of the global memory space. If the current instruction addresses an operand
within that space, BR is asserted to request control of the bus. The length of the memory cycle is controlled
by the READY line.
The TMS320C206/TMS320LC206 supports direct memory access (DMA) to its local (off-chip) program,
data, and I/O spaces. Two signals, HOLD/INT1, an input to the device, and HOLDA, an output, control this
mechanism. The Hold feature is enabled by clearing the mode bit in the interrupt control register (ICR
[email protected]). When the Hold feature is enabled, and HOLD/INT1 is asserted, executing an IDLE instruction
puts the address, data, and memory control signals (PS, DS, IS, STRB, R/W, and WE) in a high-impedance
state. When this occurs, the HOLDA signal is asserted, acknowledging that the processor has relinquished
control of the external bus. It is important to note that when the mode bit is set to one, the Hold feature is
disabled, and the HOLD/INT1 pin functions as a general-purpose interrupt (INT1). That is, when the Hold
feature is disabled, and HOLD/INT1 is asserted, the IDLE instruction does not cause the memory interface
signals to enter the high-impedance mode, and it does not cause the assertion of HOLDA. At reset, the mode
bit is cleared to zero, and the Hold feature is enabled.
instruction set
The ’C206 microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control. Source code for the ’C1x and ’C2x DSPs is upwardly compatible with the ’C206.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles
an instruction requires to execute varies depending upon whether the next data operand fetch is from internal
or external memory. Highest throughput is achieved by maintaining data memory on chip and using either
internal or fast external program memory.
addressing modes
The ’C206 instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and
register.
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data-memory-page pointer (DP) to form the 16-bit data memory
address. Thus, in the direct-addressing mode, data memory is effectively paged with a total of 512 pages, each
page containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0– AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
addressing modes (continued)
There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by either adding
or subtracting the contents of AR0, single-indirect addressing with no increment or decrement, and bit-reversed
addressing [used in Fast Fourier Transforms (FFTs)] with increment or decrement. All operations are performed
on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary
register and ARP can be modified.
In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There
are two types of immediate addressing: long and short. In short-immediate addressing, the data is contained
in a portion of the bits in a single-word instruction. In long-immediate addressing, the data is contained in the
second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need
to be stored or used more than once during the course of program execution, such as initialization values,
constants, etc.
The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference
to a specific register, or implicitly, with instructions that intrinsically reference certain registers. In either case,
operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand
address or immediate value.
repeat feature
The repeat function can be used with instructions (as defined in Table 13) such as multiply/accumulates (MAC
and MACD), block moves (BLDD and BLPD), I/O transfers (IN/OUT ), and table read/writes (TBLR/TBLW).
These instructions, although normally multicycle, are pipelined when the repeat feature is used, and they
effectively become single-cycle instructions. For example, the table-read instruction may take three or more
cycles to execute, but when the instruction is repeated, a table location can be read every cycle.
When using the repeat feature, the repeat counter (RPTC) is loaded with the addressed-data-memory location
if direct or indirect addressing is used, or an 8-bit immediate value if short-immediate addressing is used. The
RPTC register is loaded by the RPT instruction. This results in a maximum of N + 1 executions of a given
instruction when RPTC is loaded with N. RPTC is cleared by reset. Once a repeat instruction (RPT ) is decoded,
all interrupts, including NMI (except reset), are masked until the completion of the repeat loop.
instruction set summary
This section summarizes the opcodes of the instruction set for the ’C206 digital signal processor. This
instruction set is a superset of the ’C1x and ’C2x instruction sets. The instructions are arranged according to
function and are alphabetized by mnemonic within each category. The symbols in Table 12 are used in the
instruction set summary table (Table 13). T he Texas Instruments ’C20x assembler accepts ’C2x instructions.
The number of words that an instruction occupies in program memory is specified in column 3 of Table 13.
Several instructions specify two values separated by a slash mark ( / ) for the number of words. In these cases,
different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies
one word when the operand is a short-immediate value or two words if the operand is a long-immediate value.
The number of cycles that an instruction requires to execute is in column 3 of Table 13. All instructions are
assumed to be executed from internal program memory (RAM) and internal data dual-access memory. The
cycle timings are for single-instruction execution, not for repeat mode.
28
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
instruction set summary (continued)
Table 12. Opcode Symbols
SYMBOL
DESCRIPTION
A
Address
ACC
Accumulator
ACCB
Accumulator buffer
ARx
Auxiliary register value (0 – 7)
BITx
4-bit field specifies which bit to test for the BIT instruction
BMAR
Block-move address register
DBMR
Dynamic bit-manipulation register
I
Addressing-mode bit
II...II
Immediate operand value
INTM
Interrupt-mode flag bit
INTR#
Interrupt vector number
K
Constant
PREG
Product register
PROG
Program memory
RPTC
Repeat counter
SHF, SHFT
3/4-bit shift value
TC
Test-control bit
Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO.
T P Meaning
TP
00
01
10
11
BIO low
TC = 1
TC = 0
None of the above conditions
TREGn
Temporary register n (n = 0, 1, or 2)
ZLVC
4-bit field representing the following conditions:
Z:
ACC = 0
L:
ACC < 0
V:
Overflow
C:
Carry
A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a 4-bit mask field. A 1 in the
corresponding mask bit indicates that the condition is being tested. The second 4-bit field (bits 4 – 7) indicates the state of the
conditions designated by the mask bits as being tested. For example, to test for ACC ≥ 0, the Z and L fields are set while the
V and C fields are not set. The next 4-bit field contains the state of the conditions to test. The Z field is set to indicate testing
of the condition ACC = 0, and the L field is reset to indicate testing of the condition ACC ≥ 0. The conditions possible with these
8 bits are shown in the BCND and CC instructions. To determine if the conditions are met, the 4-LSB bit mask is ANDed with
the conditions. If any bits are set, the conditions are met.
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
instruction set summary (continued)
Table 13. TMS320C206/TMS320LC206 Instruction Set Summary
’x20x
MNEMONIC
OPCODE
WORDS/
CYCLES
MSB
Absolute value of accumulator
1/1
1011
1110
0000
0000
Add to accumulator with shift
1/1
0010
SHFT
IADD
RESS
Add to high accumulator
1/1
0110
0001
IADD
RESS
Add to accumulator short immediate
1/1
1011
1000
KKKK
KKKK
Add to accumulator long immediate with shift
2/2
1011
1111
1001
SHFT
ADDC
Add to accumulator with carry
1/1
0110
0000
IADD
RESS
ADDS
Add to low accumulator with sign extension suppressed
1/1
0110
0010
IADD
RESS
ADDT
Add to accumulator with shift specified by T register
1/1
0110
0011
IADD
RESS
ADRK
Add to auxiliary register short immediate
1/1
0111
1000
KKKK
KKKK
AND with accumulator
1/1
0110
1110
IADD
RESS
AND immediate with accumulator with shift
2/2
AND immediate with accumulator with shift of 16
2/2
Add P register to accumulator
1/1
ABS
ADD
AND
APAC
DESCRIPTION
B
Branch unconditionally
2/4
BACC
Branch to address specified by accumulator
1/4
BANZ
Branch on auxiliary register not zero
2/4/2
Branch if TC bit ≠ 0
2/4/2
Branch if TC bit = 0
2/4/2
Branch on carry
2/4/2
Branch if accumulator ≥ 0
2/4/2
Branch if accumulator > 0
2/4/2
Branch on I/O status low
2/4/3
Branch if accumulator ≤ 0
2/4/2
Branch if accumulator < 0
2/4/2
Branch on no carry
2/4/2
BCND
Branch if no overflow
30
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LSB
1011
1111
1011 SHFT
16-Bit Constant
1011
1110
1000
16-Bit Constant
1011
0111
1011
1110
0000
0001
0100
1001 IADD RESS
Branch Address
1110
0010
0000
0111
1011 IADD RESS
Branch Address
1110
0001
0000
0000
Branch Address
1110
0010
0000
0000
Branch Address
1110
0011
0001
0001
Branch Address
1110
0011
1000
Branch Address
1110
0011
0000
0100
Branch Address
1110
0000
0000
0000
Branch Address
1110
0011
1100
Branch Address
1110
0011
0100
1100
1100
0100
Branch Address
1110
0011
0000
0001
Branch Address
1110
0011
0000
Branch Address
0010
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
instruction set summary (continued)
Table 13. TMS320C206/TMS320LC206 Instruction Set Summary (Continued)
’x20x
MNEMONIC
BCND
WORDS/
CYCLES
DESCRIPTION
Branch if accumulator ≠ 0
2/4/2
Branch on overflow
2/4/2
Branch if accumulator = 0
2/4/2
OPCODE
MSB
1110
LSB
0011
0000
1000
Branch Address
1110
0011
0010
0010
Branch Address
1110
0011
1000
1000
Branch Address
BIT
Test bit
1/1
0100
BITx
IADD
RESS
BITT
Test bit specified by TREG
1/1
0110
1111
IADD
RESS
1010
1000
IADD
RESS
Block move from data memory to data memory source immediate
2/3
BLDD†
Block move from data memory to data memory destination immediate
2/3
BLPD
Block move from program memory to data memory
2/3
CALA
Call subroutine indirect
1/4
CALL
Call subroutine
CC
Conditional call subroutine
CLRC
2/4
2/4/2
Branch Address
1010
1001
IADD
RESS
Branch Address
1010
0101
IADD
RESS
Branch Address
1011
1110
0011
0000
0111
1010
IADD
RESS
Routine Address
1110
10TP
ZLVC
ZLVC
Routine Address
Configure block as data memory
1/1
1011
1110
0100
0100
Enable interrupt
1/1
1011
1110
0100
0000
Reset carry bit
1/1
1011
1110
0100
1110
Reset overflow mode
1/1
1011
1110
0100
0010
Reset sign-extension mode
1/1
1011
1110
0100
0110
Reset test / control flag
1/1
1011
1110
0100
1010
Reset external flag
1/1
1011
1110
0100
1100
CMPL
Complement accumulator
1/1
1011
1110
0000
0001
CMPR
Compare auxiliary register with auxiliary register AR0
1/1
1011
1111
0100
01CM
DMOV
Data move in data memory
1/1
0111
0111
IADD
RESS
IDLE
Idle until interrupt
1/1
1011
1110
0010
0010
IN
Input data from port
2/2
1010
1111
IADD
RESS
16BIT
I/O
PORT
ADRS
INTR
Software-interrupt
1/4
1011
1110
011K
KKKK
Load accumulator with shift
1/1
0001
SHFT
IADD
RESS
Load accumulator long immediate with shift
2/2
1111
1000
SHFT
LACC
1011
Zero low accumulator and load high accumulator
1/1
0110
† In ’C20x devices, the BLDD instruction cannot be used with memory-mapped registers IMR, IFR, and GREG.
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16-Bit Constant
1010
IADD
RESS
31
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
instruction set summary (continued)
Table 13. TMS320C206/TMS320LC206 Instruction Set Summary (Continued)
’x20x
MNEMONIC
LACL
LACT
LAR
OPCODE
WORDS/
CYCLES
MSB
Load accumulator immediate short
1/1
1011
1001
KKKK
Zero accumulator
1/1
1011
1001
0000
0000
Zero low accumulator and load high accumulator
1/1
0110
1010
IADD
RESS
Zero low accumulator and load low accumulator with no sign extension
1/1
0110
1001
IADD
RESS
Load accumulator with shift specified by T register
1/1
0110
1011
IADD
RESS
Load auxiliary register
1/2
0000
0ARx
IADD
RESS
Load auxiliary register short immediate
1/2
1011
0ARx
KKKK
KKKK
1011
1111
0000
1ARx
DESCRIPTION
LSB
KKKK
Load auxiliary register long immediate
2/2
Load data-memory page pointer
1/2
0000
1101
IADD
RESS
Load data-memory page pointer immediate
1/2
1011
110P
AGEP
OINT
Load high-P register
1/1
0111
0101
IADD
RESS
Load status register ST0
1/2
0000
1110
IADD
RESS
Load status register ST1
1/2
0000
1111
IADD
RESS
LT
Load TREG
1/1
0111
0011
IADD
RESS
LTA
Load TREG and accumulate previous product
1/1
0111
0000
IADD
RESS
LTD
Load TREG, accumulate previous product, and move data
1/1
0111
0010
IADD
RESS
LTP
Load TREG and store P register in accumulator
1/1
0111
0001
IADD
RESS
LTS
Load TREG and subtract previous product
1/1
0111
0100
IADD
RESS
MAC
Multiply and accumulate
2/3
0010
IADD
RESS
MACD
Multiply and accumulate with data move
2/3
Load auxiliary register pointer
1/1
1000
1011
1000
1ARx
Modify auxiliary register
1/1
1000
1011
IADD
RESS
Multiply (with TREG, store product in P register)
1/1
0101
0100
IADD
RESS
Multiply immediate
1/1
110C
KKKK
KKKK
KKKK
MPYA
Multiply and accumulate previous product
1/1
0101
0000
IADD
RESS
MPYS
Multiply and subtract previous product
1/1
0101
0001
IADD
RESS
MPYU
Multiply unsigned
1/1
0101
0101
IADD
RESS
NEG
Negate accumulator
1/1
1011
1110
0000
0010
NMI
Nonmaskable interrupt
1/4
1011
1110
0101
0010
NOP
No operation
1/1
1000
1011
0000
0000
NORM
Normalize contents of accumulator
1/1
1010
0000
IADD
RESS
OR with accumulator
1/1
0110
1101
IADD
RESS
1011
1111
1100
SHFT
LDP
LPH
LST
MAR
MPY
16-Bit Constant
1010
16-Bit Constant
1010
0011
IADD
RESS
16-Bit Constant
OR immediate with accumulator with shift
2/2
OR immediate with accumulator with shift of 16
2/2
OUT
Output data to port
2/3
0000
16BIT
1100
I/O
IADD
PORT
RESS
ADRS
PAC
Load accumulator with P register
1/1
1011
1110
0000
0011
OR
32
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16-Bit Constant
1011
1110
1000
0010
16-Bit Constant
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
instruction set summary (continued)
Table 13. TMS320C206/TMS320LC206 Instruction Set Summary (Continued)
’x20x
MNEMONIC
WORDS/
CYCLES
DESCRIPTION
OPCODE
MSB
LSB
POP
Pop top of stack to low accumulator
1/1
1011
1110
0011
0010
POPD
Pop top of stack to data memory
1/1
1000
1010
IADD
RESS
PSHD
Push data-memory value onto stack
1/1
0111
0110
IADD
RESS
PUSH
Push low accumulator onto stack
1/1
1011
1110
0011
1100
RET
Return from subroutine
1/4
1110
1111
0000
0000
RETC
Conditional return from subroutine
1/4/2
1110
11TP
ZLVC
ZLVC
ROL
Rotate accumulator left
1/1
1011
1110
0000
1100
ROR
Rotate accumulator right
1/1
1011
1110
0000
1101
Repeat instruction as specified by data-memory value
1/1
0000
1011
IADD
RESS
Repeat instruction as specified by immediate value
1/1
1011
1011
KKKK
KKKK
SACH
Store high accumulator with shift
1/1
1001
1SHF
IADD
RESS
SACL
Store low accumulator with shift
1/1
1001
0SHF
IADD
RESS
SAR
Store auxiliary register
1/1
1000
0ARx
IADD
RESS
SBRK
Subtract from auxiliary register short immediate
1/1
0111
1100
KKKK
KKKK
Set carry bit
1/1
1011
1110
0100
1111
Configure block as program memory
1/1
1011
1110
0100
0101
Disable interrupt
1/1
1011
1110
0100
0001
Set overflow mode
1/1
1011
1110
0100
0011
Set test / control flag
1/1
1011
1110
0100
1011
Set external flag XF
1/1
1011
1110
0100
1101
RPT
SETC
Set sign-extension mode
1/1
1011
1110
0100
0111
SFL
Shift accumulator left
1/1
1011
1110
0000
1001
SFR
Shift accumulator right
1/1
1011
1110
0000
1010
SPAC
Subtract P register from accumulator
1/1
1011
1110
0000
0101
SPH
Store high-P register
1/1
1000
1101
IADD
RESS
SPL
Store low-P register
1/1
1000
1100
IADD
RESS
SPM
Set P register output shift mode
1/1
1011
1111
IADD
RESS
SQRA
Square and accumulate
1/1
0101
0010
IADD
RESS
SQRS
Square and subtract previous product from accumulator
1/1
0101
0011
IADD
RESS
Store status register ST0
1/1
1000
1110
IADD
RESS
Store status register ST1
1/1
1000
1111
IADD
RESS
Store long immediate to data memory
2/2
1110
IADD
RESS
Subtract from accumulator long immediate with shift
2/2
Subtract from accumulator with shift
1/1
0011
SHFT
Subtract from high accumulator
1/1
0110
Subtract from accumulator short immediate
1/1
1011
SST
SPLK
SUB
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1010
16-Bit Constant
1011
1111
1010
SHFT
16-Bit Constant
IADD
RESS
0101
IADD
RESS
1010
KKKK
KKKK
33
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
instruction set summary (continued)
Table 13. TMS320C206/TMS320LC206 Instruction Set Summary (Continued)
’x20x
MNEMONIC
WORDS/
CYCLES
DESCRIPTION
OPCODE
MSB
LSB
SUBB
Subtract from accumulator with borrow
1/1
0110
0100
IADD
RESS
SUBC
Conditional subtract
1/1
0000
1010
IADD
RESS
SUBS
Subtract from low accumulator with sign extension suppressed
1/1
0110
0110
IADD
RESS
SUBT
Subtract from accumulator with shift specified by TREG
1/1
0110
0111
IADD
RESS
TBLR
Table read
1/3
1010
0110
IADD
RESS
TBLW
Table write
1/3
1010
0111
IADD
RESS
TRAP
Software interrupt
1/4
1011
1110
0101
0001
Exclusive-OR with accumulator
1/1
0110
1100
IADD
RESS
Exclusive OR immediate with accumulator with shift
Exclusive-OR
2/2
1111
1101
SHFT
Exclusive OR immediate with accumulator with shift of 16
Exclusive-OR
2/2
Zero low accumulator and load high accumulator with rounding
1/1
XOR
ZALR
1011
16-Bit Constant
1011
1110
1000
0011
16-Bit Constant
0110
1000
IADD
RESS
development support
Texas Instruments offers an extensive line of development tools for the ’x20x generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and
fully integrate and debug software and hardware modules.
The following products support development of ’x20x-based applications:
Software Development Tools:
Assembler/Linker
Simulator
Optimizing ANSI C Compiler
Application Algorithms
C/Assembly Debugger and Code Profiler†
Hardware Development Tools:
Emulator XDS510 (supports ’x20x multiprocessor system debug)
The TMS320 Family Development Support Reference Guide (literature number SPRU011) contains
information about development-support products for all TMS320 family member devices, including
documentation. Refer to this document for further information about TMS320 documentation or any other
TMS320 support products from Texas Instruments. There is also an additional document, the TMS320
Third-Party Support Reference Guide (literature number SPRU052), which contains information about
TMS320-related products from other companies in the industry. To receive copies of TMS320 literature, contact
the Literature Response Center at 800/477-8924.
See Table 14 for complete listings of development-support tools for the ’C20x. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
† The Texas Instruments C Source Debugger, Revision 1.00.01, is not compatible with ’C206/’LC206 silicon revisions. Contact TI for more information
regarding the most recent debugger revision and release.
XDS510 is a trademark of Texas Instruments Incorporated.
34
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
development support (continued)
Table 14. ’C206 Development-Support Tools
DEVELOPMENT TOOL
PLATFORM
PART NUMBER
Software
Compiler/Assembler/Linker
SPARC, HP
TMDS3242555-08
Compiler/Assembler/Linker
PC-DOS, OS/2
TMDS3242855-02
Assembler/Linker
PC-DOS, OS/2
TMDS3242850-02
Simulator
PC-DOS, WIN
TMDS3245851-02
Simulator
SPARC
TMDS3245551-09
Digital Filter Design Package
PC-DOS
DFDP
Debugger/Emulation Software
PC-DOS, OS/2, WIN
TMDS3240120
Debugger/Emulation Software
SPARC
TMDS3240620
Code Composer Debugger
Windows
CCMSP5XWIN
Hardware
’C20x Evaluation Module
PC-DOS
XDS510XL Emulator
PC-DOS, OS/2
XDS510WS Emulator
SPARC
TMDS32600XX
TMDS00510
TMDS00510WS
device and development-support tool nomenclature
To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part
numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP,
and TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX
and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes
(TMX/ TMDX) through fully qualified production devices/tools (TMS/TMDS). This development flow is defined
below.
Device Development Evolutionary Flow:
TMX
Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS
Fully qualified production device
Support Tool Development Evolutionary Flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been fully characterized, and the quality and reliability
of the device have been fully demonstrated. Texas Instruments standard warranty applies.
Predictions show that prototype devices ( TMX or TMP) will have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
WIN and Windows are trademarks of Microsoft Corporation.
Code Composer is a trademark of Go DSP Inc.
SPARC is a trademark of SPARC International, Inc.
PC-DOS and OS/2 are trademarks of International Business Machines Corp.
HP is a trademark of Hewlett-Packard Company.
XDS510XL and XDS510WS are trademarks of Texas Instruments Incorporated.
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35
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
device and development-support tool nomenclature (continued)
because their expected end-use failure rate is still undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, PZ) and temperature range (for example, A). The following figures provide a legend for
reading the complete device name for any TMS320 family member.
TMS 320 (B) C 206 PZ
PREFIX
TMX = Experimental device
TMP = Prototype device
TMS = Qualified device
(A)
TEMPERATURE RANGE (DEFAULT: 0°C TO 70°C)
L = 0°C to 70°C†
A = – 40°C to 85°C
PACKAGE TYPE‡
PZ = 100-pin plastic TQFP
PN = 80-pin TQFP
DEVICE FAMILY
320 = TMS320 family
BOOTLOADER OPTION§
DEVICE
’20x DSP
TECHNOLOGY
C = CMOS (5-V, 3.3-V core)
E = CMOS EPROM
F = CMOS Flash EEPROM
LC = Low-Voltage CMOS (3.3 V)
VC = Low-Voltage CMOS (3 V)
203§
206
209
† For TMS320C206PZ, TMS320LC206PZ devices with this temperature range, L is not printed on package.
‡ TQFP = Thin Quad Flat Package
§ The TMS320C203 is a bootloader device without the B option.
Figure 5. TMS320x20x Device Nomenclature
documentation support
Extensive documentation supports all of the TMS320 family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; complete user’s guides for all devices and
development-support tools; and hardware and software applications.
For general background information on DSPs and TI devices, see the three-volume publication Digital Signal
Processing Applications With the TMS320 Family (literature numbers SPRA012, SPRA016, and SPRA017).
Also available is the Calculation of TMS320C20x Power Dissipation application report (literature number
SPRA088).
For further information regarding the ’C206 and ’LC206, please refer to the TMS320C20x User’s Guide
(literature number SPRU127) and the TMS320 DSP Development Support Reference Guide (literature number
SPRU011F).
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to
update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides
access to information pertaining to the TMS320 family, including documentation, source code, and object code
for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
To send comments regarding the ’C206/’LC206 datasheet (SPRS065B), use the [email protected].ti.com
email address, which is a repository for feedback. For questions and support, contact the Product Information
Center listed at the back of the datasheet.
36
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V
Supply voltage range, VDD5 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V
Output voltage range, ’LC206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V
Output voltage range, ’C206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Operating free-air temperature range, TA (TMS320C206PZ, TMS320LC206PZ) . . . . . . . . . . . 0°C to 70°C
(TMS320C206PZA, TMS320LC206PZA) . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions‡
MIN
NOM
MAX
UNIT
VDD
VDD5
Supply voltage
3.3-V operation
2.7
3.3
3.6
V
Supply voltage (’C206 only)
5-V operation (3.3-V core)
4.5
5
5.5
V
VSS
Supply voltage
High-level input voltage, 3.3 V
VIH
High-level
g
input voltage,
g ,5V
(3.3-core)
0
CLKIN/X2
2.5
RS, CLKR, CLKX, RX
2.3
TRST, TCK
2.5
All other inputs
2.0
CLKIN/X2
3.0
RS, CLKR, CLKX, RX
2.3
TRST, TCK
3.0
All other inputs
2.0
CLKIN/X2
VIL
Low level input voltage
Low-level
RS CLKR,
RS,
CLKR CLKX,
CLKX RX
All other inputs
V
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD5 + 0.3
VDD5 + 0.3
VDD5 + 0.3
VDD5 + 0.3
V
V
’C206
– 0.3
0.6
V
’LC206
– 0.3
0.6
V
’C206
– 0.3
0.6
V
’LC206
– 0.3
0.6
V
’C206
– 0.3
0.6
V
’LC206
– 0.3
0.7
V
IOH
High-level output current
– 300
µA
IOL
Low-level output current
2
mA
TA
Operating free
free-air
air temperature
TMS320C206PZ, TMS320LC206PZ
0
70
– 40
85
°C
TMS320C206PZA,
TMS320LC206PZA
‡ Refer to the mechanical data package page for thermal resistance values, ΘJA (junction-to-ambient) and ΘJC (junction-to-case).
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37
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
VOH
VOL
g
High-level
output voltage
Low-level
output voltage
TEST CONDITIONS
MIN
3.3-V operation, IOH = MAX
All other inputs/X1
2.4/2.0
5-V operation, IOH = MAX
All other inputs/X1
2.4/2.0
IOZ
0.6
0.6
IDD
Output current,
3.3-V/5-V operation,VO = VDD or 0 V
high-impedance
g
state (off-state)
–Device running
with external clock
in PLLx1 mode
–Dummy code
execution in B0 RAM
(NOPS and MACD)
3.3-V operation
fCLKOUT = 40 MHz
’LC206
5-V/3.3-V
fCLKOUT = 40 MHz
’C206
UNIT
V
5-V operation, IOL = MAX
Input current
Supply
Su
ly current
MAX
3.3-V operation, IOL = MAX
3.3-V/5-V operation, VI = VDD or 0 V
II
TYP
CLKIN/X2
–300
300
FSX, FSR,
CLKR, CLKX,
TRST
(with internal
pulldown)
– 10
250
PLLRS, TCK
TDI, TMS
–200
10
EMU0, EMU1
(with internal
pullup)
–200
10
All other inputs
– 10
10
EMU0, EMU1
(with internal
pullup)
–200
10
FSX, FSR,
CLKR, CLKX,
TRST
(with internal
pull down)
10
–10
250
All other
3-state outputs
–10
10
V
µA
µA
µ
50
CPU – (3.3 V)
45
I/O - (5V)
10
mA
Ci
Input
capacitance
15
pF
Co
Output
capacitance
15
pF
38
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CT
IOH
Where:
IOL
IOH
VLOAD
CT
=
=
=
=
2 mA (all outputs)
300 µA (all outputs)
1.5 V
40-pF typical load-circuit capacitance
Figure 6. Test Load Circuit
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39
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
signal-transition levels
The data in this section is shown for the 3.3-V and 5-V versions of the ’x20x. Note that some of the signals use
different reference voltages, see the recommended operating conditions table. TTL-output levels are driven to
a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Figure 7 shows the TTL-level outputs.
2.4 V (VOH)
80%
20%
0.6 V (VOL)
Figure 7. TTL-Level Outputs
TTL-output transition times are specified as follows:
D
D
For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage
range and higher and the level at which the output is said to be high is 80% of the total voltage range and
higher.
Figure 8 shows the TTL-level inputs.
2.0 V (VIH)
90%
10%
0.8 V (VIL)
Figure 8. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
D
D
40
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage
range and lower.
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total
voltage range and higher.
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
A
Address or A [15 : 0]
M
Address, data, and control signals:
(A, D, MS, S. BR, RD, W, and R/W)
CI
CLKIN / X2
MS
Memory strobe pins IS, DS, or PS
CLKR
Serial-port receive clock
R
READY
CLKX
Seria-port transmit clock
RD
Read cycle or RD
CO
CLKOUT1
RS
RESET pins RS or RS
D
Data or D [15:0]
S
STRB or synchronous
FR
FSR
TP
Transitory phase
FX
FSX
W
Write cycle or WE
H
HOLD
HA
HOLDA
IN
INTN: BIO, INT1 – INT3, NMI
IO
IOx: IO0, IO1, IO2, or IO3
Lowercase subscripts and their meanings are:
The following letters and symbols and their meanings are:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
IV
Invalid
dis
disable time
HZ
High impedance
en
enable time
X
Unknown, changing, or don’t care level
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
general notes on timing parameters
All output signals from the TMS320x206 devices (including CLKOUT1) are specified from an internal clock such
that all output transitions for a given half cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.
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41
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
CLOCK CHARACTERISTICS AND TIMING
clock options
PARAMETER
DIV2
DIV1
Internal divide-by-two with external crystal or external oscillator
0
0
PLL multiply-by-one
0
1
PLL multiply-by-two
1
0
PLL multiply-by-four
1
1
internal divide-by-two clock option with external crystal†
The internal oscillator is enabled by connecting a crystal across X1 and CLKIN/X2. The crystal should be in
either fundamental or overtone operation and parallel resonant, with an effective series resistance of 30 Ω and
a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF. Note that overtone crystals
require an additional tuned-LC circuit. Figure 9 shows an external crystal (fundamental frequency) connected
to the on-chip oscillator.
X1
CLKIN/X2
Crystal
C1
C2
NOTE A: Texas Instruments encourages customers to submit samples of the device to the resonator/crystal vendor for full characterization.
Figure 9. Internal Clock Option
† PLL modes can also be used with the on-chip oscillator. However, in this case, the PLL lock time should be based on stable clock from the on-chip
oscillator.
42
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
timing at VDD = 3.3 V/5 V with the PLL circuit disabled, divide-by-two mode (’C206, ’LC206)†
PARAMETER
fx
TEST CONDITIONS
Input clock frequency
TA = –40°C to 85°C, 3.3 V/5 V
MIN
0†
NOM
MAX
UNIT
80.0
MHz
† This device is implemented in static logic and therefore can operate with tc(CI) approaching ∞. The device is characterized at 340 ns cycle.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 10)
’320C206-80
’320LC206-80
PARAMETER
MIN
TYP
25
2tc(CI)
UNIT
MAX
†
ns
18
ns
tc(CO)
td(CIH-CO)
Cycle time, CLKOUT1
tf(CO)
tr(CO)
Fall time, CLKOUT1
5
ns
Rise time, CLKOUT1
5
ns
Delay time, CLKIN high to CLKOUT1 high/low
1
tw(COL)
Pulse duration, CLKOUT1 low
H–3
H +3
ns
tw(COH)
Pulse duration, CLKOUT1 high
H–3
H+3
ns
† This device is implemented in static logic and therefore can operate with tc(CI) approaching ∞. The device is characterized at 340 ns cycle.
timing requirements (see Figure 10)
’320C206-80
’320LC206-80
MIN
tc(CI)
tf(CI)
Cycle time, CLKIN
tr(CI)
tw(CIL)
Rise time, CLKIN
12.5
Fall time, CLKIN
Pulse duration, CLKIN low
5
UNIT
MAX
†
ns
5
ns
5
†
ns
ns
†
tw(CIH)
Pulse duration, CLKIN high
5
ns
† This device is implemented in static logic and therefore can operate with tc(CI) approaching ∞. The device is characterized at 340 ns cycle.
tw(CIH)
tc(CI)
tw(CIL)
CLKIN
td(CIH-CO)
tr(CI)
tf(CI)
tc(CO)
tw(COL)
tw(COH)
CLKOUT1
tr(CO)
tf(CO)
Figure 10. CLKIN-to-CLKOUT1 Timing Without PLL ( using ÷2 clock option )
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43
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
timing at VDD = 3.3 V/5 V with the PLL circuit enabled (’C206/’LC206)
PARAMETER
TEST CONDITIONS
MIN
MAX
4
40.96
4
20.48
4
10.24
Input clock frequency, multiply-by-one
fx
Input clock frequency, multiply-by-two
TA = –40°C to 85°C, 3.3 V/5 V
Input clock frequency, multiply-by-four
UNIT
MHz
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 11)
’320C206-80
’320LC206-80
PARAMETER
MIN
TYP
25
UNIT
MAX
†
tc(CO)
tf(CO)
Cycle time, CLKOUT1
tr(CO)
tw(COL)
Rise time, CLKOUT1
Pulse duration, CLKOUT1 low
H–3
H
H+3
ns
tw(COH)
Pulse duration, CLKOUT1 high
H–3
H
H+3
ns
td(TP)
Delay time, transitory phase—PLL synchronized after CLKIN
supplied
5000
cycles
Fall time, CLKOUT1
5
ns
ns
5
ns
† Static design tc(CI) can approach ∞
timing requirements (see Figure 11)
’320C206-80
’320LC206-80
MIN
tc(CI)
( )
UNIT
MAX
Cycle time, CLKIN multiply-by-one
25
ns
Cycle time, CLKIN multiply-by-two
50
ns
Cycle time, CLKIN multiply-by-four
100
ns
tf(CI)
tr(CI)
Fall time, CLKIN
tw(CIL)
tw(CIH)
Pulse duration, CLKIN low
12
Pulse duration, CLKIN high
12
125
ns
Rise time, CLKIN
4
ns
4
ns
125
ns
tw(CIH)
tc(CI)
tw(CIL)
CLKIN
tf(CI)
tw(COH)
tr(CI)
tf(CO)
tc(CO)
tw(COL)
tr(CO)
CLKOUT1
Figure 11. CLKIN-to-CLKOUT1 Timing With PLL ( Enabled )
44
POST OFFICE BOX 1443
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
MEMORY AND PERIPHERAL INTERFACE TIMING
memory and parallel I/O interface read timing
A15– A0, PS, DS, IS, R/W, and BR timings are all included in the timings referenced to A15 – A0 except when
in transition between a read operation following a write operation or a write operation following a read operation,
where PS, DS, and IS pulse high [see tw(MS)].
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 12)
ALTERNATE
SYMBOLS
PARAMETER
tsu(A-RD)
th(RD-A)
Setup time, address valid before RD low
tsu(A)RD
th(A)RD
Hold time, address valid after RD high
td(COL-A)
Delay time, CLKOUT1 low to read address valid
th(COL-A)RD Hold time, read address valid after CLKOUT1 low
td(CO-RD)
td(COL-S)
Delay time, CLKOUT1 high / low to RD low / high
tw(RDL)
tw(RDH)
’320C206-80
MIN
’320LC206-80
MAX
H–4
MIN
H–5
–6
–4
UNIT
ns
–7
6
th(A)COLRD
MAX
ns
6
–5
ns
ns
–1
6
–2
5
ns
0
7
0
6
ns
Pulse duration, RD low (no wait states)
H–3
H+3
H–3
H+3
ns
Pulse duration, RD high
H–3
H+3
H–3
H+3
ns
Delay time, CLKOUT1 low to STRB low / high
timing requirements [H = 0.5tc(CO)] (see Figure 12)
ALTERNATE
SYMBOLS
’320C206-80
’320LC206-80
MIN
MIN
MAX
MAX
UNIT
ta(A)
Access time, from address valid to read
data
2H – 15
2H – 15
ns
ta(C)
Access time, from control IS, PS, DS valid
to read data
2H – 16
2H – 15
ns
tsu(D-RD)
th(RD-D)
th(AIV
D)
h(AIV-D)
Setup time, read data before RD high
Hold time, read data after RD high
Hold time,
time read data from address invalid
tsu(D)RD
th(D)RD
th(D)A
15
14
ns
0
0
ns
0°C to
70°C
0
1
ns
– 40°C
to 85°C
2
2
ns
10
ns
Setup time, read data before CLKOUT1
low
tsu(DCOL)RD
11
th(COL-D)RD
ta(RD)
Hold time, read data after CLKOUT1 low
th(DCOL)RD
1
ta(S)
Access time, from STRB low to read data
tsu(D-COL)RD
Access time, from RD low to read data
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
ns
H – 14
H – 12
ns
2H – 15
2H – 16
ns
45
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
MEMORY AND PERIPHERAL INTERFACE TIMING (CONTINUED)
CLKOUT1
td(COL – A)
th(COL-A)RD
A0 – A15
td(CO – RD)
td(CO – RD)
tsu(A-RD)
th(AIV-D)
th(RD-A)
tw(RDL)
RD
tw(RDH)
ta(RD)
th(RD-D)
ta(A)
tsu(D–COL)RD
tsu(D-RD)
th(COL-D)RD
D0 – D15
(data in)
R/W
Inverted
R / W†
td(COL – S)
STRB
† If the FRDN bit in the PMST register (FFE4h) is a 1, then the signal issued from the RD pin (pin 45) is an inverted R/W signal (or fast RD) replacing
the RD signal.
Figure 12. Memory Interface Read Timing
46
POST OFFICE BOX 1443
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
MEMORY AND PERIPHERAL INTERFACE TIMING (CONTINUED)
memory and parallel I/O interface write timing
A15– A0, PS, DS, IS, R/W, and BR timings are all included in the timings referenced to A15 – A0 except when
in transition between a read operation following a write operation or a write operation following a read operation,
where PS, DS, and IS pulse high [see tw(MS)].
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 13)
ALTERNATE
SYMBOLS
PARAMETER
tsu(A-W)
th(W-A)
Setup time, address valid before WE low
tsu(A-COL)
th(COL-A)W
Setup time, write address valid before CLKOUT1 low
’320C206-80
MIN
’320LC206-80
MAX
MIN
MAX
UNIT
tsu(A)W
th(A)W
H–6
H–6
ns
H–8
H–8
ns
H–7
H–7
ns
Hold time, write address valid after CLKOUT1 low
tsu(A)CO
th(A)COLW
H–5
H–5
ns
tw(MS)
tw(WL)
Pulse duration, IS, DS, PS inactive high
tw(NSN)
Pulse duration, WE low (no wait states)
2H – 2
tw(WH)
td(COL-W)
Pulse duration, WE high
2H – 4
td(RD-W)
td(W-RD)
Delay time, RD high to WE low
td(FRDN)
tsu(D-W)
Delay time, FRDN signal with respect to R/W
th(W-D)
tsu(D-COL)W
Hold time, write data valid after WE high
th(COL-D)W
ten(D-W)
tdis(W-D)
Disable time, WE high to data bus high impedance
Hold time, address valid after WE high
H–2
Delay time, CLKOUT1 low to WE low / high
–1
td(RDW)
td(WRD)
Delay time, WE high to RD low
Setup time, write data valid before WE high
H–1
2H + 4
2H – 2
ns
2H + 4
2H – 4
6
–1
ns
ns
6
ns
2H – 7
2H – 7
ns
3H – 7
3H – 7
ns
–1
–1
2H – 14
2
2
ns
2H – 17
2H – 17
ns
Hold time, write data valid after CLKOUT1 low
tsu(DCOL)W
th(DCOL)W
3
3
ns
Enable time, data bus driven from WE
ten(D)W
1
1
ns
Setup time, write data valid before CLKOUT1 low
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
2H
8
2H – 14
ns
tsu(D)W
th(D)W
2H
8
ns
ns
47
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
MEMORY AND PERIPHERAL INTERFACE TIMING (CONTINUED)
CLKOUT1
RD
td(RD-W)
td(W-RD)
STRB
tw(MS)
tsu(A-COL)
IS, DS
or PS
th(COL-A)W
th(W-A)
A0–A15
td(FRDN)
R/W
tsu(A-W)
Inverted
R / W†
td(COL–W)
td(COL–W)
WE
tw(WL)
tsu(D-COL)W
tw(WH)
tsu(D-W)
ten(D-W)
th(W-D)
th(COL-D)W
tdis(W-D)
D0–D15
(data out)
† If the FRDN bit in the PMST register (FFE4h) is a 1, then the signal issued from the RD pin (pin 45) is an inverted R/W signal (or fast RD) replacing
the RD signal.
Figure 13. Memory Interface Write Timing
48
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
MEMORY AND PERIPHERAL INTERFACE TIMING (CONTINUED)
READY timing
timing requirements [H = 0.5tc(CO)] (see Figure 14)
ALTERNATE
SYMBOL
tsu(R-CO) Setup time, READY before CLKOUT1 rising edge
th(CO-R) Hold time, READY after CLKOUT1 rising edge
tsu(R-RD) Setup time, READY before RD falling edge
th(RD-R) Hold time, READY after RD falling edge
tsu(R)RD
th(R)RD
tv(R-W)
th(W-R)
tv(R)W
th(R)W
Valid time, READY after WE falling edge
Hold time, READY after WE falling edge
tv(R-A)RD Valid time, READY after address valid on read
tv(R-A)W Valid time, READY after address valid on write
’320C206-80
’320LC206-80
MIN
MIN
MAX
MAX
UNIT
12
12
ns
0
0
ns
14
14
ns
–2
–2
H – 14
H+3
tv(R)ARD
tv(R)AW
ns
H – 14
H+3
ns
ns
H – 16
H – 16
ns
2H – 16
2H – 16
ns
CLKOUT1
RD
WE
tsu(R-CO)
th(W-R)
tv(R-W)
th(CO-R)
tsu(R-RD)
th(RD-R)
READY
tv(R-A)RD
tv(R-A)W
A0 – A15
Figure 14. READY Timing
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49
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
XF, TOUT, RS, INT1 – INT3, NMI, and BIO timing
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 15)
ALTERNATE
SYMBOL
PARAMETER
td(COH-XF)
td(COH-TOUT)
Delay time, CLKOUT1 high to XF valid
tw(TOUT)
Pulse duration, TOUT high
’320C206-80
UNIT
MAX
MIN
MAX
1
6
1
6
ns
1
7
1
7
ns
td(XF)
td(TOUT)
Delay time, CLKOUT1 high to TOUT high / low
’320LC206-80
MIN
2H – 5
2H – 5
ns
CLKOUT1
td(COH-XF)
XF
td(COH-TOUT)
tw(TOUT)
TOUT
Figure 15. XF and TOUT Timing
timing requirements† [H = 0.5tc(CO)] (see Figure 16 and Figure 17)
ALTERNATE
SYMBOL
tsu(RS-CIL)
tsu(RS-COL)
tw(RSL)
td(RS-RST)
tsu(IN-COLS)
th(COLS-IN)
Setup time, RS before CLKIN low
tsu(RS)CIL
tsu(RS)COL
Setup time, RS before CLKOUT1 low
Pulse duration, RS low‡
Delay time, RS high to reset-vector fetch
Setup time, INTN before CLKOUT1 low (synchronous)
td(EX)
tsu(IN)COL
Hold time, INTN after CLKOUT1 low (synchronous)
th(IN)COL
tw(IN)
Pulse duration, INTN low
td(IN-INT)
Delay time, INTN low to interrupt-vector fetch
† INTN: BIO, INT1 – INT3, NMI
‡ This parameter assumes the CLKIN to be stable before RS goes active.
50
POST OFFICE BOX 1443
td(IN)
• HOUSTON, TEXAS 77251–1443
’320C206-80
MIN
MAX
’320LC206-80
MIN
MAX
UNIT
9
9
ns
12
12
ns
12H
12H
ns
34H
34H
ns
10
10
ns
0
ns
0
2H + 18
2H + 18
ns
12H
12H
ns
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
XF, TOUT, RS, INT1 – INT3, NMI, and BIO timing (continued)
CLKIN/X2
tsu(RS-CIL)
RS
tw(RSL) +x†
td(RS-RST)
tsu(RS-COL)
CLKOUT1
A0 – A15
PLLRS
Case A. RS and PLLRS Activated at the Same Time During Power-on Reset
CLKIN/X2
tsu(RS-CIL)
RS
tw(RSL) +x†
td(RS-RST)
tsu(RS-COL)
CLKOUT1
A0 – A15
PLLRS
Case B. PLLRS Always Tied Low
CLKIN/X2
tsu(RS-CIL)
RS
tw(RSL) +x†
td(RS-RST)
tsu(RS-COL)
CLKOUT1
A0 – A15
PLLRS
Case C. Core Reset After Power Up, With PLLRS Tied High
† The value of x depends on the reset condition as follows:
Divide-by-two Mode: In this mode, the PLL is bypassed. Assuming CLKIN is stable, x=0. If the internal oscillator is used (i.e. a crystal is
connected to X1 and X2 pins), x=oscillator lock-up time. The state of the PLLRS is not applicable for 2 mode and should always be tied high
or low.
PLL enabled: Assuming CLKIN is stable, x=PLL lock-up time. If the internal oscillator is used, x=oscillator lock-up time + PLL lock-up time.
In case of resets after power on reset, x=0, i.e. tw(RSL)=12 H ns only.
Figure 16. Reset Timings: Cases A, B, and C
CLKOUT1
tsu(IN-COLS)
th(COLS-IN)
tw(IN)
INTN‡
‡ INTN: BIO, INT1 – INT3, NMI
Figure 17. Interrupts and BIO Timing
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51
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
external DMA timing
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 18)
ALTERNATE
SYMBOL
PARAMETER
’320C206-80
MIN
’320LC206-80
MAX
MIN
9
MAX
td(CO-HA)
td(HL-HAL)
Delay time, CLKOUT1 rising to HOLDA
Delay time, HOLD low to HOLDA low†
4H
4H
ns
td(HH-HAH)
thz(M-HAL)
Delay time, HOLD high to HOLDA high
10H
10H
ns
Address high impedance before HOLDA low‡
9
UNIT
ns
tz(M-HAL)
H–5
H–5
ns
ten(HAH-M) Enable time, address driven from HOLDA high
H–5
H–5
ns
† The delay values will change based on the software logic (IDLE instruction) that activates HOLDA. See the TMS320C20x User’s Guide (literature
number SPRU127) for functional description of HOLD logic.
‡ This parameter includes all memory control lines.
td(CO-HA)
CLKOUT1
HOLD/INT1
td(HH-HAH)
td(HL-HAL)
HOLDA
ten(HAH-M)
thz(M-HAL)
Address Bus/
Data Bus/
Control Signals
Figure 18. External DMA Timing
52
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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
serial-port receive timing
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5tc(CO)] (see Figure 19)
ALTERNATE
SYMBOL
tc(CLKR)
tf(CLKR)
Cycle time, serial-port clock (CLKR)
tr(CLKR)
tw(CLKR)
Rise time, serial-port clock (CLKR)
tsu(FR-CLKR)
tsu(DR-CLKR)
Setup time, FSR before CLKR falling edge
th(CLKR-FR)
th(CLKR-DR)
Hold time, FSR after CLKR falling edge
tc(SCK)
tf(SCK)
Fall time, serial-port clock (CLKR)
Pulse duration, serial-port clock (CLKR) low/high
’320C206-80
MIN
tr(SCK)
tw(SCK)
th(FS)
th(DR)
Hold time, DR after CLKR falling edge
MAX
4H
MIN
MAX
4H
UNIT
ns
8
8
ns
8
8
ns
2H
2H
ns
7
7
ns
7
7
ns
7
7
ns
10
10
ns
tsu(FS)
tsu(DR)
Setup time, DR before CLKR falling edge
’320LC206-80
tc(CLKR)
tf(CLKR)
tw(CLKR)
CLKR
th(CLKR-FR)
tw(CLKR)
tr(CLKR)
tsu(FR-CLKR)
tsu(DR-CLKR)
FSR
th(CLKR-DR)
DR
1
2
15/7
16/8
Figure 19. Serial-Port Receive Timing
POST OFFICE BOX 1443
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53
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
serial-port transmit timings (note: timings are for all SSP modes unless otherwise specified)
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 20)
ALTERNATE
SYMBOL
PARAMETER
td(CLKX-DX)
Delay time, CLKX high
to DX valid
’320C206-80
’320LC206-80
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Internal CLKX
and internal
FSX
Internal CLKX
and external
FSX
td(DX)
–5
22
–5
22
External
CLKX and
internal FSX
External
CLKX and
external FSX
td(DX)
0
20
0
20
Multichannel
mode
–5
25
–5
25
SPI mode
–5
4
–5
4
ns
tdis(DX-CLKX)
Disable time, DX valid
from CLKX high
tdis(DX)
th(CLKX-DX)
Hold time, DX valid
after CLKX high
th(DX)
tc(CLKX)
Cycle time, serial-port
clock (CLKX)
Internal CLKX
tc(SCK)
4H
4H
ns
tf(CLKX)
Fall time, serial-port
clock (CLKX)
Internal CLKX
tf(SCK)
5
5
ns
tr(CLKX)
Rise time, serial-port
clock (CLKX)
Internal CLKX
tr(SCK)
5
5
ns
tw(CLKX)
Pulse duration,
serial-port clock
(CLKX) low/high
Internal CLKX
tw(SCK)
Internal CLKX
and internal
FSX
External
CLKX and
internal FSX
td(FS)
td(CLKX-FX)
Delay time, CLKX rising
edge to FSX
10
–6
SPI mode
th(CLKXH-FX)
Internal FSX
–5
ns
14
th(FS)H
5
18
5
18
–5
4
–5
4
–5
† These timings also apply to the following pins in multichannel mode: CLKR, FSR, IO0.
54
ns
2H – 10
14
ns
ns
Multichannel
mode†
Hold time, FSX after
CLKX rising edge
–6
2H – 10
–5
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
–5
ns
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
serial-port transmit timings (note: timings are for all SSP modes unless otherwise specified)
(continued)
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5tc(CO)] (see Figure 20)
’320C206-80
ALTERNATE
SYMBOL
MIN
’320LC206-80
MAX
MIN
MAX
UNIT
tc(CLKX)
Cycle time, serial-port clock
(CLKX)
External CLKX
tc(SCK)
tf(CLKX)
Fall time, serial-port clock
(CLKX)
External CLKX
tf(SCK)
8
8
ns
tr(CLKX)
Rise time, serial-port clock
(CLKX)
External CLKX
tr(SCK)
8
8
ns
tw(CLKX)
Pulse duration,
serial-port clock (CLKX)
low/high
External CLKX
tw(SCK)
td(CLKX-FX)
Delay time, CLKX rising
edge high to FSX
Internal CLKX
and external
FSX
External CLKX
and external
FSX
td(FS)
th(CLKXL-FX)
Hold time, FSX after CLKX
falling edge low
External FSX
th(FS)
th(CLKXH-FX)
Hold time, FSX after CLKX
rising edge high
External FSX
th(FS)H
4H
4H
2H
ns
2H
2H – 8
7
ns
2H – 8
7
2H – 10
ns
ns
2H – 10
ns
tf(CLKX)
tc(CLKX)
tw(CLKX)
CLKX
td(CLKX-FX)
tw(CLKX)
th(CLKXH-FX)
tr(CLKX)
th(CLKXL-FX)
FSX
td(CLKX-DX)
th(CLKX-DX)
tdis(DX-CLKX)
DX
1
2
15/7
16/8
Figure 20. Serial-Port Transmit Timings
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
55
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
general-purpose input/output (I/O) pin timings
switching characteristics over recommended operating conditions (see Figure 21)
ALTERNATE
SYMBOL
PARAMETER
td(CO-IO)
th(CO-IO)f
Delay time, CLKOUT1 falling edge to IOx output valid
Hold time, IOx output valid after CLKOUT1 falling edge
’320C206-80
td(IO)
th(IO)out
MIN
MAX
’320LC206-80
MIN
MAX
13
–2
13
–2
UNIT
ns
ns
timing requirements (see Figure 21)
ALTERNATE
SYMBOL
tsu(IO-CO)
th(CO-IO)r
Setup time, IOx input valid before CLKOUT1 rising edge
Hold time, IOx input valid after CLKOUT1 rising edge
tsu(IO)
th(IO)in
’320C206-80
MIN
MAX
’320LC206-80
MIN
MAX
9
9
ns
5
5
ns
CLKOUT1
th(IO)out
td(IO)
IOx
Output
Mode†
tsu(IO)
th(IO)in
IOx
Input
Mode†
† IOx represents IO0, IO1, IO2, or IO3 input/output pins.
Figure 21. General-Purpose I/O Timings
56
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
UNIT
TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
MECHANICAL DATA
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 / B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
Thermal Resistance Characteristics
PARAMETER
DESCRIPTION
°C / W
ΘJA
Junction-to-ambient
58
ΘJC
Junction-to-case
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
57
PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TMS320C206PZ80
NRND
LQFP
PZ
100
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TMS320C206PZA80
NRND
LQFP
PZ
100
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TMS320LC206PZ80
NRND
LQFP
PZ
100
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TMS320LC206PZA80
NRND
LQFP
PZ
100
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
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Addendum-Page 1
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