7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS Memory Logic Diagram FEATURES: DESCRIPTION: • 8K x 16-bit dual port RAM - Stand Alone - Master Slave • RAD-PAK® radiation-hardened against natural space radiation • Total dose hardness: - > 100 krad (Si), depending upon space mission • Excellent Single Event Effects: -SELTH LET = >100 MeV/mg/cm2 -SEUTH LET = 7 MeV/mg/cm2 • Package: -84 Pin RAD-PAK® quad flat pack • Separate upper byte and lower byte control for multiplexed bus compatibility • High speed access time: 35/45 ns • Expandable to 32 bits or more using master/slave select when cascading • High speed CMOS technology -TTL compatible, single 5V power supply -Interrupt flag for port-to-port communication -On chip port arbitration logic -Asynchronous operation from either port Maxwell Technologies’ 7025E Dual Port RAM High Speed CMOS® microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. The 7025E is designed to be used as a stand-alone 128k-bit Dual Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32bit or more word systems. This design results in full-speed, error-free operation without the need for additional discrete logic. The 7025E provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CS permits the on-chip circuitry of each port to enter a very low standby power mode. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 08.15.02 Rev 2 (619) 503-3300- Fax: (619) 503-3301- www.maxwell.com All data sheets are subject to change without notice 1 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS TABLE 1. 7025E PINOUT DESCRIPTION NAMES LEFT PORT RIGHT PORT Chip Select CSL CSR Read/Write Select R/WL R/WR Output Select OSL OSR AOL-A12L AOR-A12R Data Input/Output I/OOL-I/O15L I/OOR-I/O15R Semaphore Select SEML SEMR Upper Byte Select UBL UBR Lower Byte Select LBL LBR Interrupt Flag INTL INTR BUSYL BUSYR Address Busy Flag Master or Slave Select VCC Power GND Ground Memory M/S TABLE 2. 7025E ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS Supply Voltage (Relative to VSS) VCC -0.3 7.0 V Operating Temperature Range TA -55 125 °C Input or Output Voltage Applied -- GND -0.3V VCC+ 0.3 V TSTG -65 150 °C Storage Temperature Range TABLE 3. DELTA LIMITS PARAMETER VARIATION ICCOP ± 10% AS STATED I TABLE 6 ICCOP1 ± 10% AS STATED I TABLE 6 ICCSB ± 10% AS STATED I TABLE 6 ICCSB1 ± 10% AS STATED I TABLE 6 TABLE 4. 7025E RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNITS Supply Voltage Positive VCC 4.5 5.5 V Input Voltage VIL VIH -0.5 2.2 0.8 6.0 V 08.15.02 Rev 2 All data sheets are subject to change without notice 2 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS TABLE 4. 7025E RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNITS ΘJC -- 1.02 °C/W TA -55 125 °C SYMBOL MIN MAX UNITS Input Capacitance: VIN = 0V1 CIN -- 5 pF Output Capacitance: VOUT = COUT -- 7 pF Thermal Impedance Operating Temperature Range TABLE 5. 7025E CAPACITANCE PARAMETER 0V1 1. Guaranteed by design. Memory TABLE 6. 7025E DC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, TA = -55 TO 125 °C UNLESS OTHERWISE) PARAMETER SYMBOL SUBGROUPS MIN MAX UNITS ILI 1, 2, 3 -- ±10 µA ILO 1, 2, 3 -- ±10 µA Standby Supply Current, Both ports TTL level inputs -35 -45 ICCSB 1, 2, 3 --- 50 50 Standby Supply Current, Both ports CMOS level inputs -35 -45 ICCSB1 1, 2, 3 --- 5 5 Operating Supply Current, Both ports Active -35 -45 ICCOP 1, 2, 3 --- 320 280 Operating Supply Current, One Port Active, One Port Standby -35 -45 ICCOP1 1, 2, 3 --- 190 180 Input Low Voltage3 Input High Voltage VIL VIH 1, 2, 3 -2.2 0.8 -- V Output Low Voltage 4 Output High Voltage VOL VOH 1, 2, 3 -2.4 0.4 -- V Input Leakage Current 1 Output Leakage Current 2 mA mA mA mA 1. VCC = 5.5V, VIN = GND to VCC, CS = VIH, VOUT = 0 to VCC. 2. Vcc=5.5V; Vout = GND to Vcc 3. VIH max = VCC + 0.3V, VIL min = -0.3V or -1V pulse width 50 ns 4. VCC min, IOL = 4 mA, IOH = -4 mA. 08.15.02 Rev 2 All data sheets are subject to change without notice 3 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS TABLE 7. 7025E AC ELECTRICAL CHARACTERISTICS FOR READ CYCLE (VCC = 5V ± 10%, VSS = 0V, TA = -55 TO 125 °C) PARAMETER SUBGROUPS MIN MAX Read Cycle Time -35 -45 tRC 9, 10, 11 Address Access Time -35 -45 tAA 9, 10, 11 Chip Select Access Time 1 -35 -45 tACS 9, 10, 11 Byte Select Access Time 1 -35 -45 tABE 9, 10, 11 Output Select to Output Valid -35 -45 tAOE 9, 10, 11 Output Low Z Time 2,3 -35 -45 tLZ 9, 10, 11 Output High Z Time 2,3 -35 -45 tHZ 9, 10, 11 Chip Enable to Power Up Time 2 tPU Chip Disable to Power Up Time 2 Semaphore Flag Update Pulse (OE or SEM) UNIT 35 45 --- --- 35 45 --- 35 45 --- 35 45 --- 20 25 3 3 --- --- 20 20 ns 9, 10, 11 0 -- ns tPD 9, 10, 11 -- 50 ns tSOP 9, 10, 11 15 -- ns ns ns ns ns ns Memory SYMBOL ns 1. To access RAM, CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIN and SEM = VIL. Either condition must be valid for the entire tEW time. 2. Guaranteed by design. 3. Transition is measured ± 500 mV from low or high impedance voltage with load. TABLE 8. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE CYCLE (VCC = 5V ± 10%, VSS = 0V, TA = -55 TO 125 °C) PARAMETER SYMBOL SUBGROUPS Write Cycle Time -35 -45 tWC 9, 10, 11 Address Valid to End of Write -35 -45 tAW 9, 10, 11 08.15.02 Rev 2 MIN MAX 35 45 --- 30 40 --- UNIT ns ns All data sheets are subject to change without notice 4 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS TABLE 8. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE CYCLE (VCC = 5V ± 10%, VSS = 0V, TA = -55 TO 125 °C) PARAMETER SUBGROUPS Chip Select to End of Write 1 -35 -45 tSW 9, 10, 11 Address Setup Time -35 -45 tAS 9, 10, 11 Write Pulse Width -35 -45 tWP 9, 10, 11 Write Recovery Time -35 -45 tWR 9, 10, 11 Data Valid to End of Write -35 -45 tDW 9, 10, 11 Output High Z Time 2,3 -35 -45 tHZ 9, 10, 11 Data Hold Time -35 -45 tDH 9, 10, 11 Write Select to Output in High Z 2,3 -35 -45 tWZ 9, 10, 11 Output Active from End of Write -35 -45 tOW 9, 10, 11 2,3,4 SEM Flag Write to Read Time -35 -45 tSWRD SEM Flag Contention Window -35 -45 tSPS MIN MAX 30 40 --- 0 0 --- 30 35 --- 0 0 --- 25 25 --- --- 20 20 0 0 --- --- 20 20 0 0 --- 10 10 --- 10 10 --- UNIT ns ns ns ns ns Memory SYMBOL ns ns ns ns ns ns 1. To access RAM, CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIN and SEM = VIL. Either condition must be valid for the entire tEW time. 2. Guaranteed by design. 3. Transition is measured ± 500 mV from low or high impedance voltage with load. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tDW. 08.15.02 Rev 2 All data sheets are subject to change without notice 5 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS TABLE 9. 7025E AC ELECTRICAL CHARACTERISTICS FOR WRITE MASTER/SLAVE CONFIGURATION (VCC = 5V ± 10%, VSS = 0V, TA = -55 TO 125 °C) PARAMETER SYMBOL MIN MAX --- 35 35 --- 30 30 --- 30 30 --- 25 25 --- 60 70 --- 45 55 5 5 --- --- 3 UNIT For Master Only tBAA BUSY Disable Time to Address Not Matched -35 -45 tBDA BUSY Access Time to Chip Select Low -35 -45 tBAC BUSY Disable Time to Chip Select High -35 -45 tBDC Write Pulse to Data Delay 1 -35 -45 tWDD Write Data Valid to Read Data Delay 1 -35 -45 tDDD Arbitration Priority Setup Time 2 -35 -45 tAPS BUSY Disable to Valid Data -35 -45 tBDD ns ns ns ns Memory BUSY Access Time to Address Match -35 -45 ns ns ns ns 3 For Slave Only Write to BUSY Input 4 tWB 0 -- ns Write Hold after BUSY 5 tWH 25 -- ns Write Pulse to Data Delay 1 -35 -45 tWDD --- 60 70 Write Data Valid to Read Data Delay 1 -35 -45 tDDD --- 45 55 ns ns 1. Port to port timing delay through RAM cells from writing port to reading port. 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tWD (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 08.15.02 Rev 2 All data sheets are subject to change without notice 6 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS TABLE 10. 7025E AC PARAMETERS FOR INTERRUPT TIMING (VCC = 5V ± 10%, TA = -55 TO 125 °C, f = 1 MHZ) PARAMETER SYMBOL MIN MAX UNITS Address Setup Time tAS 0 -- ns Write Recovery Time tWR 0 -- ns Interrupt Set Time -35 -45 tINS --- 30 35 Interrupt Reset Time -35 -45 tINR --- 30 35 ns ns TABLE 11. 7025E TRUTH TABLE FOR INTERRUPT FLAG CONTROL 1 CS OS A0-A12 INT Set right INTL flag L L X 1FFF X Reset right INTL flag X X X X X Set left INTL flag X X X X L2 Reset left INTL flag X L L 1FFE H3 Set right INTR flag X X X X L3 Reset right INTR flag X L L 1FFF H2 Set left INTR flag L L X 1FFE X Reset left INTR flag X X X X X Memory R/W FUNCTION Left Port Right Port 1. Assumes BUSYL = BUSYR = H. 2. If BUSYR = L, then no change. 3. If BUSYL = L, then no change. 08.15.02 Rev 2 All data sheets are subject to change without notice 7 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS TABLE 12. 7025E TRUTH TABLE FOR ARBITRATION OPTIONS OPTIONS INPUTS OUTPUTS CS UB LB M/S SEM BUSY INT Busy Logic Master L L X L L X H H H H Output Signal -- Busy Logic Slave L L X L L X L L H H Input Signal -- Interrupt Logic L L X L L X X X H H -- Output Signal Semaphore Logic H H X X X X H L L L H HI-Z -- MODE OUTPUTS INPUTS 1 Memory TABLE 13. 7025E NON-CONTENTION READ/WRITE CONTROL CS R/W OE UB LB SEM I/O8-I/O15 I/O0-I/O7 H X X X X H HI-Z HI-Z Deselected power down X X X H H H HI-Z HI-Z Both bytes deselected: Power down L L X L H H DATAIN HI-Z Write to upper byte only L L X H L H HI-Z DATAIN Write to lower byte only L L X L L H DATAIN DATAIN Write to both bytes L H L L H H DATAOUT HI-Z Read upper byte only L H L H L H HI-Z DATAOUT Read lower byte only L H L L L H DATAOUT DATAOUT Read both bytes X X H X X X HI-Z HI-Z Outputs disabled 1. AOL - A12L = AOR-A12R. 08.15.02 Rev 2 All data sheets are subject to change without notice 8 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS TABLE 14. 7025E SEMAPHORE READ/WRITE CONTROL 1 OUTPUTS INPUTS MODE CS R/W OE UB LB SEM I/O8-I/O15 I/O0-I/O7 H H L X X L DATAOUT DATAOUT Read data in semaphore flag X H L H H L DATAOUT DATAOUT Read data in semaphore flag H X X X L DATAIN DATAIN Write DinO into semaphore flagf X X H H L DATAIN DATAIN Write DinO into semaphore flag L X X L X L -- -- Not allowed L X X X L L -- -- Not allowed Memory 1. AOL - A12L = AOR-A12R. 08.15.02 Rev 2 All data sheets are subject to change without notice 9 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS FIGURE 1. TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE1,2,3 FIGURE 2. TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE1,4,5 Memory 1. 2. 3. 4. 5. F/W is high for read cycles. Device is continuously enabled, CS = VIL, UB or LB = VL. This waveform cannot be used for semaphore reads. CE = VIL. Addresses valid prior to or coincident with CS transition. To access RAM, CS = VL, UB or LB = VIL, SEM = VIH. To access semaphore, CS = VIH, SEM = VIL. 08.15.02 Rev 2 All data sheets are subject to change without notice 10 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS FIGURE 3. TIMING WAVEFORM OF READ CYCLE NO. 3, EITHER SIDE1,3,4,5 1. 2. 3. 4. Memory FIGURE 4. TIMING WAVEFORM OF READ WITH BUSY 2,3,4 (FOR MASTER) To ensure math, the earlier of the two ports wins. Write cycle parameters should be adhered to, to ensure proper writing. Device is continuously enable for both ports. OE = L for the reading port. 08.15.02 Rev 2 All data sheets are subject to change without notice 11 ©2002 Maxwell Technologies All rights reserved. (8K x 16-Bit) Dual Port RAM High-Speed CMOS 7025E FIGURE 5. TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT 1,2,3 (FOR SLAVE ONLY) Memory 1. Assume BUSY Input = H or the writing port, and OE = L for the reading port. 2. Write cycle parameters should be adhered to, to ensure proper writing. 3. Device is continuously enable for both ports. FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING1,2,3,7 08.15.02 Rev 2 All data sheets are subject to change without notice 12 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS FIGURE 7. TIMING WAVEFORM OF WRITE CYCLE NO. 2, CS CONTROLLED TIMING 1,2,3,5 FIGURE 8. TIMING WAVEFORM OF WRITE WITH BUSY (FOR SLAVE) Memory 1. 2. 3. 4. 5. 6. 7. 8. 9. R/W must be high during all address transitions. A write occurs during the overlap (tSW to tWF) of a low CS or SEM and a low R/W. T.WF is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle. During this period, the I/O pins are in the output state, and input signals must not be applied. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. Transitions measured = 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sample and not 100% tested. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of two or (tWZ +tDW) to allow the I/O driver to turn off and data to be placed on the bus for the required tDW. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. To access RAM, CS = VIL, SEM = VIH. To access upper byte, CS = VIL, UB = VIL, SEM = VIH. To access lower byte, CS = VIL, LB = VIL, SEM = VIH. 08.15.02 Rev 2 All data sheets are subject to change without notice 13 ©2002 Maxwell Technologies All rights reserved. (8K x 16-Bit) Dual Port RAM High-Speed CMOS 7025E FIGURE 9. TIMING WAVEFORM OF CONTENTION CYCLE NO. 1, CS ARBITRATION (FOR MASTER) Memory FIGURE 10. TIMING WAVEFORM OF CONTENTION CYCLE NO. 2, ADDRESS VALID ARBITRATION (FOR MASTER ONLY) 1 LEFT ADDRESS VALID FIRST 08.15.02 Rev 2 All data sheets are subject to change without notice 14 ©2002 Maxwell Technologies All rights reserved. (8K x 16-Bit) Dual Port RAM High-Speed CMOS 7025E RIGHT ADDRESS VALID FIRST 1. CSL = CSR = VIL. FIGURE 11. WAVEFORM OF INTERRUPT TIMING 1 SET ADDRESS Memory CLEAR ADDRESS 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See interrupt truth table. 3. Timing depends on which enable signal is asserted last. 4. Timing depends on which enable signal is de-asserted first. 08.15.02 Rev 2 All data sheets are subject to change without notice 15 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS FIGURE 12. 32-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS 1. No arbitration in Master/Slave. BUSY - IN inhibits write in Master/Slave. Memory FIGURE 13. TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE 1 1. CS = VIH for the duration of the above timing (both write and read cycle). 08.15.02 Rev 2 All data sheets are subject to change without notice 16 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS FIGURE 14. TIMING WAVEFORM OF SEMAPHORE CONTENTION 1,3,4 08.15.02 Rev 2 All data sheets are subject to change without notice Memory 1. DOR = DOL = VIL, CSR = CSL = VIH, semaphore Flag is released from both sides (reads as ones from both sides) at cycle start. 2. Either side “A” = left and side “B” = right, or side “A” = right and side “B” = left. 3. This parameter is measured from the point where R/WA or SEMA goes high until R/WB or SEMB goes high. 4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guaranty which side will obtain the flag. 17 ©2002 Maxwell Technologies All rights reserved. (8K x 16-Bit) Dual Port RAM High-Speed CMOS 7025E Memory 84 PIN RAD-PAK® FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A 0.163 0.176 0.189 A1 0.113 0.123 0.133 b 0.006 0.010 0.014 c 0.004 0.006 0.010 D 0.635 0.650 0.665 D1 0.500 BSC e 0.025 BSC S1 0.013 0.070 -- F1 0.540 0.545 0.550 F2 0.415 0.420 0.425 F3 0.412 0.415 0.418 F4 0.560 0.565 0.570 L -- 1.620 1.635 L1 1.595 1.600 1.615 L2 0.940 0.950 0.960 N 84 08.15.02 Rev 2 All data sheets are subject to change without notice 18 ©2002 Maxwell Technologies All rights reserved. (8K x 16-Bit) Dual Port RAM High-Speed CMOS 7025E Q84-01 Note: All dimensions in inches Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 08.15.02 Rev 2 All data sheets are subject to change without notice 19 ©2002 Maxwell Technologies All rights reserved. 7025E (8K x 16-Bit) Dual Port RAM High-Speed CMOS Product Ordering Options Model Number 7025E RP Q X -XX Option Details Feature 35 = 35 ns 45 = 45 ns Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B I = Industrial (testing @ -55°C, +25°C, +125°C) E = Engineering (testing @ +25°C) Package Q = Quad Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature (8K x 16-Bit) Dual Port RAM HighSpeed CMOS 08.15.02 Rev 2 All data sheets are subject to change without notice Memory Access Time 20 ©2002 Maxwell Technologies All rights reserved.