May 1997 ML4818* Phase Modulation/Soft Switching Controller GENERAL DESCRIPTION FEATURES The ML4818 is a complete phase modulation control IC suitable for full bridge soft switching converters. Unlike conventional PWM circuits, the phase modulation technique allows for zero-voltage switching transitions and square wave drive across the transformer. The IC modulates the phases of the two sides of the bridge to control output power. ■ Full bridge phase modulation zero voltage switching circuit with programmable ZV transition times ■ Constant frequency operation to 500kHz ■ Current mode operation ■ Cycle-by-cycle current limiting with integrating fault detection and restart delay ■ Precision buffered 5V reference (+1%) ■ Four 1.5A peak current totem-pole output drivers ■ Under-voltage lockout circuit with 6V hysteresis The ML4818 can be operated in current mode. The delay times for the outputs are externally programmable to allow the zero-voltage switching transitions to take place. Pulse-by-pulse current limit, integrating fault detection, and soft start reset are provided. The under-voltage lockout circuit features a 6V hysteresis with a low starting current to allow off-line start up with a low power bleed resistor. A shutdown function powers down the IC, putting it into a low quiescent state. Power DIP package allows higher dissipation * Some Packages Are Obsolete) ■ BLOCK DIAGRAM 10 13 11 2 SHUTDOWN VREF REFERENCE AND UNDER-VOLTAGE LOCKOUT CLOCK 24 RT VCC INHIBIT OUTPUTS OSC CT 20 R Q 3 5 8 RAMP + Q + A2 OUT DELAY 16 ΦMOD E/A OUT – INV T FLIP FLOP V+ – ERROR AMP +5V 9 S 0.7V + T Q VCC 17 I1 VCC SOFT START 3V A1 OUT DELAY – B1 OUT DELAY + 22 R VCC R 12 4 Q RCRESET ILIM I2 S Q DELAY S RDELAY + 1V – B2 OUT GND *PINS 1, 6, 7, 15, 18, 19 AND 23 ARE GND 21 14 * 1 ML4818 PIN CONNECTION 24-Pin Power DIP GND 1 24 24-Pin SOIC VREF GND 1 24 VREF CT 2 23 GND CT 2 23 GND RAMP 3 22 B1 OUT RAMP 3 22 B1 OUT ILIM 4 21 B2 OUT ILIM 4 21 B2 OUT E/A OUT 5 20 VCC GND 6 19 GND GND 7 18 GND INV 8 17 A1 OUT SOFT START 9 16 A2 OUT SHUTDOWN 10 15 GND RT 11 14 RDELAY RCRESET 12 13 CLOCK E/A OUT 5 20 VCC GND 6 19 GND GND 7 18 GND INV 8 17 A1 OUT SOFT START 9 16 A2 OUT SHUTDOWN 10 15 GND RT 11 14 RDELAY RCRESET 12 13 CLOCK TOP VIEW TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 GND Ground 12 RCRESET Timing elements for Integrating fault detection and reset delay circuits 2 CT Timing capacitor for oscillator 13 CLOCK Oscillator output 3 RAMP Non-inverting input to main comparator. Connected to current sense resistor for current mode 14 RDELAY Resistor to ground on this pin programs the amount of delay from the time an output turns off until its complementary output turns on 4 ILIM Current limit sense pin. Normally connected to current sense resistor 15 GND Ground 5 E/A OUT Output of error amplifier and input to PWM comparator 16 A2 OUT High current totem pole output A1 GND Ground and substrate 17 A1 OUT High current totem pole output A2 8 INV Inverting input to error amp 9 SOFT START Normally connected to soft start capacitor 10 SHUTDOWN Pulling this pin low puts the IC into a power down mode and turns off all outputs. This pin is internally pulled up to VREF. 6,7 11 2 RT Resistor which sets discharge current for oscillator timing capacitor 18,19 GND Ground and substrate 20 VCC Positive supply for the IC 21 B2 OUT High current totem pole output B1 22 B1 OUT High current totem pole output B2 23 GND Ground 24 VREF Buffered output for the 5V voltage reference ML4818 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC ........................................................................... 30V Output Driver Current, Source or Sink DC ....................................................................... 0.5A Pulse (0.5 µs) ........................................................ 1.5A Analog Inputs (CT, RAMP, I LIM, E/A OUT, INV, SOFT START, RCRESET) ............................... –0.3V to 6V CLOCK Output Current (RT) ....................................–5mA Error Amplifier Output Current (E/A OUT) ................ 5mA SOFT START Sink Current ..................................... 50 mA Oscillator Charging Current (CT) .............................–5mA Junction Temperature ............................................. 150°C Storage Temperature Range ..................... –65°C to 150°C Lead Temperature (Soldering 10 Sec) ...................... 260°C Thermal Resistance (θJA ) Plastic Power DIP ............................................ 40°C/W Plastic SOIC ..................................................... 80°C/W OPERATING CONDITIONS Operating Temperature Range ....................... 0°C to 70°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 15V, RT = 12.7kΩ, CT = 250pF, R CLK = 3kΩ, RDELAY = 5kΩ, TA = Operating Temperature Range (Note 1). PARAMETER CONDITIONS MIN TYP. MAX UNITS 410 450 525 kHz OSCILLATOR Initial Accuracy TA = 25°C Voltage Stability 12V < VCC < 25V Temperature Stability Total Variation line, temp. 375 CT Discharge Current VCT = 2V 4.7 2.4 Clock Out High Clock Out Low Ramp Peak 0 Ramp Valley Ramp Valley to Peak –0.3 %/V 0.2 % 525 kHz 5.5 6.3 mA 3.1 6 V 0 0.4 V 4.1 V 1.5 5 V 0 2.6 5 V REFERENCE Output Voltage TA = 25°C, IO = 1mA 4.95 5.0 5.05 V Line Regulation 12V < VCC < 25V –20 2 20 mV Load Regulation 1mA < IO < 10mA –20 3 20 mV Temperature Stability .2 Total Variation 4.85 5.15 Output Noise Voltage 10Hz to 10kHz 50 Long Term Stability TJ = 125°C, 1000 hrs 5 Short Circuit Current VREF = 0V –20 mV/°C V mV 25 –50 mV mA ERROR AMPLIFIER Input Offset Voltage –40 Input Bias Current –3 Input Offset Current 30 mV 0.6 3 µA 0.1 1 µA Open Loop Gain 1 < VO < 4V 70 75 dB PSRR 12 < VCC < 25V 65 80 dB 3 ML4818 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER CONDITIONS MIN TYP. 1 3.2 MAX UNITS ERROR AMPLIFIER (Continued) Output Sink Current VEA OUT = 1V Output Source Current VEA OUT = 5.1V –0.5 –2.2 –20 mA Output High Voltage IEA OUT = –0.5mA 5.0 5.5 6.0 V Output Low Voltage IEA OUT = 1mA 0.8 V Unity Gain Bandwidth 2.0 Slew Rate 8.5 mA 2.8 MHz V/µs PHASE MODULATOR RAMP Bias Current VRAMP = 2.5V EA OUT Zero DC Threshold VRAMP = 0V –1 –10 µA 0.6 0.9 V 50 80 ns 99 200 250 ns 4 4.3 5 V 0.4 tPD, RAMP to Output tDELAY CL = 1nF RDELAY Voltage SOFT START Charge Current VSOFT START = 4V –15 –25 –30 µA Discharge Current VSOFT START = 1V 10 20 30 mA ILIM Bias Current 0V < VILIM < 4V –10 –1 10 µA Current Limit Threshold VSHUTDOWN = 0V 0.92 1.02 1.12 V CURRENT LIMIT/SHUTDOWN tPD, ILIM 50 ns RCRESET Shutdown Threshold 3.15 3.4 3.65 V RCRESET Restart Threshold 1.0 1.3 1.6 V –400 –523 –1000 µA 2.0 2.4 2.8 V –100 –25 10 µA 0.1 0.7 0.4 2.8 V V RCRESET Charging Current VILIM =2V, VRCRESET = 1.5V SHUTDOWN Threshold SHUTDOWN Input Bias Current VSHUTDOWN = 0 OUTPUT Output Low Level IOUT = 20mA IOUT = 200mA, TA = 25°C Output High Level IOUT = –20mA IOUT = –200mA, TA = 25°C Rise/Fall Time CL = 1000pF 12.0 11.0 13.5 13.0 V V 50 75 ns UNDER-VOLTAGE LOCKOUT Start Threshold 15.5 16.5 17.2 V Stop Threshold 9.25 10.2 10.7 V SUPPLY Start Up Current VCC < 15.8V 3 4 mA ICC VINV = 4V, VRAMP = VILIM = 0V, CL = 1nF, TA = 25°C (Note 2) 60 70 mA Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: VCC must be brought above the UVLO start voltage (17.2V) before dropping to VCC = 15V to ensure start-up. 4 ML4818 FUNCTIONAL DESCRIPTION PHASE MODULATOR the voltage across Q3 is now 0V, B2 turns Q3 on at zero voltage. Power is controlled by modulating the switching phase on sides A and B of the full H-bridge converter (Figure 1). Power is delivered to the output through the transformer secondary. The power conversion process is described by the following sequence and illustrated by the timing diagram of Figure 2: 4. The CLOCK now goes high turning A2 off. During this period, Q1 and Q2 and Q4 are off. The transformer leakage current discharges the drain-tosource capacitance on Q4 until there is 0V across it. 1. A2 and B1 are high (Q1 and Q2 are on), beginning the power conversion cycle. 5. A1 will remain low for a period defined by tDELAY, then it goes high. The voltage across Q4 is now 0V as A1 turns it on at zero voltage. 2. After the Φ MOD comparator trips, B1 goes low turning off Q2. The parasitic drain-to-source capacitances of Q2 and Q4 charge to +VIN. This forces the drain-to-source voltage across Q3 to 0V. 6. The previous sequence is now repeated with the opposite polarity on all outputs (see Figure 2). The above sequence is then repeated but with the opposite polarity on all outputs. 3. B2 now goes high after tDELAY (set by RDELAY). Since +VIN TB A2 Q3 LLEAKAGE ML4818 A B TRANSFORMER Q2 A1 TA Q1 B2 Q4 B1 ILIM RSENSE Figure 1. Simplified diagram of Phase Modulated power Outputs. CT CLOCK A2 tDELAY A1 tDELAY tDELAY B1 tPD1 tDELAY tPD1 B2 tDELAY tPD1 tDELAY B A Figure 2. Phase Modulation control waveforms (Shaded areas indicate a power cycle). 5 ML4818 The ML4818 can also be used in current mode by sensing load current on the RAMP input (pin 3). The four output delay timers are programmed via an external RDELAY resistor as shown below. This resistor value should be no less than 1kΩ. Expressing RDELAY in kΩ the delay, in ns is: ISET 11 5V RT 1.7V 2 TDELAY = 33 × RDELAY + 45 (1) Q1 ISET 5V + CT CLOCK OUT – 13 250Ω 5.5mA The ML4818 contains special logic circuits to provide for voltage mode feed-forward and lock out long pulses into the internal logic. This prevents instability from occuring when the Φ Comparator trips in voltage mode. Figure 5. Ocillator Block Diagram Φ MOD OUTPUT RAMP S Q OSC 3 QR R fOSC = Figure 3. Voltage Feed-Forward Circuit. The collector of QR in figure 3 is high only during a power cycle. When the power cycle terminates, RAMP is pulled low. In voltage mode operation, a capacitor is connected from RAMP to GND with a resistor from RAMP to VIN to provide input voltage feed forward. OSCILLATOR The ML4818 oscillator charges the external capacitor, C T, with a current (ISET) equal to 5/RT. When the CT voltage reaches the upper threshold (Ramp Peak), the comparator changes state, turning on the current sink which discharges CT to the lower threshold (Ramp Valley). The CT pin is clamped to Ramp Valley by Q1 (Figure 5) to prevent inaccuracy due to undershoot on CT. To use the CLOCK output for driving external synchronization circuitry, a pull-down resistor is required from CLOCK to GND. CLOCK RAMP PEAK CT RAMP VALLEY TC TD Figure 4. Ocillator Timing Diagram 6 For frequencies of less than 500kHz, oscillator frequency can be set by using the following formulae: 1 0.52 CT R T + 500 CT (2) ERROR AMPLIFIER The ML4818 error amplifier is a 2.5MHz bandwidth, 8.5V/µs slew rate op-amp with provision for limiting the positive output voltage swing (output inhibit line) to implement the soft start function. The error amplifier output source current is limited to 4.5mA. ML4818 VCC 120 VCC 180 100 GAIN PHASE 90 60 40 45 PHASE (Degrees) 135 GAIN 80 Q2 Q1 20 0 0 100 1k 10k 100k FREQUENCY OUT 0 10M 1M POWER GND Figure 6. Error Amplifier Open-Loop Gain and Phase vs. Frequency. Figure 7. Power Driver Simplified Schematic. 7 5 OUTPUT VOLTAGE (V) 4 3 SOURCE 2 15 10 10nF 10nF 5 1nF 1nF ~ ~ SATURATION DROP (V) 6 SINK 100 1 200 tF 0 0 0.2 0.4 0.6 0.8 1.0 1.2 OUTPUT CURRENT (A) 100 (ns) 200 tR 1.4 Figure 8. Output Drive Saturation Voltage vs. Output Current. Figure 9. Output Rise/Fall Time. OUTPUT DRIVER STAGE The ML4818 has four high current high speed totem pole output drivers each capable of 1.5A peak output, designed to quickly switch the gates of capacitive loads, such as power MOSFET transistors. Figure 8 illustrates the saturation characteristics of the ouput drive transistors shown in Figure 7. Typical rise and fall time characteristics of the output drivers are illustrated with capacitive loads of 1nF and 10nF in Figure 9. 7 ML4818 CURRENT LIMIT, FAULT DETECTION AND SOFT START Since the per cycle charge on RCRESET is proportional to how early in the power cycle the over-current occurs, a reset will occur more quickly under output short circuit conditions (Figures 11a and 11b) than during a load surge (Figures 11c and 11d). Current limit is implemented when the current sensed on ILIM reaches the 1V limit. At this point, the PWM cycle is terminated. The flip flop (Figure 10) turns on the current source to charge CRST and remains on for the duration of the clock period. When CRST has charged to 3.4V, a soft start reset occurs. The number of times the PWM cycle is terminated due to over-current is “remembered” on CRST. Over time, CRST is discharged by RRST providing a measure of “forgetting” when the over-current condition no longer occurs. This integrating fault detection is useful in differentiation between short circuit and load surge conditions. When the soft start reset occurs, the output is inhibited and the soft start capacitor is discharged. The output will remain off until CRST discharges to 1.3V through RRST, providing a reset delay. When the IC restarts, the error amplifier output voltage is limited to the voltage at SOFT START, thus limiting the duty cycle. V+ ISWITCH I1 9 SOFT START CSS TERMINATE PWM CYCLE 4 R1 ILIM + C1 1V – S RSENSE V+ Q I2 12 RRST R CLOCK RCRESET CRST + 3.4V 1.3V INHIBIT OUTPUT – UNDER-VOLTAGE LOCKOUT Figure 10. Over-Current, Soft-Start, and Integrating Fault Detect Circuits. 1V 1V V(PIN 4) V(PIN 4) 3.4V 3.4V V(PIN 12) V(PIN 12) Figure 11a, 11b. ILIMIT and Resulting RCRESET Waveforms During Short Circuit. 8 Figure 11c, 11d. ILIMIT and Resulting RCRESET Waveforms During Load Surge. ML4818 UNDER-VOLTAGE LOCKOUT 0.555" On power up, when VCC is below 16V, the IC draws very little current (1.1mA typ.) and VREF is disabled. When VCC rises above 16V, the IC becomes active and VREF is enabled and will stay in that condition until VCC falls below 10.2V. (see Figure 12). INHIBIT OUTPUTS – 4V + POWER DOWN TO LOGIC CIRCUITS 5V VREF I 24 9V VCC INTERNAL BIAS + I 20 – Figure 12. Under-Voltage Lockout and Reference Circuits. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 I I Figure 14. PC Board Copper Area Used as a Heat Sink. 70 50 68 SUPPLY CURRENT (mA) 66 64 40 62 60 58 30 56 54 52 50 –75 20 –25 25 75 125 175 TEMPERATURE Figure 13. Supply Current vs. Temperature (°C). THERMAL INFORMATION The ML4818 is offered in a Power DIP package. This package features improved thermal conduction through the leadframe. Much of the heat is conducted through the center 4 grounded leads. Thermal dissipation can be improved with this package by using copper area on the board to function as a heat sink. Increasing this area can reduce the θJA (see figures 14 and 15), increasing the power handling capability of the package. Additional improvement may be obtained by using an external heat sink (available from Staver). 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 I : HEAT SINK DIMENSION (INCHES) Figure 15. θJA as a Function of I (see figure 15). APPLICATIONS The application circuit shown in Figure 16 features the ML4818 in a primary-side controlled voltage mode application with voltage feed-forward. Input voltage is rectified 120VAC (nominal). Feed-forward is provided by the RAMP pin via the resistor connected to the high voltage input. Current is sensed through sense transformer T4. 9 100kΩ 1/4W 1000pF 5.1kΩ 1/4W 120pF 220pF 470pF 100kΩ 240kΩ, 1/4W 1µF 4.3kΩ, 1/4W 1µF 470pF 680pF 14 11 13 15 12 16 17 8 10 18 7 9 19 21 4 6 22 3 20 23 2 5 24 1 ML4818 330kΩ 1/4W 7.5kΩ, 1/4W 0.1µF 1µF 100µF 25V 1N5818 1µF + 1N5818 VCC 2 x IN5248 10T 4T 4T MUR150 T2 10T IRF840 5.1Ω, 1/4W 1N4148 39Ω 1/4W 10T IRF840 5.1Ω, 1/4W MUR150 200µH T2 1N5818 10 T4 T1 1T 80T T1 45T 0.33µF 630V 4T 4T 0.01µF 1kV 680µF, 200V 680µF, 200V +HV J1 240kΩ 1/4W 240kΩ 1/4W IRF840 T3 10T 5.1Ω, 1/4W SCHOTTKY DIODE 10T IRF840 5.1Ω, 1/4W + + VCC 15µH T3 Figure 16. Offline Full Bridge Converter. 510 1/4W 1kΩ POT IC2 100µF 25V 10T MOC8102 1µF 1N5818 AC IN 1kΩ,1/4W + 1µF 120VAC–220VAC JUMPER FUSE 5A, 250V 4 x 1N5406, 3A, 600V 2 x IN5248 82kΩ, 1W + VOUT, 15V, 13A – ML4818 ML4818 PHYSICAL DIMENSIONS inches (millimeters) Package: P24N 24-Pin Narrow PDIP 1.240 - 1.260 (31.49 - 32.01) 24 0.240 - 0.270 0.295 - 0.325 (6.09 - 6.86) (7.49 - 8.26) PIN 1 ID 0.070 MIN (1.77 MIN) (4 PLACES) 1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) 11 ML4818 PHYSICAL DIMENSIONS inches (millimeters) Package: S24 24-Pin SOIC 0.600 - 0.614 (15.24 - 15.60) 24 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.012 - 0.020 (0.30 - 0.51) 0.090 - 0.094 (2.28 - 2.39) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE ML4818CP ML4818CS 0°C to 70°C 0°C to 70°C PACKAGE Power DIP (P24) SOIC (S24W) (Obsolete) © Micro Linear 1997 Micro Linear is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 12 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS4818-01