March 1997 ML6401* 8-Bit 20 MSPS A/D Converter GENERAL DESCRIPTION FEATURES The ML6401 is a single-chip 8-bit 20 MSPS BiCMOS Video A/D Converter IC, incorporating a differential input track and hold, clock generation circuitry, and reference voltage. ■ 5.0V ±10% single supply operation The input track and hold consists of a low (4pF) capacitance input and a fast settling operational amplifier. The A/D conversion is accomplished through a pipeline approach, reducing the number of required comparators and latches. The non-over-lapping clocks required for this architecture are all internally generated. Clock generation circuitry requires only one 50% duty cycle clock input. The use of error correction throughout the A/D converter improves DNL. All bias voltages and currents required by the A/D converter are internally generated. The digital outputs are three-stateable. ■ Power dissipation less than 200mW typical ■ Internal reference voltage ■ Replaces TMC1175MC20 and AD775JR, functionally compatible to Sony CXD1175AM/AP ■ 16-pin reduced pin count packages available: ML6401CS-3 ■ Low input capacitance track and hold: 4pF ■ Onboard non-overlapping clock generation to minimize external components ■ Three-state outputs and no missing codes ■ 150MHz input track and hold BLOCK DIAGRAM/TYPICAL APPLICATION *Some Packages Are End Of Life 5V VIDEO INPUT VDDA VDDA VDDA VDDD VDDD VIN+ + OE 150MHz T&H 47µF ADC 1 D7 VIN– 0.1µF 1kΩ 75Ω D6 ADC 2 D5 1kΩ SUB DAC AMP SUB DAC AMP DIGITAL ERROR CORRECTION ADC 3 D4 D3 10µF + VIN-BIAS 1.5V VREFOUT D2 INTERNAL 1.0V REFERENCES D1 VREFIN CLOCK GENERATOR D0 GNDA GNDA CLK GNDD GNDO 20MHz 1 ML6401 PIN CONFIGURATION ML6401-1 24-Pin SOIC (S24W) ML6401-3 16-Pin SOIC (S16N) OE 1 24 GNDD D0 1 16 OE GNDO 2 23 VIN– D1 2 15 GNDD D0 3 22 VIN–BIAS D2 3 14 GNDA D1 4 21 GNDA D3 4 13 VIN+ D2 5 20 GNDA D4 5 12 VDDA D3 6 19 VIN+ D5 6 11 VDDD D4 7 18 VDDA D6 7 10 CLK D5 8 17 VREFIN D7 8 9 D6 9 16 VREFOUT D7 10 15 VDDA VDDO 11 14 VDDA CLK 12 13 VDDD VDDD TOP VIEW TOP VIEW PIN DESCRIPTION (Pin numbers in parentheses are for S16N package) PIN 1 (16) 2 NAME OE DESCRIPTION Output Enable. A logic low signal on this pin enables the outputs. GNDO Output ground pin. PIN NAME 13 (9,11) VDDD DESCRIPTION Digital supply pin. 14 (12) VDDA Analog supply pin. 15 (12) VDDA Analog supply pin. 16 VREFOUT Full scale reference output. Connect to pin 17 for self bias. (VRTS on 1175) (ML401-1 only) 17 VREFIN Full scale reference input. Connect to pin 16 for self bias. (VRT on 1175) (ML401-1 only) 3 (1) D0 D0 (LSB) output signal (TTL compatible). 4 (2) D1 D1 output signal (TTL compatible). 5 (3) D2 D2 output signal (TTL compatible). 6 (4) D3 D3 output signal (TTL compatible). 7 (5) D4 D4 output signal (TTL compatible). 18 (12) VDDA Analog supply pin. 8 (6) D5 D5 output signal (TTL compatible). 19 (13) VIN+ Input signal. 9 (7) D6 D6 output signal (TTL compatible). 20 (14) GNDA Analog ground. 10 (8) D7 D7 (MSB) output signal (TTL compatible). 21 (14) GNDA Analog ground. 11 VDDO Output supply pin. 22 VIN–BIAS 12 (10) CLK Clock input pin. Common mode bias output. Connect to pin 23 for self bias. (VRBS on 1175) (ML401-1 only) 23 VIN– Common mode bias input. Connect to pin 22 for self bias. Drive with the negative input if differential input is being used. (VRB on 1175) (ML401-1 only) 24 (15) GNDD Digital Ground. 2 ML6401 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Lead Temperature (soldering, 10 sec) ..................... 150°C Thermal Resistance (θJA) Plastic DIP ....................................................... 80°C/W Plastic SOIC ................................................... 110°C/W Supply Current (ICC) ............................................... 55mA Peak Driver Output Current ............................... ±500mA Analog Inputs ................................................... –0.3 to 7V Junction Temperature ............................................. 150°C Storage Temperature Range ..................... –65°C to 150°C OPERATING CONDITIONS Temperature Range ....................................... 0°C to 70°C TPWH(min) = TPWL(min) ............................................... 25ns ELECTRICAL CHARACTERISTICS Unless otherwise specified, CL = 15pF, VCC = 5V ±10%, TA = Operating Temperature Range (Note 1). PARAMETER CONDITIONS MIN Resolution TYP MAX 8 Power Dissipation UNITS Bits 200 325 mW Transfer Function DC Integral Linearity fCLk = 15MSPS ±0.8 ±1.25 LSB DC Differential Linearity fCLk = 15MSPS ±0.6 ±1 LSB AC Integral Linearity VIN = 2V, 4.4MHz ±2 LSB Offset Voltage VIN– = VIN–BIAS, VREFOUT = VREFIN ±10 LSB Gain Error VIN– = VIN–BIAS, VREFOUT = VREFIN ±2 ±5 LSB VIN = NTSC 40 IRE modulated ramp, fCLK = 14.3 MSPS 1.8 % VIN = NTSC 40 IRE modulated ramp, fCLK = 14.3 MSPS 0.9 degree VIN = 2V, 1MHz, fCLK = 20MHz 48 dB 0.18 % Spurious Free Dynamic Range 58 dB SIN and Distortion (SINAD) 47 dB Effective Bits 7.4 bits Digital Output = 0, VIN– = VIN–BIAS, VREFOUT = VREFIN 0.5 V Digital Output = 255, VIN– = VIN–BIAS, VREFOUT = VREFIN 2.5 V Input Current fCLK = 20MHz ±20 Input Capacitance VIN = 2V 4.0 pF 150 MHz Analog Signal Processing Differential Gain Differential Phase Signal to Noise Ratio Distortion Analog Inputs Input Voltage Analog Input Bandwidth ±30 µA Reference Outputs VIN–BIAS VREFOUT VRIN IREFOUT = 50µA 1.45 1.5 1.55 V 0.97 1.0 1.03 V ±5 µA 3 ML6401 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER CONDITIONS MIN TYP 20 25 MAX UNITS Switching Characteristics Maximum CLK Input Frequency MHz Clock Duty Cycle CLK = 13.5MHz 40 60 % tPWH CLK ≤ 20MHz 25 ns tPWL CLK ≤ 20MHz 25 ns Low Level Input Voltage VIL 0 0.8 V High Level Input Voltage VIH 2.4 VDDD V Low Level Input Current VIL = 0.1V –5 +5 µA High Level Input Current VIH = VDDD – 0.1V –5 +5 µA Analog To Digital Converter Inputs — CLK Input Capacitance 4.0 pF 5 ns Timing — Digital Outputs (CL = 15pF, IOL = 2mA, RL = 2kΩ, fCLK = 20MHz) Sampling Delay tDS Output Hold Time tHO 4 12 10 ns Output Delay Time tDO 5 18 30 ns Three-State Delay Time — Output Enable 10 25 ns Three-State Delay Time — Output Disable 10 20 ns Analog To Digital Converter Outputs — Digital Low Level Output Voltage IOL = 2mA 0 0.6 V High Level Output Voltage IOH = 2mA 2.4 VCCO V –20 +20 µA 4.5 5.5 V Output Current in Three-State Mode Supplies Analog, Digital & Output Supply Voltage Analog Supply Current Static 26 34 mA Digital Supply Current fCLK = 20MHz 10 15 mA Output Supply Current fCLK = 20MHz, CL = 0pF 4 10 mA Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. TIMING DIAGRAM N+2 SAMPLE (VIN+) – (VIN–) N+3 N+1 N N+4 tDS CLK N–3 N–2 N–1 N tHO D0 TO D7 4 tDO N+1 tPWH OUT tPWL ML6401 FUNCTIONAL DESCRIPTION INTRODUCTION A/D CONVERTER The Micro Linear ML6401 is a single-chip video A/D converter IC which is intended for analog to digital conversion of 2Vp-p signals at rates up to 20MSPS. Incorporating both bias and clock generation, it forms a complete solution for data conversion. The operating power dissipation is typically less than 200mW. The IC is designed to offer low power dissipation and a high level of integration resulting in an optimized solution. The IC consists of an input track and hold, a three stage pipelined A/D converter, digital error correction circuitry, internal dual non-overlapping clock generator, and internal voltage reference. The A/D conversion is performed via a three stage pipelined architecture. The first two stages quantize their input signal to three bits, then subtract the result from the input and amplify the difference by a factor of four. This creates a residue signal which spans the full scale range of the following converter. The subtraction and amplification is performed via a differential capacitor feedback amplifier, similar to the input track and hold. The third stage quantizes the signal to four bits. One bit from each of the last two stages is used for error correction. INPUT TRACK AND HOLD The input track and hold consists of a differential capacitor feedback amplifier. The input capacitance, including pin protection and transmission gate, is 4pF. The input to the track and hold can be driven differentially, or single-ended. Single-ended operation uses an internal or external reference to bias the negative input. The full scale range can be set externally, or supplied from an internal source. The track and hold samples the input signal during the positive half cycle of the input clock, and holds the last value of VIN during the negative half cycle of the input clock. The settling time of the amplifier is less than 20ns. The first stage A/D performs the conversion at the end of the track and hold period, approximately one-half cycle after the input was sampled. The second stage A/D performs the conversion one half cycle later, after the subtraction/amplification of the first stage has settled. The third stage A/D performs the conversion after another onehalf cycle delay, when the second stage has settled. Error correction is then performed, and, one clock cycle later, data is transferred to the output latch. This permits the data to be read 3 clocks after the sample was taken. This technique results in lower input capacitance, lower harmonic distortion, and higher signal to noise ratios than the classical two step parallel technique, providing a greater number of effective bits. CLOCK GENERATION The ML6401 typically requires an input clock that if running at 20MHz would have a low time of 25ns, and a high time of 25ns. This input is applied to a clock generation circuit which creates the two non-overlapping clock signals required by the feedback amplifiers. 8 EFB Pipeline delay is the number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every clock cycle. 7 6 1 2 3 4 5 6 FREQUENCY 7 8 9 10 Typical Effective Bits versus Input Signal Frequency. 5 ML6401 INPUT COUPLING The following two figures illustrate two simple means of connecting AC and DC coupled signals into the ML6401-1. internally generated VREFOUT (1 volt) is brought to pin 16 (VRTS of 1175), and an internally generated VIN-BIAS (1.5 volts) is brought to pin 22 (VRBS of 1175). This allows the following four modes of operation: CXD1175 REPLACEMENT 1. CXD1175 — See Figure 3. Connect VRTS to VRT and VRBS to VRB. The ladder will have 2 volts across it (equal to the full scale range), which varies with supply. The 24-pin ML6401-1 is pin compatible with the Sony CXD1175 since all features common to both A/D’s share common pins. The 24-pin ML6401-1 is not, however, a direct replacement for the CXD1175. The architectural differences between the two parts result in slightly different application circuits only in the area of the reference pins. The 1175 brings the top and bottom of the reference ladder to external pins (denoted VRT and VRB respectively), and provides two additional pins (VRTS and VRBS) which can be used to bias the ladder. There are three major differences in the use of the 24-pin ML64011. First, there is no single resistor ladder which can be brought out to users in order to vary gain and offset. Second, the 24-pin ML6401 cannot handle full scale ranges of VDDA volts. And third, where the 1175 architecture has two voltages (VRT and VRB) which fix the two endpoints of the conversion range (code 255 and code 0), the 24-pin ML6401 has one voltage (VREF) which affects only full scale range (code 255 – code 0) and one voltage (VIN–) which affects only bias (code 128). An ML6401 — With pin 16 connected to pin 17, and pin 22 connected to pin 23, the A/D will supply internally generated bandgap biases, making full scale range 2 volts and bias (code 128) 1.5 volts. This is a virtual drop in for an 1175 with pins 16 and 17 shorted, and pins 22 and 23 shorted (0.1 volt bias difference). 2. CXD1175 — See Figure 4. Leave VRTS and VRBS open, and drive VRT and VRB with external voltages. The 1175 spec allows VRT-VRB to equal from 1.8 volts to VDDA volts. This allows users the flexibility to supply higher quality references (higher precision, lower noise), and change the full scale range of the A/D (these voltages can be varied to effectively implement a VGA). Also, the offset of the A/D can be varied. ML6401 — Leave pin 16 and pin 22 open, and drive pin 17 and pin 23 with external voltages. The full scale range will be 2 × pin 17 volts, and the bias (code 128) will occur at pin 23 ±2% volts. The full scale range of the A/D must be kept below 4 volts, but the part is only specified for full scale range of 2 volts. VIDEO INPUT VIDEO INPUT –0.5V to +0.5V VDDA VIN+ + RA S&H 47µF ADC 1 +0.5V to 2.5V + VDDA VIN+ S&H VIN– 0.1µF RL 3 × RA RB 1kΩ RA 0.01µF 10µF + VIN– RB 1kΩ 75Ω ADC 1 RA VIN-BIAS 1.5V VREFOUT INTERNAL 1.0V REFERENCES VREFIN RA = 1k TYP VIN-BIAS 1.5V 0.01µF VREFOUT INTERNAL 1.0V REFERENCES VREFIN GNDD 0.01µF GNDD Figure 1. AC Coupled Input, External Resistors Bias the Input. 6 Figure 2. DC Coupled Input. ML6401 HC04 +12V C6 47µF + C5 0.1µF CLOCK IN R3 500Ω R8 100Ω Q2 Q1 C9 + 47µF +5V C10 0.1µF Q3 1175 PINOUT + 13 C2 10µF C1 470µF R2 180Ω R5 2kΩ 15 16 17 18 R9 5kΩ VIN R1 120Ω R10 75Ω R7* 5kΩ POT R4 1kΩ + 14 19 C8 0.1µF –12V C3 + 47µF C13 10pF 20 21 22 C4 0.1µF 23 + C12 0.1µF C7 47µF C11 0.1µF 24 VDDD CLK VDDA VDDO VDDA D7 VRTS D6 VRT D5 VDDA D4 VIN+ D3 GNDA D2 GNDA D1 VRBS D0 VRB GNDD GNDO OE 12 CLK 11 10 MSB 9 8 7 6 5 4 3 LSB 2 1 *POT R7 WILL HAVE TO BE ADJUSTED Note: Circuit in dashed lines is an optional 1175 input network which can be replaced with circuits in Figure 1 or 2. Figure 3. Replacement for 1175. 3. CXD1175 — Connect VRBS to VRB and leave VRTS open while driving VRT with an external voltage. This allows similar functionality to #2 preceding, but the bias voltage (code 0) will move when the full scale range is changed. ML6401 — Open pin 16, drive pin 17 externally, and connect pin 22 to pin 23. The full scale range will be 2 × pin 17 volts, and the bias (code 128) will occur at 1.5 volts (internally generated from bandgap). The full scale range of the A/D must be kept below 4 volts, but the part is only specified for full scale range of 2 volts. 4. CXD1175 — Connect VRTS to VRT and leave VRBS open while driving VRB with an external voltage. This allows similar functionality to #2 preceding, but the bias voltage (code 0) will move when the full scale range is changed. ML6401 — Connect pin 16 to pin 17, open pin 22 and drive pin 23 externally. The full scale range will be 2 volts (internally generated from bandgap), and the bias (code 128) will occur at pin 23 ±2% volts. 7 ML6401 R12 1kΩ C R11 1kΩ (1) µPC254 + A Q4 – (2) (1) Sony: A to C, B to D (2) Micro Linear: A to D, B to C R13 500Ω D (2) – B (1) + Q5 µPC254 HC04 +12V C6 47µF + C5 0.1µF CLOCK IN R3 500Ω R8 100Ω Q2 Q1 C9 + 47µF +5V C10 0.1µF Q3 1175 PINOUT + 13 C2 10µF C1 470µF R2 180Ω R5 2kΩ 15 16 17 18 R9 5kΩ VIN R1 120Ω R10 75Ω R7* 5kΩ POT R4 1kΩ + 14 19 C8 0.1µF –12V C3 + 47µF C13 10pF 20 21 22 C4 0.1µF 23 + C12 0.1µF C7 47µF C11 0.1µF 24 VDDD CLK VDDA VDDO VDDA D7 VRTS D6 VRT D5 VDDA D4 VIN+ D3 GNDA D2 GNDA D1 VRBS D0 VRB GNDD *POT R7 WILL HAVE TO BE ADJUSTED Note: Circuit in dashed lines is an optional 1175 input network which can be replaced with circuits in Figure 1 or 2. Figure 4. Replacement with Wiring Changes (shown) for the 1175. 8 GNDO OE 12 CLK 11 10 MSB 9 8 7 6 5 4 3 2 1 LSB ML6401 PHYSICAL DIMENSIONS inches (millimeters) Package: S24 24-Pin SOIC 0.600 - 0.614 (15.24 - 15.60) 24 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.012 - 0.020 (0.30 - 0.51) 0.090 - 0.094 (2.28 - 2.39) SEATING PLANE 0.022 - 0.042 (0.56 - 1.07) 0.005 - 0.013 (0.13 - 0.33) 0.009 - 0.013 (0.22 - 0.33) Package: S16N 16-Pin Narrow SOIC 0.386 - 0.396 (9.80 - 10.06) 16 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) PIN 1 ID 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) 11 ML6401 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML6401CS-1 0°C to 70°C 24-Pin SOIC (S24) ML6401CS-3 0°C to 70°C 16-Pin SOIC (S16N) (EOL) © Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 10 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 DS6401-01