MICRON MT28F800B5

8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
FLASH MEMORY
MT28F008B5
MT28F800B5
5V Only, Dual Supply (Smart 5)
0.18µm Process Technology
FEATURES
• Eleven erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
• Eight main memory blocks
• Smart 5 technology (B5):
5V ±10% VCC
5V ±10% VPP application/
production programming1
• Advanced 0.18µm CMOS floating-gate process
• Compatible with 0.3µm Smart 5 device
• Address access time: 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• TSOP and SOP packaging options
• Byte- or word-wide READ and WRITE
(MT28F800B5, 1 Meg x 8/512K x 16)
OPTIONS
48-Pin TSOP Type I
44-Pin SOP2
GENERAL DESCRIPTION
MARKING
• Timing
80ns
• Configurations
1 Meg x 8
512K x 16/1 Meg x 8
• Boot Block Starting Word Address
Top
Bottom
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
• Packages
MT28F008B5
Plastic 40-pin TSOP Type I
(10mm x 29mm)
MT28F800B5
Plastic 48-pin TSOP Type I
(12mm x 20mm)
Plastic 44-pin SOP (600 mil)
Notes:
40-Pin TSOP Type I
The MT28F008B5 (x8) and MT28F800B5 (x16/x8)
are nonvolatile, electrically block-erasable (Flash),
programmable read-only memories containing
8,388,608 bits organized as 524,288 words (16 bits) or
1,048,576 bytes (8 bits). Writing or erasing the device is
done with a 5V VPP voltage, while all operations are
performed with a 5V VCC. Due to process technology
advances, 5V VPP is optimal for application and production programming. These devices are fabricated
with Micron’s advanced 0.18µm CMOS floating-gate
process.
The MT28F008B5 and MT28F800B5 are organized
into eleven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure
or overwrite, the devices feature a hardware-protected
boot block. This block may be used to store code
implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.
Please refer to Micron’s Web site (www.micron.com/
flash) for the latest data sheet.
-8
MT28F008B5
MT28F800B5
T
B
None
ET
VG
WG
SG2
1. This generation of devices does not support 12V VPP
compatibility production programming; however, 5V
VPP application production programming can be used
with no loss of performance.
2. Contact factory for availability.
Part Number Example:
MT28F800B5WG-8 BET
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
1
Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
Pin Assignment (Top View)
44-PIN SOP1
48-Pin TSOP Type I
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
VPP
1
44
RP#
A18
2
43
WE#
A17
3
42
A8
A7
4
41
A9
A6
5
40
A10
A5
6
39
A11
A4
7
38
A12
A3
8
37
A13
A2
9
36
A14
A1
10
35
A15
A0
11
34
A16
CE#
12
33
BYTE#
VSS
13
32
VSS
OE#
14
31
DQ15/(A - 1)
DQ0
15
30
DQ7
DQ8
16
29
DQ14
DQ1
17
28
DQ6
DQ9
18
27
DQ13
DQ2
19
26
DQ5
DQ10
20
25
DQ12
DQ3
21
24
DQ4
DQ11
22
23
VCC
Order Number and Part Marking
MT28F800B5WG-8 B
MT28F800B5WG-8 T
MT28F800B5WG-8 BET
MT28F800B5WG-8 TET
Order Number and Part Marking
MT28F800B5SG-8 B
MT28F800B5SG-8 T
MT28F800B5SG-8 BET
MT28F800B5SG-8 TET
40-Pin TSOP Type I
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
VSS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
Order Number and Part Marking
MT28F008B5VG-8 B
MT28F008B5VG-8 T
MT28F008B5VG-8 BET
MT28F008B5VG-8 TET
Notes: 1. Contact factory for availability.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
2Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
3
A9
Logic
Logic
Status
Register
VPP
Switch/
Pump
State
Machine
Execution
Counter
Addr.
19 (20)
Command
Power
(Current)
Control
Latch
Buffer/
Addr.
Notes: 1. Does not apply to MT28F800B5SG.
2. Does not apply to MT28F008B5.
VPP
I/O
Control
9
YDecoder
Identification
Register
(10)
10
X - Decoder/Block Erase Control
RP#
VCC
CE#
OE#
WE#
WP# 1
A0-A18/(A19)
BYTE# 2
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
Y - Select Gates
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
8KB Parameter Block
8KB Parameter Block
16KB Boot Block
Functional Block Diagram
8
8
7
DQ15
16
Input Data
Latch/Mux
Input
Buffer
7
Output
Buffer
Output
Buffer
Output
Buffer
A-1
Input
Buffer
Input
Buffer
8
7
8
DQ0-DQ7
DQ8-DQ14 2
DQ15/(A - 1) 2
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
MUX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP
NUMBERS
40-PIN
TSOP
NUMBERS
48-PIN
TSOP
NUMBERS
SYMBOL
TYPE
DESCRIPTION
43
9
11
WE#
Input
–
12
14
WP#
Input
12
22
26
CE#
Input
44
10
12
RP#
Input
14
24
28
OE#
Input
33
–
47
BYTE#
Input
11, 10, 9, 8,
7, 6, 5, 4,
42, 41, 40,
39, 38, 37,
36, 35, 34,
3, 2
31
21, 20, 19,
18, 17, 16,
15, 14, 8, 7,
36, 6, 5, 4,
3, 2, 1, 40,
13, 37
–
25, 24,
23,22, 21,
20, 19, 18,
8, 7, 6, 5, 4,
3, 2, 1, 48,
17, 16
45
A0–A18/
(A19)
Input
Write Enable: Determines if a given cycle is a WRITE cycle.
If WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if VPP =
VPPH (5V) and RP# = VIH during a WRITE or ERASE. Does
not affect WRITE or ERASE operation on other blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status
register, sets the internal state machine (ISM) to the array
read mode and places the device in deep power-down
mode. All inputs, including CE#, are “Don’t Care,” and all
outputs are High-Z. RP# unlocks the boot block and
overrides the condition of WP# when at VHH; RP# must be
held at VIH during all other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are HighZ, and all data is accessed through DQ0–DQ7. DQ15/(A - 1)
becomes the least significant address input.
Address Inputs: Select a unique 16-bit word or 8-bit byte.
The DQ15/(A - 1) input becomes the lowest order address
when BYTE# = LOW (MT28F800B5) to allow for a selection
of an 8-bit byte from the 1,048,576 available.
15, 17, 19,
21, 24, 26,
28, 30
16, 18, 20,
22, 25, 27,
29
1
25-28, 32-35
DQ0–DQ7
11
29, 31, 33,
35, 38, 40,
42, 44
30, 32, 34,
36, 39, 41,
43
13
23
13, 32
–
30, 31
23, 39
29, 38
37
27, 46
9, 10, 15
VCC
VSS
NC
–
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
DQ15/
(A-1)
DQ8–
DQ14
VPP
Input/ Data I/O: MSB of data when BYTE# = HIGH.
Output Address Input: LSB of address input when BYTE# = LOW
during READ or WRITE operation.
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE. These pins are used to
input commands to the CEL.
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE when BYTE# = HIGH. These
pins are High-Z when BYTE# is LOW.
Supply Write/Erase Supply Voltage: From a WRITE or ERASE
CONFIRM until completion of the WRITE or ERASE, VPP
must be at 5V. VPP = “Don’t Care” during all other
operations.
Supply Power Supply: +5V ±10%.
Supply Ground.
–
No Connect: These pins may be driven or left unconnected.
4Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F800B5)1
FUNCTION
A0
A9
VPP
DQ0–
DQ7
DQ8–
DQ14
DQ15/
A-1
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
Data-Out
Data-Out
High-Z
Data-Out
High-Z
High-Z
Data-Out
A-1
High-Z
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
20h
D0h
10h/40h
Data-In
Data-In
FFh
X
X
X
Data-In
X
X
X
X
X
Data-In
A-1
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
X
X
H
X
X
H
X
H
X
X
X
X
X
H
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VPPH
VPPH
X
VPPH
VPPH
VPPH
VPPH
X
20h
D0h
D0h
10h/40h
Data-In
Data-In
Data-In
Data-In
FFh
X
X
X
X
Data-In
Data-In
X
X
X
X
X
X
X
Data-In
Data-In
A-1
A-1
X
L
L
H
X
H
L
VID
X
89h
00h
–
H
L
L
H
X
L
L
VID
X
89h
High-Z
X
H
L
L
H
X
H
H
VID
X
9Ch
88h
–
H
L
L
H
X
L
H
VID
X
9Ch
High-Z
X
H
L
L
H
X
H
H
VID
X
9Dh
88h
–
H
L
L
H
X
L
H
VID
X
9Dh
High-Z
X
RP#
CE#
H
L
H
X
X
X
X
X
X
X
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
Standby
RESET
OE# WE# WP# BYTE#
READ
READ (word mode)
READ (byte mode)
Output Disable
WRITE/ERASE (EXCEPT BOOT BLOCK)2
H
H
H
H
H
H
ERASE SETUP
ERASE CONFIRM3
WRITE SETUP
WRITE (word mode)4
WRITE (byte mode)4
READ ARRAY5
VPPH
X
VPPH
VPPH
X
WRITE/ERASE (BOOT BLOCK)2
ERASE SETUP
ERASE CONFIRM3
ERASE CONFIRM3, 6
WRITE SETUP
WRITE (word mode)4
WRITE (word mode)4, 6
WRITE (byte mode)4
WRITE (byte mode)4, 6
READ ARRAY5
DEVICE IDENTIFICATION
Manufacturer
Compatibility (word
mode)8
Manufacturer
Compatibility (byte
mode)
Device (word mode, top
boot)8
Device (byte mode, top
boot)
Device (word mode,
bottom boot)8
Device (byte mode,
bottom boot)
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
H
VHH
H
H
VHH
H
VHH
H
H
X
7
L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).
VPPH = 5V.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
When WP# = VIH, RP# may be at VIH or VHH.
A1–A8, A10–A17 = VIL.
Value reflects DQ8–DQ15.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
5Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F008B5)1
FUNCTION
Standby
RESET
READ
READ
Output Disable
RP#
CE#
OE#
WE#
WP#
A0
A9
VPP
DQ0–DQ7
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
High-Z
H
H
L
L
L
H
H
H
X
X
X
X
X
X
X
X
Data-Out
High-Z
L
H
L
X
X
X
H
L
H
L
X
X
X
X
VPPH
20h
D0h
H
L
H
L
X
X
X
H
L
H
L
X
X
X
X
VPPH
H
L
H
L
X
X
X
X
10h/40h
Data-In
FFh
WRITE/ERASE (EXCEPT BOOT BLOCK)2
H
ERASE SETUP
ERASE CONFIRM
WRITE SETUP
WRITE4
3
READ ARRAY5
WRITE/ERASE (BOOT BLOCK)2
ERASE SETUP
ERASE CONFIRM
3
ERASE CONFIRM3, 6
WRITE SETUP
H
L
H
L
X
X
X
VHH
L
H
L
X
X
X
X
VPPH
20h
D0h
H
L
H
L
H
X
X
VPPH
D0h
H
L
H
L
X
X
X
VHH
L
H
L
X
X
X
X
VPPH
10h/40h
Data-In
WRITE4, 6
H
L
H
L
H
X
X
VPPH
Data-In
READ ARRAY5
H
L
H
L
X
X
X
X
FFh
DEVICE IDENTIFICATION7
Manufacturer Compatibility
Device (top boot)
Device (bottom boot)
H
H
H
L
L
L
L
L
L
H
H
H
X
X
X
L
H
H
VID
VID
VID
X
X
X
89h
98h
99h
4
WRITE
Notes: 1.
2.
3.
4.
5.
6.
7.
L = VIL, H = VIH, X = VIL or VIH.
VPPH = 5V.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
When WP# = VIH, RP# may be at VIH or VHH.
A1–A8, A10–A19 = VIL.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
6Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F800B5 and MT28F008B5 Flash memories incorporate a number of features ideally suited for
system firmware. The memory array is segmented into
individual erase blocks. Each block may be erased
without affecting data stored in other blocks. These
memory blocks are read, written and erased with commands to the command execution logic (CEL). The
CEL controls the operation of the internal state
machine (ISM), which completely controls all WRITE,
BLOCK ERASE, and VERIFY operations. The ISM protects each memory location from over-erasure and
optimizes each memory location for maximum data
retention. In addition, the ISM greatly simplifies the
control necessary for writing the device in-system or in
an external programmer.
The Functional Description provides detailed information on the operation of the MT28F800B5 and
MT28F008B5 and is organized into these sections:
• Overview
• Memory Architecture
• Output (READ) Operations
• Input Operations
• Command Set
• ISM Status Register
• Command Execution
• Error Handling
• WRITE/ERASE Cycle Endurance
• Power Usage
• Power-Up
OVERVIEW
Smart 5 Technology (B5)
Smart 5 operation allows maximum flexibility for insystem READ, WRITE and ERASE operations. WRITE
and ERASE operations may be executed with a VPP
voltage of 3.3V or 5V. Due to process technology
advances, 5V VPP is optimal for application and production programming. For any operation, VCC is at 5V.
Eleven Independently Eraseable
Memory Blocks
The MT28F800B5 and MT28F008B5 are organized
into eleven independently erasable memory blocks
that allow portions of the memory to be erased without affecting the rest of the memory data. A special
boot block is hardware-protected against inadvertent
erasure or writing by requiring either a super-voltage
on the RP# pin or driving the WP# pin HIGH. (The WP#
pin does not apply to the SOP package.) One of these
two conditions must exist, along with the VPP voltage
(5V) on the VPP pin, before a WRITE or ERASE is per8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
formed on the boot block. The remaining blocks
require that only the VPP voltage be present on the VPP
pin before writing or erasing.
Hardware-Protected Boot Block
This block of the memory array can be erased or
written only when the RP# pin is taken to VHH or when
the WP# pin is brought HIGH. (The WP# pin does not
apply to the SOP package.) This provides additional
security for the core firmware during in-system firmware updates should an unintentional power fluctuation or system reset occur. The MT28F800B5 and
MT28F008B5 are available with the boot block starting
at the bottom of the address space (“B” suffix) or the
top of the address space (“T” suffix).
Selectable Bus Size (MT28F800B5)
The MT28F800B5 allows selection of an 8-bit (1 Meg
x 8) or 16-bit (512K x 16) data bus for reading and writing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is
read or written only on the lower 8 bits (DQ0–DQ7).
Data written to the memory array utilizes all active
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written
in word form.
Internal State Machine (ISM)
BLOCK ERASE and BYTE/WORD WRITE timing are
simplified with an ISM that controls all erase and write
algorithms in the memory array. The ISM ensures protection against over-erasure and optimizes write margin to each cell.
During WRITE operations, the ISM automatically
increments and monitors WRITE attempts, verifies
write margin on each memory cell and updates the
ISM status register. When BLOCK ERASE is performed,
the ISM automatically overwrites the entire addressed
block (eliminates over-erasure), increments and monitors ERASE attempts, and sets bits in the ISM status
register.
ISM Status Register
The ISM status register enables an external processor to monitor the status of the ISM during WRITE and
ERASE operations. Two bits of the 8-bit status register
are set and cleared entirely by the ISM. These bits indicate whether the ISM is busy with an ERASE or WRITE
task and when an erase has been suspended. Addi-
7Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
tional error information is set in three other bits: VPP
status, write status, and erase status.
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register
or status register). Commands may be issued to the
CEL while the ISM is active. However, there are restrictions on what commands are allowed in this condition.
See the Command Execution section for more detail.
ERASE function is block-oriented. All READ and
WRITE operations are done on a random-access basis.
The boot block is protected from unintentional
ERASE or WRITE with a hardware protection circuit
which requires that a super-voltage be applied to RP#
or that the WP# pin be driven HIGH before erasure is
commenced. The boot block is intended for the core
firmware required for basic system functionality. The
remaining ten blocks do not require that either of
these two conditions be met before WRITE or ERASE
operations.
Deep Power-Down Mode
Boot Block
To allow for maximum power conservation, the
MT28F800B5 and MT28F008B5 feature a very low current, deep power-down mode. To enter this mode, the
RP# pin is taken to VSS ±0.2V. In this mode, the current
draw is a maximum of 20µA. Entering deep powerdown also clears the status register and sets the ISM to
the read array mode.
The hardware-protected boot block provides extra
security for the most sensitive portions of the firmware. This 16KB block may only be erased or written
when the RP# pin is at the specified boot block unlock
voltage (VHH) or when the WP# pin is HIGH. During a
WRITE or ERASE of the boot block, the RP# pin must
be held at VHH or the WP# pin held HIGH until the
WRITE or ERASE is completed. (The WP# pin does not
apply to the SOP package.) The VPP pin must be at
VPPH (5V) when the boot block is written to or erased.
The MT28F800B5 and MT28F008B5 are available in
two configurations and top or bottom boot block. The
top boot block version supports processors of the x86
variety. The bottom boot block version is intended for
680X0 and RISC applications. Figure 1 illustrates the
memory address maps associated with these two versions.
Command Execution Cell (CEL)
MEMORY ARCHITECTURE
The MT28F800B5 and MT28F008B5 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into eleven addressable blocks that vary in size
and are independently erasable. When blocks rather
than the entire array are erased, total device endurance is enhanced, as is system flexibility. Only the
Figure 1: Memory Address Maps
Bottom Boot
MT28F800B5/008B5xx-xxB
WORD ADDRESS
BYTE ADDRESS
7FFFFh
FFFFFh
Top Boot
MT28F800B5/008B5xx-xxT
WORD ADDRESS
BYTE ADDRESS
7FFFFh
FFFFFh
7E000h
7DFFFh
7D000h
7CFFFh
7C000h
7BFFFh
FC000h
FBFFFh
FA000h
F9FFFh
F8000h
F7FFFh
70000h
6FFFFh
E0000h
DFFFFh
60000h
5FFFFh
C0000h
BFFFFh
50000h
4FFFFh
A0000h
9FFFFh
40000h
3FFFFh
80000h
7FFFFh
30000h
2FFFFh
60000h
5FFFFh
20000h
1FFFFh
40000h
3FFFFh
10000h
0FFFFh
20000h
1FFFFh
00000h
00000h
128KB Main Block
70000h
6FFFFh
E0000h
DFFFFh
60000h
5FFFFh
C0000h
BFFFFh
128KB Main Block
16KB Boot Block
128KB Main Block
50000h
4FFFFh
A0000h
9FFFFh
40000h
3FFFFh
80000h
7FFFFh
30000h
2FFFFh
60000h
5FFFFh
20000h
1FFFFh
40000h
3FFFFh
10000h
0FFFFh
20000h
1FFFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
00000h
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
8KB Parameter Block
16KB Boot Block
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
8KB Parameter Block
96KB Main Block
128KB Main Block
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
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©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
Parameter Blocks
Status Register
The two 8KB parameter blocks store less sensitive
and more frequently changing system parameters and
also may store configuration or diagnostic coding.
These blocks are enabled for erasure when the VPP pin
is at VPPH. No super-voltage unlock or WP# control is
required.
Performing a READ of the status register requires
the same input sequencing as a READ of the array
except that the address inputs are “Don’t Care.” The
status register contents are always output on DQ0–
DQ7, regardless of the condition of BYTE# on the
MT28F800B5. DQ8–DQ15 are LOW when BYTE# is
HIGH, and DQ8–DQ14 are High-Z when BYTE# is
LOW. Data from the status register is latched on the
falling edge of OE# or CE#, whichever occurs last. If the
contents of the status register change during a read of
the status register, either OE# or CE# may be toggled
while the other is held LOW to update the output.
Following a WRITE or ERASE, the device automatically enters the status register read mode. In addition,
a READ during a WRITE or ERASE produces the status
register contents on DQ0–DQ7. When the device is in
the erase suspend mode, a READ operation produces
the status register contents until another command is
issued. In certain other modes, READ STATUS REGISTER may be given to return to the status register read
mode. All commands and their operations are
described in the Command Set and Command Execution sections.
Main Memory Blocks
The eight remaining blocks are general-purpose
memory blocks and do not require a super-voltage on
RP# or WP# control to be erased or written. These
blocks are intended for code storage, ROM-resident
applications or operating systems that require in-system update capability.
OUTPUT (READ) OPERATIONS
The MT28F800B5 and MT28F008B5 feature three
different types of READs. Depending on the current
mode of the device, a READ operation produces data
from the memory array, status register or device identification register. In each of these three cases, the
WE#, CE# and OE# inputs are controlled in a similar
manner. Moving between modes to perform a specific
READ is described in the Command Execution section.
Memory Array
To read the memory array, WE# must be HIGH, and
OE# and CE# must be LOW. Valid data is output on the
DQ pins when these conditions are met, and a valid
address is given. Valid data remains on the DQ pins
until the address changes, or OE# or CE# goes HIGH,
whichever occurs first. The DQ pins continue to output new data after each address transition as long as
OE# and CE# remain LOW.
The MT28F800B5 features selectable bus widths.
When the memory array is accessed as a 512K x 16,
BYTE# is HIGH, and data is output on DQ0–DQ15. To
access the memory array as a 1 Meg x 8, BYTE# must
be LOW, DQ8–DQ14 are High-Z, and all data is output
on DQ0–DQ7. The DQ15/(A-1) pin becomes the lowest
order address input so that 1,048,576 locations can be
read.
After power-up or RESET, the device is automatically in the array read mode. All commands and their
operations are described in the Command Set and
Command Execution sections.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
Identification Register
A READ of the two 8-bit device identification registers requires the same input sequencing as a READ of
the array. WE# must be HIGH, and OE# and CE# must
be LOW. However, ID register data is output only on
DQ0–DQ7, regardless of the condition of BYTE# on the
MT28F800B5. A0 is used to decode between the two
bytes of the device ID register; all other address inputs
are “Don’t Care.” When A0 is LOW, the manufacturer
compatibility ID is output, and when A0 is HIGH, the
device ID is output. DQ8–DQ15 are High-Z when
BYTE# is LOW. When BYTE# is HIGH, DQ8–DQ15 are
00h when the manufacturer compatibility ID is read
and 88h when the device ID is read.
To get to the identification register read mode,
READ IDENTIFICATION may be issued while the
device is in certain other modes. In addition, the identification register read mode can be reached by applying a super-voltage (VID) to the A9 pin. Using this
method, the ID register can be read while the device is
in any mode. When A9 is returned to VIL or VIH, the
device will return to the previous mode.
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©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
INPUT OPERATIONS
The DQ pins are used either to input data to the
array or to input a command to the CEL. A command
input issues an 8-bit command to the CEL to control
the mode of operation of the device. A WRITE is used
to input data to the memory array. The following section describes both types of inputs. More information
describing how to use the two types of inputs to write
or erase the device is provided in the Command Execution section.
Commands
To perform a command input, OE# must be HIGH,
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM (described in a later section). The 8-bit
command is input on DQ0–DQ7, while DQ8–DQ15 are
“Don’t Care” on the MT28F800B5. The command is
latched on the rising edge of CE# (CE#-controlled) or
WE# (WE#-controlled), whichever occurs first. The
condition of BYTE# has no effect on a command input.
Table 1:
Memory Array
A WRITE to the memory array sets the desired bits
to logic 0s but cannot change a given bit to a logic 1
from a logic 0. Setting any bits to a logic 1 requires that
the entire block be erased. To perform a WRITE, OE#
must be HIGH, CE# and WE# must be LOW, and VPP
must be set to VPPH. Writing to the boot block also
requires that the RP# pin be at VHH or WP# be HIGH.
A0–A18 (A19) provide the address to be written, while
the data to be written to the array is input on the DQ
pins. The data and addresses are latched on the rising
edge of CE# (CE#-controlled) or WE# (WE#-controlled), whichever occurs first. A WRITE must be preceded by a WRITE SETUP command. Details on how to
input data to the array are described in the Write
Sequence section.
Selectable bus sizing applies to WRITEs as it does to
READs on the MT28F800B5. When BYTE# is LOW (byte
mode), data is input on DQ0–DQ7, DQ8–DQ14 are
High-Z, and DQ15 becomes the lowest order address
input. When BYTE# is HIGH (word mode), data is
input on DQ0–DQ15.
Command Set
COMMAND
HEX CODE
RESERVED
00h
READ ARRAY
FFh
IDENTIFY DEVICE
90h
READ STATUS REGISTER
70h
CLEAR STATUS REGISTER
ERASE SETUP
50h
20h
ERASE CONFIRM/RESUME
D0h
WRITE SETUP
ERASE SUSPEND
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
40h or 10h
B0h
DESCRIPTION
This command and all unlisted commands are invalid and should not be
called. These commands are reserved to allow for future feature
enhancements.
Must be issued after any other command cycle before the array can be read.
It is not necessary to issue this command after power-up or RESET.
Allows the device and manufacturer compatibility ID to be read. A0 is used
to decode between the manufacturer compatibility ID (A0 = LOW) and
device ID (A0 = HIGH).
Allows the status register to be read. Please refer to Table 2 for more
information on the status register bits.
Clears status register bits 3-5, which cannot be cleared by the ISM.
The first command given in the two-cycle ERASE sequence. The ERASE is not
completed unless followed by ERASE CONFIRM.
The second command given in the two-cycle ERASE sequence. Must follow
an ERASE SETUP command to be valid. Also used during an ERASE SUSPEND
to resume the ERASE.
The first command given in the two-cycle WRITE sequence. The write data
and address are given in the following cycle to complete the WRITE.
Requests a halt of the ERASE and puts the device into the erase suspend
mode. When the device is in this mode, only READ STATUS REGISTER, READ
ARRAY and ERASE RESUME commands may be executed.
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8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
COMMAND SET
To simplify writing of the memory blocks, the
MT28F800B5 and MT28F008B5 incorporate an ISM
that controls all internal algorithms for writing and
erasing the floating gate memory cells. An 8-bit command set is used to control the device. Details on how
to sequence commands are provided in the Command
Execution section. Table 1 lists the valid commands.
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled
to check for WRITE or ERASE completion or any
related errors. During or following a WRITE, ERASE or
ERASE SUSPEND, a READ operation outputs the status
register contents on DQ0–DQ7 without prior command. While the status register contents are read, the
outputs are not updated if there is a change in the ISM
status unless OE# or CE# is toggled. If the device is not
Table 2:
STATUS
BIT #
SR7
SR6
SR5
SR4
SR3
SR0-2
in the write, erase, erase suspend or status register read
mode, READ STATUS REGISTER (70h) can be issued to
view the status register contents.
All of the defined bits are set by the ISM, but only
the ISM and erase suspend status bits are reset by the
ISM. The erase, write and VPP status bits must be
cleared using CLEAR STATUS REGISTER. If the VPP status bit (SR3) is set, the CEL does not allow further write
or erase operations until the status register is cleared.
This enables the user to choose when to poll and clear
the status register. For example, the host system may
perform multiple BYTE WRITE operations before
checking the status register instead of checking after
each individual WRITE. Asserting the RP# signal or
powering down the device also clears the status register.
Status Register
STATUS REGISTER BIT
DESCRIPTION
ISM STATUS
1 = Ready
0 = Busy
ERASE SUSPEND STATUS
1 = ERASE suspended
0 = ERASE in progress/completed
ERASE STATUS
1 = BLOCK ERASE error
0 = Successful BLOCK ERASE
WRITE STATUS
1 = WORD/BYTE WRITE error
0 = Successful WORD/BYTE WRITE
VPP STATUS
1 = No VPP voltage detected
0 = VPP present
The ISMS bit displays the active status of the state machine during
WRITE or BLOCK ERASE operations. The controlling logic polls this bit
to determine when the erase and write status bits are valid.
Issuing an ERASE SUSPEND places the ISM in the suspend mode and
sets this and the ISMS bit to “1.” The ESS bit remains “1” until an
ERASE RESUME is issued.
ES is set to “1” after the maximum number of ERASE cycles is executed
by the ISM without a successful verify. ES is only cleared by a CLEAR
STATUS REGISTER command or after a RESET.
WS is set to “1” after the maximum number of WRITE cycles is
executed by the ISM without a successful verify. WS is only cleared by a
CLEAR STATUS REGISTER command or after a RESET.
VPPS detects the presence of a VPP voltage. It does not monitor VPP
continuously, nor does it indicate a valid VPP voltage. The VPP pin is
sampled for 5V after WRITE or ERASE CONFIRM is given. VPPS must be
cleared by CLEAR STATUS REGISTER or by a RESET.
Reserved for future use.
RESERVED
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
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©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
COMMAND EXECUTION
Commands are issued to bring the device into different operational modes. Each mode allows specific
operations to be performed. Several modes require a
sequence of commands to be written before they are
reached. The following section describes the properties of each mode, and Table 3 lists all command
sequences required to perform the desired operation.
first cycle. The next cycle is the WRITE, during which
the write address and data are issued and VPP is
brought to VPPH. Writing to the boot block also
requires that the RP# pin be brought to VHH or the WP#
pin be brought HIGH at the same time VPP is brought
to VPPH. The ISM now begins to write the word or byte.
VPP must be held at VPPH until the write is completed
(SR7 = 1).
While the ISM executes the WRITE, the ISM status
bit (SR7) is at “0,” and the device does not respond to
any commands. Any READ operation produces the
status register contents on DQ0–DQ7. When the ISM
status bit (SR7) is set to a logic 1, the WRITE has been
completed, and the device enters status register read
mode until another command is given.
After the ISM has initiated the WRITE, it cannot be
aborted except by a RESET or by powering down the
part. Doing either during a WRITE corrupts the data
being written. If only the WRITE SETUP command has
been given, the WRITE may be nullified by performing
a null WRITE. To execute a null WRITE, FFh must be
written when BYTE# is LOW, or FFFFh must be written
when BYTE# is HIGH. When the ISM status bit (SR7)
has been set, the device is in the status register read
mode until another command is issued.
Read Array
The array read mode is the initial state of the device
upon power-up and after a RESET. If the device is in
any other mode, READ ARRAY (FFh) must be given to
return to the array read mode. Unlike the WRITE
SETUP command (40h), READ ARRAY does not need
to be given before each individual read access.
IDENTIFY DEVICE
IDENTIFY DEVICE (90h) may be written to the CEL
to enter the identify device mode. While the device is
in this mode, any READ produces the device ID when
A0 is HIGH and the manufacturer compatibility ID
when A0 is LOW. The device remains in this mode until
another command is given.
Write Sequence
Two consecutive cycles are needed to input data to
the array. WRITE SETUP (40h or 10h) is given in the
Table 3:
Command Sequences
COMMANDS
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
ALTERNATE WORD/BYTE
WRITE
Notes: 1.
2.
3.
4.
5.
6.
7.
BUS
FIRST CYCLE
CYCLES
REQ’D OPERATION ADDRESS
1
3
2
1
2
2
2
2
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
X
X
X
X
X
X
X
X
SECOND CYCLE
DATA OPERATION
FFh
90h
70h
50h
20h
B0h
40h
10h
ADDRESS
DATA NOTES
READ
READ
IA
X
ID
SRD
WRITE
WRITE
WRITE
WRITE
BA
X
WA
WA
D0h
D0h
WD
WD
1
2, 3
4
5, 6
6, 7
6, 7
Must follow WRITE or ERASE CONFIRM commands to the CEL to enable Flash array READ cycles.
IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
ID = Identify Data.
SRD = Status Register Data.
BA = Block Address (A12–A19).
Addresses are “Don’t Care” in first cycle but must be held stable.
WA = Address to be written; WD = Data to be written to WA.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
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©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
ERASE Sequence
ERASE Suspension
Executing an ERASE sequence sets all bits within a
block to logic 1. The command sequence necessary to
execute an ERASE is similar to that of a WRITE. To provide added security against accidental block erasure,
two consecutive command cycles are required to initiate an erase of a block. In the first cycle, addresses are
“Don’t Care,” and ERASE SETUP (20h) is given. In the
second cycle, VPP must be brought to VPPH, an address
within the block to be erased must be issued, and
ERASE CONFIRM (D0h) must be given. If a command
other than ERASE CONFIRM is given, the write and
erase status bits (SR4 and SR5) are set, and the device
is in the status register read mode.
After the ERASE CONFIRM (D0h) is issued, the ISM
starts the ERASE of the addressed block. Any READ
operation outputs the status register contents on
DQ0–DQ7. VPP must be held at VPPH until the ERASE is
completed (SR7 = 1). When the ERASE is completed,
the device is in the status register read mode until
another command is issued. Erasing the boot block
also requires that either the RP# pin be set to VHH or
the WP# pin be held HIGH at the same time VPP is set
to VPPH.
The only command that may be issued while an
ERASE is in progress is ERASE SUSPEND. This command allows other commands to be executed while
pausing the ERASE in progress. When the device has
reached the erase suspend mode, the erase suspend
status bit (SR6) and ISM status bit (SR7) is set. The
device may now be given a READ ARRAY, ERASE
RESUME or READ STATUS REGISTER command. After
READ ARRAY has been issued, any location not within
the block being erased may be read. If ERASE RESUME
is issued before SR6 has been set, the device immediately proceeds with the ERASE in progress.
Table 4:
ERROR HANDLING
After the ISM status bit (SR7) has been set, the VPP
(SR3), write (SR4) and erase (SR5) status bits may be
checked. If one or a combination of these three bits
has been set, an error has occurred. The ISM cannot
reset these three bits. To clear these bits, CLEAR STATUS REGISTER (50h) must be given. If the VPP status
bit (SR3) is set, further write or erase operations cannot resume until the status register is cleared. Table 4
lists the combination of errors.
Status Register Error Decode1
STATUS BITS
SR5
SR4
SR3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ERROR DESCRIPTION
No errors
VPP voltage error
WRITE error
WRITE error, VPP voltage not valid at time of WRITE
ERASE error
ERASE error, VPP voltage not valid at time of ERASE CONFIRM
Command sequencing error or WRITE/ERASE error
Command sequencing error, VPP voltage error, with WRITE and ERASE errors
Notes: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
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©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE ENDURANCE
POWER-UP
The MT28F800B5 and MT28F008B5 are designed
and fabricated to meet advanced firmware storage
requirements. To ensure this level of reliability, VPP
must be at 5V ±10% during WRITE or ERASE cycles.
Due to process technology advances, 5V VPP is optimal
for application and production programming.
The likelihood of unwanted WRITE or ERASE, operations is minimized because two consecutive cycles
are required to execute either operation. However, to
reset the ISM and to provide additional protection
while VCC is ramping, one of the following conditions
must be met:
• RP# must be held LOW until VCC is at valid functional level; or
• CE# or WE# may be held HIGH and RP# must be
toggled from VCC-GND-VCC.
After a power-up or RESET, the status register is
reset, and the device enters the array read mode.
POWER USAGE
The MT28F800B5 and MT28F008B5 offer several
power-saving features that may be utilized in the array
read mode to conserve power. Deep power-down
mode is enabled by bringing RP# LOW. Current draw
(ICC) in this mode is a maximum of 20µA. When CE# is
HIGH, the device enters standby mode. In this mode,
maximum ICC current is 130µA. If CE# is brought HIGH
during a WRITE or ERASE, the ISM continues to operate, and the device consumes the respective active
power until the write or erase is completed.
Figure 2:
Power-Up/Reset Timing Diagram
RP#
Note 1
VCC
(5V)
t
AA
Address
VALID
VALID
Data
t
RWH
UNDEFINED
NOTE:
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
1. VCC must be within the valid operating range before RP#
goes HIGH.
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8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
SELF-TIMED WRITE SEQUENCE
(WORD OR BYTE WRITE)1
COMPLETE WRITE
STATUS-CHECK SEQUENCE
Start
Start (WRITE completed)
WRITE 40h or 10h
SR3 = 0?
NO
VPP Error 4, 5
NO
BYTE/WORD WRITE Error5
YES
VPP = 5V
SR4 = 0?
YES
WRITE Word or Byte
Address/Data
WRITE Successful
STATUS REGISTER
READ
SR7 = 1?
NO
YES
Complete Status2
Check (optional)
WRITE Complete 3
Notes: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.
2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register
is cleared.
3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued.
4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further
WRITE or ERASE operations are allowed by the CEL.
5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
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8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
SELF-TIMED BLOCK ERASE SEQUENCE1
COMPLETE BLOCK ERASE
STATUS-CHECK SEQUENCE
Start
Start (ERASE completed)
WRITE 20h
SR3 = 0?
NO
VPP Error 5, 6
YES
Command Sequence Error6
NO
BLOCK ERASE Error6
YES
VPP = 5V
SR4, 5 = 1?
WRITE D0h,
Block Address
NO
SR5 = 0?
ERASE
Busy
STATUS REGISTER
READ
YES
ERASE Successful
NO
NO
SR7 = 1?
Suspend ERASE?
YES
YES
Complete Status 2
Check (optional)
Suspend 4
Sequence
ERASE Resumed
ERASE Complete
3
Notes: 1. Sequence may be repeated to erase additional blocks.
2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register
is cleared.
3. To return to the array read mode, the FFh command must be issued.
4. Refer to the ERASE SUSPEND flowchart for more information.
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further
WRITE or ERASE operations are allowed by the CEL.
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
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©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
ERASE SUSPEND/RESUME SEQUENCE
Start (ERASE in progress)
WRITE B0h
(ERASE SUSPEND)
VPP = 5V
STATUS REGISTER
READ
SR7 = 1?
NO
YES
SR6 = 1?
NO
YES
ERASE Completed
WRITE FFh
(READ ARRAY)
Done
Reading?
NO
YES
WRITE D0h
(ERASE RESUME)
Resume ERASE
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
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©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
**VCC, input and I/O pins may transition to -2V for
<20ns and VCC + 2V for <20ns.
†
Voltage may pulse to -2V for <20ns and 14V for <20ns.
Voltage on VCC Supply Relative to VSS .... -0.5V TO +6V**
Input Voltage Relative to VSS ................... -0.5V TO +6V**
VPP Voltage Relative TO VSS .....................-0.5V TO +5.5V†
RP# or A9 Pin Voltage Relative to Vss... -0.5V to +12.6V†
Temperature Under Bias..........................-40ºC to +85ºC
Storage Temperature (plastic) ...............-55ºC to +125ºC
Power Dissipation ....................................................... 1W
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ OPERATING
CONDITIONS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
VCC
VIH
VIL
VID
4.5
2
-0.5
10
5.5
VCC + 0.5
0.8
12.6
V
V
V
V
1
1
1
1
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
Device Identification Voltage, A9
DC OPERATING CHARACTERISTICS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
PARAMETER/CONDITION
OUTPUT VOLTAGE LEVELS (TTL)
Output High Voltage (IOH = -2.5mA)
Output Low Voltage (IOL = 5.8mA)
OUTPUT VOLTAGE LEVELS (CMOS)
Output High Voltage (IOH = -100µA)
INPUT LEAKAGE CURRENT
Any input (0V ≤ VIN ≤ VCC); All other pins not under test = 0V
INPUT LEAKAGE CURRENT: VHH INPUT
(10V ≤ VHH ≤ 12.6V = VID)
INPUT LEAKAGE CURRENT: RP# INPUT
(10V ≤ RP# ≤ 12.6V = VHH)
OUTPUT LEAKAGE CURRENT
(DOUT is disabled; 0V ≤ VOUT ≤ VCC)
SYMBOL
MIN
MAX
UNITS
NOTES
VOH1
VOL
2.4
–
–
0.50
V
V
1
VOH2
VCC - 0.4
–
V
1
IL
-1
1
µA
IID
–
500
µA
IHH
–
500
µA
IOZ
-10
10
µA
Notes: 1. All voltages referenced to VSS.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
18Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
CAPACITANCE
(TA = +25ºC; f = 1 MHz)
PARAMETER/CONDITION
Input Capacitance
Output Capacitance
SYMBOL
MAX
UNITS
CI
CO
9
12
pF
pF
READ AND STANDBY CURRENT DRAIN1
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
PARAMETER/CONDITION
READ CURRENT: WORD-WIDE, TTL INPUT LEVELS
(CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH; RP# = VIH)
READ CURRENT: WORD-WIDE, CMOS INPUT LEVELS
(CE# ≤ 0.2V; OE# ≥ VCC - 0.2V; f = 10 MHz; Other inputs ≤ 0.2V or ≥ VCC
- 0.2V; RP# ≥ VCC - 0.2V)
READ CURRENT: BYTE-WIDE, TTL INPUT LEVELS
(CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH; RP# = VIH)
READ CURRENT: BYTE-WIDE, CMOS INPUT LEVELS
CE# ≤ 0.2V; OE# ≥ VCC - 0.2V; f = 10 MHz; Other inputs ≤ 0.2V or ≥ VCC 0.2V; RP# = VCC - 0.2V)
STANDBY CURRENT: TTL INPUT LEVELS
VCC power supply standby current (CE# = RP# = VIH;
Other inputs = VIL or VIH)
STANDBY CURRENT: CMOS INPUT LEVELS
VCC power supply standby current (CE# = RP# = VCC - 0.2V)
DEEP POWER-DOWN CURRENT: VCC SUPPLY
(RP# = VSS ±0.2V)
STANDBY OR READ CURRENT:
VPP SUPPLY (VPP ≤ 5.5V)
DEEP POWER-DOWN CURRENT: VPP SUPPLY
(RP# = VSS ±0.2V)
SYMBOL
MAX
UNITS
NOTES
ICC1
55
mA
2, 3
ICC2
50
mA
2, 3
ICC3
55
mA
2, 3
ICC4
50
mA
2, 3
ICC5
2
mA
ICC6
130
µA
ICC8
20
µA
IPP1
±15
µA
IPP2
5
µA
Notes: 1. Vcc = MAX VCC during Icc tests.
2. Icc is dependent on cycle rates.
3. Icc is dependent on output loading. Specified values are obtained with the outputs open.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
19Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
READ TIMING PARAMETERS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +5V ±10%
AC CHARACTERISTICS
PARAMETER
Read cycle time
Access time from CE#
Access time from OE#
Access time from address
RP# HIGH to output valid delay
OE# or CE# HIGH to output in High-Z
Output hold time from OE#, CE# or address change
RP# LOW pulse width
-8/-8 ET
SYMBOL
t
RC
ACE
t
AOE
t
AA
t
RWH
t
OD
t
OH
t
RP
MIN
MAX
80
t
80
40
80
1,000
20
0
60
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
1
Notes: 1. OE# may be delayed by tACE - tAOE after CE# falls before tACE is affected.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
20Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
AC TEST CONDITIONS
Input pulse levels ...................................... 0.4V to 2.4V
Input rise and fall times.......................................<10ns
Input timing reference level .................... 0.8V and 2V
Output timing reference level ................. 0.8V and 2V
Output load........................1 TTL gate and CL = 100pF
WORD-WIDE READ CYCLE1
VIH
A0–A18/(A19)
VALID ADDRESS
VIL
tRC
tAA
VIH
CE#
VIL
tACE
VIH
OE#
VIL
VIH
WE#
VIL
tOD
tAOE
tOH
VIH
DQ0–DQ15
VALID DATA
VIL
tRWH
VIH
RP#
VIL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
-8/-8 ET
SYMBOL
tRC
MIN
-8/-8 ET
MAX
UNITS
SYMBOL
ns
tRWH
t
80
ns
t
t
40
ns
t
tAA
80
ns
ACE
AOE
80
MIN
OD
OH
0
MAX
UNITS
1,000
ns
20
ns
ns
Notes: 1. BYTE# = HIGH (MT28F800B5 only).
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
21Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
BYTE-WIDE READ CYCLE1
VIH
A0–A18/(A19)
VALID ADDRESS
VIL
tRC
tAA
VIH
CE#
VIL
tACE
VIH
OE#
VIL
VIH
WE#
VIL
tOD
tAOE
tOH
VIH
DQ0–DQ7
VALID DATA
VIL
VIH
DQ8–DQ14
HIGH-Z
VIL
tRWH
VIH
RP#
VIL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA≤ +85ºC)
-8/-8 ET
SYMBOL
t
RC
MIN
-8/-8 ET
MAX
80
UNITS
SYMBOL
ns
t
tACE
80
ns
tOD
t
40
ns
t
t
80
ns
AOE
AA
MIN
RWH
OH
0
MAX
UNITS
1,000
ns
20
ns
ns
Notes: 1. BYTE# = LOW (MT28F800B5 only).
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
22Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
RECOMMENDED DC WRITE/ERASE CONDITIONS1
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +5V ±10%
PARAMETER/CONDITION
VPP WRITE/ERASE lockout voltage
VPP voltage during WRITE/ERASE operation
Boot block unlock voltage
VCC WRITE/ERASE lockout voltage
SYMBOL
MIN
MAX
UNITS
NOTES
VPPLK
VPPH
VHH
VLKO
–
4.5
10
2
1.5
5.5
12.6
–
V
V
V
V
2
3
WRITE/ERASE CURRENT DRAIN
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +5V ±10%
PARAMETER/CONDITION
WORD WRITE CURRENT: VCC SUPPLY
WORD WRITE CURRENT: VPP SUPPLY
BYTE WRITE CURRENT: VCC SUPPLY
BYTE WRITE CURRENT: VPP SUPPLY
ERASE CURRENT: VCC SUPPLY
ERASE CURRENT: VPP SUPPLY
ERASE SUSPEND CURRENT: VCC SUPPLY
(ERASE suspended)
ERASE SUSPEND CURRENT: VPP SUPPLY
(ERASE suspended)
SYMBOL
MAX
UNITS
NOTES
ICC9
IPP3
ICC10
IPP4
ICC11
IPP5
ICC12
25
20
25
20
30
40
10
mA
mA
mA
mA
mA
mA
mA
4
4
5
5
IPP6
200
µA
6
Notes: 1. WRITE operations are tested at VPP voltages equal to or less than the previous erase.
2. Absolute WRITE/ERASE protection when VPP ≤ VPPLK.
3. When 5V VCC and VPP are used, VCC cannot exceed VPP by more than 500mV during WRITE and ERASE
operations.
4. Applies to MT28F800B5 only.
5. Applies to MT28F008B5 and MT28F800B5 with BYTE# = LOW.
6. Parameter is specified when device is not accessed. Actual current draw will be Icc12 plus read current if a READ
is executed while the device is in erase suspend mode.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
23Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS: WE#- (CE#-)CONTROLLED WRITES
Commercial Temperature (0ºC ≤ TA ≤ +70ºC) and Extended Temperature (-40ºC ≤ TA ≤ +85ºC); VCC = +5V ±10%
AC CHARACTERISTICS
-8/-8 ET
PARAMETER
SYMBOL
t
MAX
UNITS
WC
80
ns
WPH (tCPH)
30
ns
t
WRITE cycle time
WE# (CE#) HIGH pulse width
MIN
50
ns
Address setup time to WE# (CE#) HIGH
t
AS
50
ns
Address hold time from WE# (CE#) HIGH
t
AH
0
ns
Data setup time to WE# (CE#) HIGH
t
DS
50
ns
Data hold time from WE# (CE#) HIGH
t
DH
0
ns
WE# (CE#) pulse width
t
WP (tCP)
CE# (WE#) setup time to WE# (CE#) LOW
t
CS (tWS)
0
ns
CE# (WE#) hold time from WE# (CE#) HIGH
t
CH (tWH)
0
ns
200
ns
VPP setup time to WE# (CE#) HIGH
t
VPS1
NOTES
1
RS
1,000
ns
t
RHS
100
ns
2
WRITE duration (WORD or BYTE WRITE)
t
WED1
4.5
µs
4
Boot BLOCK ERASE duration
t
WED2
100
ms
4
Parameter BLOCK ERASE duration
t
WED3
100
ms
4
Main BLOCK ERASE duration
t
WED4
500
ms
4
t
RP# HIGH to WE# (CE#) LOW delay
RP# at VHH or WP# HIGH setup time to WE# (CE#) HIGH
WE# (CE#) HIGH to busy status (SR7 = 0)
t
WB
200
ns
3
VPP hold time from status data valid
t
VPH
0
ns
4
RP# at VHH or WP# HIGH hold time from status data valid
t
RHH
0
Boot block relock delay time
t
REL
ns
2
100
ns
5
WORD/BYTE WRITE AND ERASE DURATION CHARACTERISTICS
PARAMETER
TYP
MAX
UNITS
NOTES
Boot/parameter BLOCK ERASE time
Main BLOCK ERASE time
Main BLOCK WRITE time (byte mode)
Main BLOCK WRITE time (word mode)
0.5
1.5
1
1
7
14
–
–
s
s
s
s
6
6
6, 7, 8
6, 7, 8
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
Measured with VPP = VPPH = 5V.
RP# should be held at VHH OR WP# held HIGH until boot block WRITE or ERASE is complete.
Polling status register before tWB is met may falsely indicate WRITE or ERASE completion.
WRITE/ERASE times are measured to valid status register data (SR7 = 1).
t
REL is required to relock boot block after WRITE or ERASE to boot block.
Typical values measured at TA = +25ºC.
Assumes no system overhead.
Typical WRITE times use checkerboard data pattern.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
24Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE
WE#-CONTROLLED WRITE/ERASE
VIH
A0–A18/(A19)
Note 1
VIL
tAS
AIN
tAS
tAH
tAH
VIH
CE#
VIL
tCS
tCH
VIH
OE#
tWC
VIL
tWP
tWED1/2/3/4
tWPH
VIH
WE#
DQ0–DQ7/
DQ0–DQ15 2
tWB
VIL
tDS
VIH
CMD
in
VIL
VHH
tDH
tDH
tDS
Status
(SR7=0)
CMD/
Data-in
tRS
tRHS
Status
(SR7=1)
tRHH
CMD
in
[Unlock boot block]
VIH
RP# 3
VIL
[Unlock boot block]
VIH
WP# 3
VIL
tVPH
tVPS1
VPP
VPPH1
[5V VPP]
VIL
WRITE or ERASE (block)
address asserted, and
WRITE data or ERASE
CONFIRM issued
WRITE SETUP or
ERASE SETUP input
WRITE or ERASE
executed, status register
checked for completion
Command for next
operation issued
DON’T CARE
TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA≤ +85ºC)
-8/-8 ET
SYMBOL
MIN
-8/-8 ET
MAX
UNITS
SYMBOL
MIN
MAX
UNITS
tWC
80
ns
tRS
1,000
ns
tWPH
30
ns
tRHS
100
ns
t
WP
50
ns
t
WED1
4.5
µs
AS
50
ns
t
WED2
100
ms
AH
0
ns
t
WED3
100
ms
tDS
50
ns
tWED4
500
ms
tDH
0
ns
tWB
200
ns
t
VPH
0
ns
RHH
0
ns
t
t
CS
0
ns
t
t
CH
0
ns
t
t
VPS1
200
ns
Notes: 1. Address inputs are “Don’t Care” but must be held stable.
2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.
3. Either RP# at VHH or WP# HIGH unlocks the boot block.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
25Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE
CE#-CONTROLLED WRITE/ERASE
VIH
A0–A18/(A19)
Note 1
VIL
tAS
AIN
tAS
tAH
tAH
VIH
WE#
VIL
tWS
tWH
VIH
OE#
VIL
tWC
tCP
tWED1/2/3/4
tCPH
VIH
CE#
DQ0–DQ7/
DQ0–DQ15 2
VIL
VIH
VIL
VHH
t WB
tDH
tDS
tDH
tDS
CMD
in
Status
(SR7=0)
CMD/
Data-in
tRS
tRHS
Status
(SR7=1)
tRHH
CMD
in
[Unlock boot block]
VIH
RP# 3
VIL
[Unlock boot block]
VIH
WP# 3
VIL
tVPH
tVPS1
VPP
[5V VPP]
VPPH1
VIL
WRITE or ERASE (block)
address asserted, and
WRITE data or ERASE
CONFIRM issued
WRITE SETUP or
ERASE SETUP input
WRITE or ERASE
executed, status register
checked for completion
Command for next
operation issued
DON’T CARE
TIMING PARAMETERS
Commercial Temperature (0ºC ≤ TA ≤ +70ºC)
Extended Temperature (-40ºC ≤ TA≤ +85ºC)
-8/-8 ET
SYMBOL
MIN
MAX
-8/-8 ET
UNITS
SYMBOL
WC
80
ns
t
t
WPH
30
ns
t
t
CP4
t
MIN
MAX
UNITS
1,000
ns
RHS
100
ns
RS
50
ns
t
WED1
4.5
µs
tAS
50
ns
tWED2
100
ms
tAH
0
ns
tWED3
100
ms
DS
50
ns
t
WED4
500
ms
DH
0
ns
t
WB
200
ns
WS
0
ns
t
VPH
0
ns
tWH
0
ns
tRHH
0
ns
200
ns
t
t
t
tVPS1
Notes: 1. Address inputs are “Don’t Care” but must be held stable.
2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.
3. Either RP# at VHH or WP# HIGH unlocks the boot block.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
26Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
40-PIN PLASTIC TSOP I
(10mm x 20mm)
.795 (20.20)
.780 (19.80)
.727 (18.47)
.0197 (0.50)
TYP
.010 (0.25)
.721 (18.31)
1
40
PIN #1 INDEX
.397 (10.08)
.391 (9.93)
.010 (0.25)
.006 (0.15)
20
21
.010 (0.25)
.004 (0.10)
.007 (0.18)
.005 (0.13)
SEE DETAIL A
GAGE
PLANE
.047 (1.20)
MAX
.008 (0.20)
.002 (0.05)
.024 (0.60)
.016 (0.40)
DETAIL A
.0315 (0.80)
Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
27Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
48-PIN PLASTIC TSOP I
(10mm x 20mm)
.795 (20.20)
.780 (19.80)
.727 (18.47)
.0197 (0.50)
TYP
.010 (0.25)
.721 (18.31)
1
48
PIN #1 INDEX
.475 (12.07)
.469 (11.91)
.010 (0.25)
.006 (0.15)
24
25
.010 (0.25)
.004 (0.10)
.007 (0.18)
.005 (0.12)
SEE DETAIL A
GAGE
PLANE
.047 (1.20) MAX
.008 (0.20)
.002 (0.05)
.024 (0.60)
.016 (0.40)
DETAIL A
.0315 (0.80)
Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
28Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
44-PIN PLASTIC SOP
(600 Mil)
1.113 (28.27)
1.107 (28.12)
.050 (1.27)
TYP
.007 (0.18)
.020 (0.50)
.015 (0.38)
.005 (0.13)
.643 (16.34)
.620 (15.74)
.499 (12.68)
.493 (12.52)
PIN #1 INDEX
.030 (0.76)
SEE DETAIL A
.004 (0.10)
.016 (0.40)
.010 (0.25)
.106 (2.70) MAX
GAGE PLANE
.010 (0.25)
DETAIL A
.0315 (0.80)
(ROTATED 90 CW)
.066 (1.72)
Notes: 1. Contact factory for availability
2. All dimensions in millimeters MAX/MIN or typical where noted.
3. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side.
DATA SHEET DESIGNATION
No Marking This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
29Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
REVISION HISTORY
Rev. 3, ...............................................................................................................................................................................8/02
• Removed PRELIMINARY designation
• Changed tRS from 600ns (MIN) to 1,000ns (MIN)
• Changed VOL from 0.45V (MAX) to 0.50V (MAX)
Rev. 2, PRELIMINARY....................................................................................................................................................12/01
• Updated input capacitance specification
• Updated tRWH specification
Original document, PRELIMINARY, Rev. 1....................................................................................................................7/01
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E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron and the Micron and M logos are trademarks and/or service marks of Micron Technology, Inc.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
30
Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.