MICRON MT48LC4M4A2

16 MEG: x4, x8
SDRAM
SYNCHRONOUS
DRAM
MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks
MT48LC2M8A1/A2 S - 1 Meg x 8 x 2 banks
For the latest data sheet revisions, please refer to the
Micron Web site: www.micron.com/datasheets.
FEATURES
PIN ASSIGNMENT (Top View)
• PC100-compliant; includes CONCURRENT AUTO
PRECHARGE
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Longer lead TSOP for improved reliability (OCPL*)
• One- and two-clock WRITE recovery (tWR) versions
OPTIONS
44-Pin TSOP
x4
NC
DQ0
NC
DQ1
-
MARKING
• Configurations
4 Meg x 4 (2 Meg x 4 x 2 banks)
2 Meg x 8 (1 Meg x 8 x 2 banks)
4M4
2M8
• WRITE Recovery (tWR/tDPL)
tWR = 1 CLK
A1
tWR = 2 CLK (Contact factory for availability.)A2
• Plastic Package - OCPL*
44-pin TSOP (400 mil)
Vss
DQ7
VssQ
DQ6
VDDQ
DQ5
VssQ
DQ4
VDDQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
x4
NC
DQ3
NC
DQ2
-
NOTE: The # symbol indicates signal is active LOW. A dash
(-) indicates x4 pin function is same as x8 pin
function.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
-8B
-10
NOTE: The 16Mb SDRAM base number differentiates the
offerings in two places: MT48LC2M8A1 S. The fourth
field distinguishes the architecture offering: 4M4
designates 4 Meg x 4, and 2M8 designates 2 Meg x 8.
The fifth field distinguishes the WRITE recovery
offering: A1 designates one CLK and A2 designates two
CLKs.
4 MEG x 4
2 MEG x 8
2 Meg x 4 x 2 banks 1 Meg x 8 x 2 banks
4K
4K
2K (A0-A10)
2K (A0-A10)
2 (BA)
1 (BA)
1K (A0-A9)
512 (A0-A8)
KEY TIMING PARAMETERS
SPEED
GRADE
Part Number Example:
MT48LC2M8A1TG-10 S
-8B
-10
-8B
-10
16Mb (x4/x8) SDRAM PART NUMBERS
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
x8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TG
• Timing (Cycle Time)
8ns; tAC = 6ns @ CL = 3
10ns; tAC = 9ns @ CL = 2
PART NUMBER
MT48LC4M4A1TG S
MT48LC2M8A1TG S
x8
VDD
DQ0
VssQ
DQ1
VDDQ
DQ2
VssQ
DQ3
VDDQ
NC
NC
WE#
CAS#
RAS#
CS#
BA
A10
A0
A1
A2
A3
VDD
ARCHITECTURE
4 Meg x 4 (tWR = 1 CLK)
2 Meg x 8 (tWR = 1 CLK)
CLOCK
ACCESS TIME
SETUP
FREQUENCY CL = 2** CL = 3** TIME
125 MHz
100 MHz
83 MHz
66 MHz
–
–
9ns
9ns
6ns
7.5ns
–
–
2ns
3ns
2ns
3ns
HOLD
TIME
1ns
1ns
1ns
1ns
* Off-center parting line
**CL = CAS (READ) latency
1
©1998, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
16 MEG: x4, x8
SDRAM
GENERAL DESCRIPTION
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
The Micron 16Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing the alternate bank will hide the PRECHARGE cycles
and provide seamless, high-speed, random-access operation.
The Micron 16Mb SDRAM is designed to operate in
3.3V, low-power memory systems. An auto refresh mode
is provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously
burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks in order to hide precharge time, and the
capability to randomly change column addresses on each
clock cycle during a burst access.
The Micron 16Mb SDRAM is a high-speed CMOS,
dynamic random-access memory containing 16,777,216
bits. It is internally configured as a dual memory array
(the 4 Meg x 4 is a dual 2 Meg x 4, and the 2 Meg x 8 is a dual
1 Meg x 8) with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CLK).
Each of the two internal banks is organized with 2,048
rows and either 1,024 columns by 4 bits (4 Meg x 4) or 512
columns by 8 bits (2 Meg x 8).
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with the ACTIVE command are used to select the
bank and row to be accessed (BA selects the bank, A0-A10
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 4 Meg x 4 ........................
Functional Block Diagram - 2 Meg x 8 ........................
Pin Descriptions ............................................................
4
5
6
Functional Description ................................................
Initialization .............................................................
Register Definitions .................................................
Mode Register .....................................................
Burst Length ..................................................
Burst Type .....................................................
CAS Latency ..................................................
Operating Mode ............................................
Write Burst Mode .........................................
Commands .....................................................................
Truth Table 1 (Commands and DQM Operation) .......
Command Inhibit ..............................................
No Operation (NOP) ..........................................
Load Mode Register ...........................................
Active ...................................................................
Read .....................................................................
Write ....................................................................
Precharge ............................................................
Auto Precharge ...................................................
Burst Terminate .................................................
Auto Refresh .......................................................
Self Refresh .........................................................
Operation .......................................................................
Bank/Row Activation .........................................
Reads ...................................................................
Writes ..................................................................
Precharge ............................................................
Power-Down .......................................................
7
7
7
7
7
7
9
9
9
10
10
11
11
11
11
11
11
11
11
11
12
12
13
13
14
20
22
22
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
Clock Suspend ....................................................
Burst Read/Single Write ....................................
Concurrent Auto Precharge ..............................
Truth Table 2 (CKE) .................................................
Truth Table 3 (Current State) ....................................
Truth Table 4 (Current State) ....................................
23
23
24
26
27
29
Absolute Maximum Ratings .........................................
DC Electrical Characteristics and Operating Conditions .
ICC Operating Conditions and Maximum Limits ........
Capacitance ....................................................................
31
31
31
32
AC Electrical Characteristics (Timing Table) ............ 32
Timing Waveforms
Initialize and Load Mode Register .........................
Power-Down Mode ..................................................
Clock Suspend Mode ...............................................
Auto Refresh Mode ..................................................
Self Refresh Mode ....................................................
Reads
Read - Without Auto Precharge ........................
Read - With Auto Precharge ..............................
Alternating Bank Read Accesses .......................
Read - Full-Page Burst .......................................
Read - DQM Operation ......................................
Writes
Write - Without Auto Precharge .......................
Write - With Auto Precharge .............................
Alternating Bank Write Accesses ......................
Write - Full-Page Burst ......................................
Write - DQM Operation .....................................
3
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
ROWADDRESS
LATCH
11
11
ROW
DECODER
FUNCTIONAL BLOCK DIAGRAM
4 Meg x 4 SDRAM
2,048
BANK 0
MEMORY
ARRAY
(2,048 x 1,024 x 4)
CKE
CLK
DQM
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
1,024 (x4)
CONTROL
LOGIC
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
MODE REGISTER
4
COLUMNADDRESS BUFFER
10
BURST COUNTER
12
COLUMNADDRESS LATCH
1,024
10
COLUMN
DECODER
DATA
OUTPUT
REGISTER
4
DQ0 DQ3
4
DATA
INPUT8
REGISTER
1,024
A0-A10, BA
12
REFRESH
CONTROLLER
ADDRESS
REGISTER
REFRESH
COUNTER
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
11
ROWADDRESS
MUX
1,024 (x4)
11
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
ROWADDRESS
LATCH
11
ROW
DECODER
11
2,048
4
BANK 1
MEMORY
ARRAY
(2,048 x 1,024 x 4)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
ROWADDRESS
LATCH
11
11
ROW
DECODER
FUNCTIONAL BLOCK DIAGRAM
2 Meg x 8 SDRAM
2,048
BANK 0
MEMORY
ARRAY
(2,048 x 512 x 8)
CKE
CLK
DQM
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
512 (x8)
CONTROL
LOGIC
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
MODE REGISTER
8
COLUMNADDRESS BUFFER
9
BURST COUNTER
12
COLUMNADDRESS LATCH
512
9
COLUMN
DECODER
DATA
OUTPUT
REGISTER
8
DQ0 DQ7
8
DATA
INPUT8
REGISTER
512
A0-A10, BA
12
REFRESH
CONTROLLER
ADDRESS
REGISTER
REFRESH
COUNTER
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
11
ROWADDRESS
MUX
512 (x8)
11
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
ROWADDRESS
LATCH
11
ROW
DECODER
11
2,048
5
BANK 1
MEMORY
ARRAY
(2,048 x 512 x 8)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
32
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
31
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), ACTIVE POWER-DOWN (row active in either bank), or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers, including
CLK, are disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
15
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
14, 13,
12
RAS#, CAS#,
WE#
Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered.
33
DQM
Input
Input/Output Mask: DQM is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQM is
sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z
state (after a two-clock latency) when DQM is sampled HIGH during a READ
cycle.
16
BA
Input
Bank Address: BA defines to which bank the ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA is also used to program the twelfth
bit of the Mode Register.
18-21, 24-29, 17
A0-A10
Input
Address Inputs: A0-A10 are sampled during the ACTIVE command (row-address
A0-A10) and READ/WRITE command (column-address A0-A9 [x4]; A0-A8 [x8],
with A9 as a “Don’t Care;” and with A10 defining AUTO PRECHARGE) to select
one location out of the memory array in the respective bank. A10 is sampled
during a PRECHARGE command to determine if both banks are to be
precharged (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
4, 8, 37, 41
x4: DQ0, 1, 2, 3
x8: DQ1, 3, 4, 6
x4: NC
Input
Data I/O: Data bus.
x8: DQ0, 2, 5, 7
Input
10, 11, 30, 34, 35
NC
–
5, 9, 36, 40
3, 7, 38, 42
VDDQ
VSSQ
1, 22
VDD
Supply Power Supply: +3.3V ±0.3V.
23, 44
VSS
Supply Ground.
2, 6, 39, 43
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
–
No Connect: These pins should be left unconnected.
Data I/O: Data bus.
No Connect: These pins should be left unconnected.
Supply DQ Power.
Supply DQ Ground.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
FUNCTIONAL DESCRIPTION
In general, the SDRAM is a dual memory array (the
4 Meg x 4 is a dual 2 Meg x 4, and the 2 Meg x 8 is a dual
1 Meg x 8) which operates at 3.3V and includes a synchronous interface (all signals are registered on the positive
edge of the clock signal, CLK). Each of the two internal
banks is organized with 2,048 rows and either 1,024 columns by 4 bits (4 Meg x 4) or 512 columns by 8 bits (2 Meg
x 8).
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with the ACTIVE command are used to select the
bank and row to be accessed (BA selects the bank, A0-A10
select the row). The address bits (A0-A9; A9 is a “Don’t
Care” for x8) registered coincident with the READ or
WRITE command are used to select the starting column
location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition,
command descriptions and device operation.
operating mode, and a write burst mode, as shown in
Figure 1. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode Register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or interleaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the write burst mode, and
M10 and M11 are reserved for future use.
The Mode Register must be loaded when both banks
are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed
for a given READ or WRITE command. Burst lengths of 1,
2, 4 or 8 locations are available for both the sequential
and the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely selected
by A1-A9 (A9 is “Don’t Care” for x8) when the burst length
is set to two; by A2-A9 (A9 is “Don’t Care” for x8) when the
burst length is set to four; and by A3-A9 (A9 is “Don’t
Care” for x8) when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. Full-page
bursts wrap within the page if the boundary is reached.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Once
power is applied to VDD and VDDQ (simultaneously) and
the clock is stable, the SDRAM requires a 100µs delay
prior to applying an executable command. The RAS#,
CAS#, WE# and CS# inputs should be held HIGH during
this phase of power-up.
Once the 100µs delay has been satisfied, CKE HIGH
and the PRECHARGE command can be applied (set up
and held with respect to a positive edge of CLK). Both
banks must then be precharged, thereby placing the
device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in
an unknown state, it should be loaded prior to applying
any operational command.
Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting column address, as shown in Table 1.
Register Definition
MODE REGISTER
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
Figure 1
Mode Register Definition
BA
11
A10
10
A9
9
A8
8
A6
A7
6
7
A5
5
A4
A3
4
Reserved* WB Op Mode CAS Latency
3
1
2
BT
A1
A2
Address Bus
A0
0
Table 1
Burst Definition
Burst
Length
Mode Register (Mx)
2
Burst Length
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
0
Sequential
1
Interleaved
M6 M5 M4
0
0
Reserved
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
A1
0
0
1
1
A2 A1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
8
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2
Full
x4: n = A0-A9
Cn+3, Cn+4...
Page
x8: n = A0-A8
…Cn-1,
(x4:1,024) (location 0-1,023)
(x8: 512) (location 0-511)
Cn…
CAS Latency
0
M9
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
4
Burst Type
M3
Starting Column
Order of Accesses Within a Burst
Address:
Type = Sequential Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
NOTE: 1. For a burst length of two, A1-A9 select the block
of two burst (A9 is a “Don’t Care” for x8); A0
selects the starting column within the block.
2. For a burst length of four, A2-A9 select the block
of four burst (A9 is a “Don’t Care” for x8); A0-A1
select the starting column within the block.
3. For a burst length of eight, A3-A9 select the block
of eight burst (A9 is a “Don’t Care” for x8); A0-A2
select the starting column within the block.
4. For a full-page burst, the full row is selected and
A0-A9 select the starting column (A9 is a “Don’t
Care” for x8).
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0-A9 select the unique
column to be accessed (A9 is a “Don’t Care” for
x8), and Mode Register bit M3 is ignored.
All other states reserved
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
CAS Latency
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first piece of output data. The latency can be set to
1, 2, or 3 clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1) and, provided that
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0, and the latency is
programmed to two clocks, the DQs will start driving
after T1 and the data will be valid by T2, as shown in
Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7
and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes.
The programmed burst length applies to both READ and
WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.
Figure 2
CAS LATENCY
T0
T1
T2
READ
NOP
Table 2
CAS LATENCY
CLK
COMMAND
tLZ
ALLOWABLE OPERATING
FREQUENCY (MHz)
tOH
DOUT
DQ
tAC
SPEED
CAS Latency = 1
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
CAS
CAS
CAS
LATENCY = 1 LATENCY = 2 LATENCY = 3
-8D/E
£ 33
£ 100
£ 125
-8A/B/C
£ 33
£ 83
£ 125
-10
£ 33
£ 66
£ 100
tOH
DOUT
DQ
tAC
CAS Latency = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
COMMANDS
Truth Table 1 provides a quick reference of available commands. This is followed by a written description
of each command. Two additional Truth Tables appear
following the Operation section; these tables provide
current state/next state information.
TRUTH TABLE 1 – Commands and DQM Operation
(Note: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQM
ADDR
COMMAND INHIBIT (NOP)
H
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
3
READ (Select bank and column and start READ burst)
L
H
L
H
X
Bank/Col
X
4
WRITE (Select bank and column and
start WRITE burst)
L
H
L
L
X
Bank/Col
Valid
4
BURST TERMINATE
L
H
H
L
X
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
X
5
AUTO REFRESH or
SELF REFRESH (Enter self refresh mode)
L
L
L
H
X
X
X
6, 7
LOAD MODE REGISTER
L
L
L
L
X
Op-code
X
2
Write Enable/Output Enable
–
–
–
–
L
–
Active
8
Write Inhibit/Output High-Z
–
–
–
–
H
–
High-Z
8
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
X
DQs NOTES
X
CKE is HIGH for all commands shown except SELF REFRESH.
A0-A10 and BA define the op-code written to the Mode Register.
A0-A10 provide row address, and BA determines which bank is made active (BA LOW = Bank 0; BA HIGH = Bank 1).
A0-A9 (A9 is a “Don’t Care” for x8) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA determines which bank is being read from or written to
(BA LOW = Bank 0; BA HIGH = Bank 1).
For A10 LOW, BA determines which bank is being precharged (BA LOW = Bank 0; BA HIGH = Bank 1); for A10 HIGH,
both banks are precharged and BA is a “Don’t Care.”
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
10
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©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is effectively deactivated, or deselected.
the row being accessed will be precharged at the end of
the WRITE burst; if auto precharge is not selected, the
row will remain open for subsequent accesses. Input
data appearing on the DQs is written to the memory array
subject to the DQM input logic level appearing coincident with the data. If the DQM signal is registered LOW,
the corresponding data will be written to memory; if the
DQM signal is registered HIGH, the corresponding data
inputs will be ignored, and a WRITE will not be executed
to that location.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW).
This prevents unwanted commands from being registered during idle or wait states.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-A10 and
BA. See Mode Register heading in Register Definition
section. The LOAD MODE REGISTER command can only
be issued when both banks are idle, and a subsequent
executable command cannot be issued until tMRD is
met.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in both
banks. The bank(s) will be available for a subsequent row
access some specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one
or both banks are to be precharged, and in the case where
only one bank is to be precharged, input BA selects the
bank. Otherwise BA is treated as a “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands
being issued to that bank.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA input selects the bank, and the address
provided on inputs A0-A10 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE command must be issued before opening a different row in
the same bank.
AUTO PRECHARGE
Auto precharge is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A
PRECHARGE of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except in
the full-page burst mode, where auto precharge does not
apply. Auto precharge is nonpersistent in that it is either
enabled or disabled for each individual READ or WRITE
command.
Auto precharge ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. The user
must not issue another command until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest
possible time, as described for each burst type in the
Operation section of this data sheet.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA input selects
the bank, and the address provided on inputs A0-A9 (A9
is a “Don’t Care” on x8) selects the starting column
location. The value on input A10 determines whether or
not auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of
the READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data
appears on the DQs, subject to the logic level on the DQM
input, two clocks earlier. If the DQM signal was registered HIGH, the DQs will be High-Z two clocks later; if the
DQM signal was registered LOW, the DQs will provide
valid data.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA input selects
the bank, and the address provided on inputs A0-A9 (A9
is a “Don’t Care” on x8) selects the starting column
location. The value on input A10 determines whether or
not auto precharge is used. If auto precharge is selected,
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet.
11
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©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The Micron 16Mb
SDRAM requires all of its 4,096 rows to be refreshed every
64ms (tREF). Providing a distributed AUTO REFRESH
command every 15.6µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, all 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRC) once
every 64ms.
FRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care,” with the exception of
CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to tRAS
and may remain in self refresh mode for an indefinite
period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to
CKE going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks) for tXSR because time is required for the completion of any internal refresh in progress.
A burst of 4,096 AUTO REFRESH cycles should be
completed just prior to entering and just after exiting the
self refresh mode.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the SDRAM
retains data without external clocking. The SELF RE-
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
OPERATION
Figure 3
Activating a Specific Row in a
Specific Bank
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be
activated.
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should be
divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after
the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification
of 30ns with a 90 MHz clock (11.11ns period) results in 2.7
clocks, rounded to 3. This is reflected in Figure 4, which
covers any case where 2 < tRCD (MIN)/tCK < 3. (The same
procedure is used to convert other specification limits
from time units to clock cycles.)
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to the other bank
can be issued while the first bank is being accessed,
resulting in a reduction of total row access overhead. The
minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
EXAMPLE: MEETING
T0
tRCD
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0-A10
BANK 1
BA
BANK 0
Figure 4
(MIN) WHEN 2 < tRCD (MIN)/tCK < 3
T1
T2
NOP
NOP
T3
T4
CLK
COMMAND
ACTIVE
READ or
WRITE
tRCD
DON’T CARE
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
READs
READ bursts are initiated with a READ command, as
shown in Figure 5 (A9 is a “Don’t Care”on x8).
The starting column and bank addresses are provided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive
clock edge. Figure 6 shows general timing for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A fullpage burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
A fixed-length READ burst may be followed by, or
truncated with, a READ burst (provided that auto
precharge is not activated), and a full-page READ burst
can be truncated with a subsequent READ burst. In either
case, a continuous flow of data can be maintained. The
first data element from the new burst follows either the
last element of a completed burst or the last desired data
element of a longer burst that is being truncated. The
new READ command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
Figure 5
READ Command
Figure 6
CAS Latency
CLK
CKE
T0
T1
T2
READ
NOP
CLK
COMMAND
HIGH
tLZ
tOH
DOUT
DQ
CS#
tAC
CAS Latency = 1
RAS#
T0
T1
T2
T3
READ
NOP
NOP
CLK
CAS#
COMMAND
tLZ
WE#
tOH
DOUT
DQ
tAC
CAS Latency = 2
COLUMN
ADDRESS
A0-A9
(A9 is a “Don’t Care” for x8)
ENABLE AUTO PRECHARGE
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
A10
DISABLE AUTO PRECHARGE
COMMAND
tLZ
tOH
BANK 1
DOUT
DQ
BA
tAC
BANK 0
CAS Latency = 3
DON’T CARE
UNDEFINED
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
shown in Figure 7 for CAS latencies of one, two and three;
data element n + 3 is either the last of a burst of four or the
last desired of a longer burst. The Micron 16Mb SDRAM
uses a pipelined architecture and therefore does not
require the 2n rule associated with a prefetch architec-
ture. A READ command can be initiated on any clock
cycle following a previous READ command. Full-speed
random read accesses can be performed to the same
bank, as shown in Figure 8, or each subsequent READ
may be performed to a different bank.
Figure 7
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
NOP
NOP
NOP
READ
NOP
X = 0 cycles
ADDRESS
BANK,
COL n
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
X = 1 cycle
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
15
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
Figure 8
Random READ Accesses
T0
T1
T2
T3
T4
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOP
DOUT
a
DOUT
n
DQ
NOP
DOUT
x
NOP
DOUT
m
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
16
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a WRITE burst (provided that AUTO
PRECHARGE was not activated), and a full-page READ
burst may be truncated by a WRITE burst. The WRITE
burst may be initiated on the clock edge immediately
following the last (or last desired) data element from the
READ burst, provided that I/O contention can be avoided.
In a given system design, there may be a possibility that
the device driving the input data will go Low-Z before the
SDRAM DQs go High-Z. In this case, a single-cycle delay
should occur between the last read data and the WRITE
command.
The DQM input is used to avoid I/O contention, as
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers)
to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or remain High-Z) regardless of the state of the DQM signal.
The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers)
to ensure that the written data is not masked. Figure 9
shows the case where the clock frequency allows for bus
contention to be avoided without adding a NOP cycle,
and Figure 10 shows the case where the additional NOP
is needed.
Figure 10
READ to WRITE with Extra Clock Cycle
Figure 9
READ to WRITE
T0
T1
T2
T3
T4
T5
CLK
T0
T1
T2
T3
T4
DQM
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
WRITE
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BANK,
COL b
tHZ
WRITE
DQ
BANK,
COL b
DOUT n
DIN b
tDS
tCK
NOTE:
tHZ
DOUT n
DQ
DIN b
DON‘T CARE
tDS
NOTE:
A CAS latency of three is used for illustration. The READ
command may be to either bank, and the WRITE command may be
to either bank.
A CAS latency of three and a burst of two or more is
used for illustration. The READ command may be to either
bank, and the WRITE command may be to either bank. If a
burst of one is used, then DQM is not required.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data
element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Follow-ing the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met. Note that part of the
row precharge time is hidden during the access of the last
data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum time (as described above) provides the same op-
Figure 11
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 0 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
BANK a,
ROW
DOUT
n+3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
BANK a,
ROW
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE: DQM is LOW.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
DON’T CARE
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the command and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts. The auto precharge command does not truncate fixed-length bursts and does not
apply to full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE
command, provided that auto precharge was not activated. The BURST TERMINATE command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 12 for each
possible CAS latency; data element n + 3 is the last desired data element of a longer burst.
Figure 12
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 0 cycles
ADDRESS
BANK,
COL n
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE: DQM is LOW.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
DON’T CARE
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13 (A9 is a “Don’t Care” on x8).
The starting column and bank addresses are provided with the WRITE command and auto precharge is
either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z, and any
additional input data will be ignored (see Figure 14). A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
A fixed-length WRITE burst may be followed by, or
truncated with, a WRITE burst (provided that AUTO
PRECHARGE was not activated), and a full-page WRITE
burst can be truncated with a subsequent WRITE burst.
The new WRITE command can be issued on any clock
following the previous WRITE command, and the data
provided coincident with the new command applies to
the new command. An example is shown in Figure 15.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. The Micron 16Mb SDRAM uses
a pipelined architecture and therefore does not require
the 2n rule associated with a prefetch architecture. A
WRITE command can be initiated on any clock cycle
Figure 14
WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
DIN
n
DQ
NOTE:
DIN
n+1
Burst length = 2. DQM is LOW.
Figure 13
WRITE Command
Figure 15
WRITE to WRITE
CLK
CKE
HIGH
CS#
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
RAS#
CAS#
WE#
A0-A9
COLUMN
ADDRESS
DQ
(A9 is a “Don’t Care” for x8)
ENABLE AUTO-PRECHARGE
NOTE:
A10
DISABLE AUTO-PRECHARGE
BANK 1
DIN
n
BANK,
COL b
DIN
n+1
DIN
b
DQM is LOW. Each WRITE command
may be to either bank.
DON’T CARE
BA
BANK 0
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
following a previous WRITE command. Full-speed random write accesses can be performed to the same bank,
as shown in Figure 16, or each subsequent WRITE may be
performed to a different bank.
A fixed-length WRITE burst may be followed by, or
truncated with, a READ burst (provided that auto
precharge was not activated), and a full-page WRITE
burst can be truncated with a subsequent READ burst.
Once the READ command is registered, the data inputs
will be ignored, and WRITEs will not be executed. An
example is shown in Figure 17. Data n + 1 is either the last
of a burst of two or the last desired of a longer burst.
A fixed-length WRITE burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page WRITE burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued tWR after the
clock edge at which the last desired input data element is
registered. The two-clock WRITE recovery version (A2)
requires at least two clocks, regardless of frequency, as
well as tWR being met. In addition, when truncating a
WRITE burst, the DQM signal must be used to mask
input data for the clock edge on which the PRECHARGE
command is entered. An example is shown in Figure 18.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the command and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
Figure 16
RANDOM WRITE Cycles
T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
CLK
DIN
n
DQ
T0
T1
T2
T3
WRITE
NOP
PRECHARGE
NOP
T4
T5
T6
NOP
ACTIVE
NOP
CLK
DIN
m
DIN
x
DIN
a
Figure 18
WRITE to PRECHARGE
[email protected] tCK 15ns
DQM
NOTE:
Each WRITE command may be to either bank. DQM is
LOW.
t RP
COMMAND
ADDRESS
Figure 17
WRITE to READ
T0
T1
T2
T3
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
T4
DIN
n
DIN
n+1
[email protected] tCK < 15ns
T5
CLK
DQM
t RP
COMMAND
WRITE
ADDRESS
BANK,
COL n
NOP
READ
NOP
NOP
COMMAND
NOP
ADDRESS
DIN
n
DIN
n+1
DOUT
b
PRECHARGE
BANK
(a or all)
BANK a,
COL n
NOP
NOP
ACTIVE
BANK a,
ROW
DIN
n
DIN
n+1
DOUT
b+1
The WRITE command may be to either bank, and the READ command may
be to either bank. DQM is LOW. CAS latency = 2 for illustration.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
NOP
t WR
NOTE:
NOTE:
NOP
BANK,
COL b
DQ
DQ
WRITE
DQM could remain LOW in this example if the WRITE burst is a fixed length
of two.
DON’T CARE
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
fixed-length or full-page bursts. The AUTO PRECHARGE
command does not truncate fixed-length bursts and does
not apply to full page bursts.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock
previous to the BURST TERMINATE command. This is
shown in Figure 19, where data n is the last desired data
element of a longer burst.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in both
banks. The bank(s) will be available for a subsequent row
access some specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one
or both banks are to be precharged, and in the case where
only one bank is to be precharged, input BA selects the
bank. When both banks are to be precharged, input BA is
treated as a “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
Figure 19
Terminating a WRITE Burst
T0
T1
WRITE
BURST
TERMINATE
T2
CLK
COMMAND
ADDRESS
DQ
NEXT
COMMAND
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT, when no accesses are in progress. If power-down occurs when both
banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a row
active in either bank, this mode is referred to as active
power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not
remain in the power-down state longer than the refresh
period (64ms) since no refresh operations are performed
in this mode.
The power-down state is exited by registering a
NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS).
Figure 20
PRECHARGE Command
CLK
CKE
HIGH
CS#
RAS#
Figure 21
Power-Down
CAS#
Coming out of a power-down sequence (active),
tCKS (CKE setup time) must be greater than or equal to 3ns.
WE#
((
))
((
))
CLK
tCKS
A0-A9
CKE
BANK 0 and 1
((
))
((
))
NOP
NOP
All banks idle
BANK 0 or 1
Input buffers gated off
BANK 1
Enter power-down mode.
BA
BANK 0
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
((
))
COMMAND
A10
t CKS
Exit power-down mode.
ACTIVE
tRCD
tRAS
tRC
DON’T CARE
22
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©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the
time of a suspended internal clock edge is ignored; any
data present on the DQ pins remains driven; and burst
counters are not incremented, as long as the clock is
suspended (see examples in Figures 22 and 23).
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode
Register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).
Figure 22
CLOCK SUSPEND During WRITE Burst
T0
T1
T2
T3
T4
Figure 23
CLOCK SUSPEND During READ Burst
T5
CLK
T0
CKE
CLK
INTERNAL
CLOCK
CKE
COMMAND
NOP
ADDRESS
DQ
WRITE
NOP
DIN
n+1
T2
T3
T4
T5
T6
INTERNAL
CLOCK
NOP
BANK,
COL n
DIN
n
T1
DIN
n+2
NOTE: For this example, burst length = 4 or greater,
and DQM is LOW.
COMMAND
READ
ADDRESS
BANK,
COL n
DQ
NOP
NOP
DOUT
n
NOP
DOUT
n+1
NOP
DOUT
n+2
NOP
DOUT
n+3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater,
and DQM is LOW.
DON’T CARE
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
on bank n, CAS latency later. The PRECHARGE to bank
n will begin when the READ to bank m is registered
(Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin
when the WRITE to bank m is registered (Figure 25).
READ with auto precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
Figure 24
READ with Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
NOP
Page Active
READ - AP
BANK m
NOP
READ with Burst of 4
NOP
NOP
NOP
Interrupt Burst, Precharge
NOP
Idle
tRP - BANK m
t RP - BANK n
Page Active
BANK m
BANK n,
COL a
ADDRESS
Precharge
READ with Burst of 4
BANK m,
COL d
DOUT
a+1
DOUT
a
DQ
DOUT
d
DOUT
d+1
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
Figure 25
READ with Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
READ with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
Write-Back
WRITE with Burst of 4
BANK n,
COL a
t WR - BANK m
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
DON’T CARE
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
WRITE with auto precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will
begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a WRITE
on bank n when registered. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
the WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock prior
to a WRITE to bank 1 (Figure 27).
Figure 26
WRITE with Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
READ - AP
BANK m
NOP
WRITE with Burst of 4
DIN
a
DQ
NOP
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
Interrupt Burst, Write-Back
Page Active
BANK m
NOP
BANK m,
COL d
DOUT
d+1
DOUT
d
DIN
a+1
CAS Latency = 3 (BANK m)
NOTE: 1. DQM is LOW.
Figure 27
WRITE with Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE with Burst of 4
NOP
Interrupt Burst, Write-Back
tWR - BANK n
BANK m
ADDRESS
DQ
Page Active
BANK n,
COL a
DIN
a
NOP
NOP
Precharge
tRP - BANK n
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK m,
COL d
DIN
a+1
DIN
a+2
NOTE: 1. DQM is LOW.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
WRITE - AP
BANK m
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKEn-1 CKEn
L
L
L
H
H
L
H
H
CURRENT STATE
COMMANDn
ACTIONn
NOTES
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
Clock Suspend
X
Maintain Clock Suspend
Power-Down
COMMAND INHIBIT or NOP
Exit Power-Down
5
Self Refresh
COMMAND INHIBIT or NOP
Exit Self Refresh
6
7
Clock Suspend
X
Exit Clock Suspend
Both Banks Idle
COMMAND INHIBIT or NOP
Power-Down Entry
Both Banks Idle
AUTO REFRESH
Self Refresh Entry
Reading or Writing
VALID
Clock Suspend Entry
See Truth Table 3
NOTE: 1.
2.
3.
4.
5.
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state of the SDRAM immediately prior to clock edge n.
COMMANDn is the command registered at clock edge n and ACTIONn is a result of COMMANDn .
All states and sequences not shown are illegal or reserved.
Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT
or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP
commands must be provided during the tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
edge n + 1.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
TRUTH TABLE 3 – Current State Bank n - Command to Bank n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
Any
COMMAND (ACTION)
NOTES
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
L
L
H
H
ACTIVE (Select bank and activate row)
L
L
L
H
AUTO REFRESH
7
L
L
L
L
LOAD MODE REGISTER
7
L
L
H
L
PRECHARGE
11
L
H
L
H
READ (Select bank and column and start READ burst)
10
Row Active
L
H
L
L
WRITE (Select bank and column and start WRITE burst)
10
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
8
Read
L
H
L
H
READ (Select bank and column and start new READ burst)
10
(Auto-
L
H
L
L
WRITE (Select bank and column and start WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate READ burst, start PRECHARGE)
8
Idle
Disabled)
L
H
H
L
BURST TERMINATE
9
Write
L
H
L
H
READ (Select bank and column and start READ burst)
10
(Auto-
L
H
L
L
WRITE (Select bank and column and start new WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
8
Disabled)
L
H
H
L
BURST TERMINATE
9
NOTE: 1. This table applies when CKE n-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the
previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank, and the commands shown
are those allowed to be issued to that bank when it is in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged and tRP has been met.
Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth
Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met,
the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met,
the bank will be in the row active state.
Read w/AutoPrecharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is
met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been
met. Once tMRD is met, the SDRAM will be in the all banks idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that both banks are idle.
8. May or may not be bank-specific; if both banks are to be precharged, both must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
TRUTH TABLE 4 – Current State Bank n - Command to Bank m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
Any
Idle
COMMAND (ACTION)
NOTES
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
X
X
X
X
Any command otherwise allowed to bank m
Row
L
L
H
H
ACTIVE (Select and activate row)
Activating,
L
H
L
H
READ (Select column and start READ burst)
7
Active, or
L
H
L
L
WRITE (Select column and start WRITE burst)
7
Precharging
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (Select and activate row)
(Auto-
L
H
L
H
READ (Select column and start new READ burst)
7, 10
Precharge
L
H
L
L
WRITE (Select column and start WRITE burst)
7, 11
Disabled)
L
L
H
L
PRECHARGE
Write
L
L
H
H
ACTIVE (Select and activate row)
9
(Auto-
L
H
L
H
READ (Select column and start READ burst)
7, 12
Precharge
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 13
Disabled)
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (Select and activate row)
(With Auto-
L
H
L
H
READ (Select column and start new READ burst)
7, 8, 14
Precharge)
L
H
L
L
WRITE (Select column and start WRITE burst)
7, 8, 15
L
L
H
L
PRECHARGE
Write
L
L
H
H
ACTIVE (Select and activate row)
(With Auto-
L
H
L
H
READ (Select column and start READ burst)
7, 8, 16
Precharge)
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 8, 17
L
L
H
L
PRECHARGE
9
9
9
NOTE: 1. This table applies when CKE n-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no
register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or
been terminated.
Read w/AutoPrecharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/AutoPrecharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the
WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last
valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD/VDDQ Supply
Relative to VSS ............................................ -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS ............................................ -1V to +4.6V
Operating Temperature, TA (ambient) ....... 0°C to +70°C
Storage Temperature (plastic) .............. -55°C to +150°C
Power Dissipation ......................................................... 1W
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 6; notes appear on page 34) (0°C £ TA £ 70°C; VDD/VDDQ = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
SUPPLY VOLTAGE
VDD/VDDQ
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
VIH
2
VDD + 0.3
V
23
INPUT LOW VOLTAGE: Logic 0; All inputs
VIL
-0.5
0.8
V
23
II
-5
5
µA
OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V £ VOUT £ VDDQ
IOZ
-5
5
µA
OUTPUT LEVELS:
Output High Voltage (IOUT = -2mA)
Output Low Voltage (IOUT = 2mA)
VOH
2.4
–
V
VOL
–
0.4
V
INPUT LEAKAGE CURRENT:
Any input 0V £ VIN £ VDD
(All other pins not under test = 0V)
UNITS NOTES
ICC SPECIFICATIONS AND CONDITIONS
(Notes: 1, 6, 11, 13; notes appear on page 34) (0°C £ TA £ 70°C; VDD/VDDQ = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
SYMBOL
-8B
-10
OPERATING CURRENT: Active Mode;
Burst = 2; READ or WRITE; tRC = tRC (MIN);
CAS latency = 3; tCK = 10ns (15ns for -10)
ICC1
105
90
mA
STANDBY CURRENT: Power-Down Mode; All banks idle;
CKE = LOW; tCK = 10ns (15ns for -10)
ICC2
3
2
mA
STANDBY CURRENT: Active Mode;
CKE = HIGH; CS# = HIGH; tCK = 10ns (15ns for -10);
All banks active after tRCD met; No accesses in progress
ICC3
45
40
mA
3, 12,
19
OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; tCK = 10ns (15ns for -10); All banks active;
CAS latency = 3
I CC4
125
85
mA
3, 18,
19
AUTO REFRESH CURRENT:
tRC = tRC (MIN); CAS latency = 3;
CKE = HIGH; CS# = HIGH; tCK = 10ns (15ns for -10)
ICC5
95
85
mA
3, 12,
18, 19
SELF REFRESH CURRENT: CKE £ 0.2V
ICC6
1
2
mA
4
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
31
UNITS NOTES
3, 18,
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
CAPACITANCE
PARAMETER
SYMBOL
MIN
CI1
2.5
4.0
pF
2
Input Capacitance: All other input-only pins
CI2
2.5
5.0
pF
2
Input/Output Capacitance: DQs
CIO
4.0
6.5
pF
2
Input Capacitance: CLK
MAX UNITS NOTES
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 34) (0°C £ TA £ +70°C)
AC CHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
Data-out low-impedance time
Data-out hold time
ACTIVE to PRECHARGE command
AUTO REFRESH, ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (2,048 or 4,096 rows)
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time
WRITE recovery time
-8B
A1 version
SYMBOL
tAC (3)
tAC (2)
tAC (1)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCK (1)
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ (3)
tHZ (2)
tHZ (1)
tLZ
tOH
tRAS
tRC
tRCD
tREF
tRP
tRRD
tT
tWR
A2 version
tWR
CL = 3
CL = 2
CL = 1
CL = 3
CL = 2
CL = 1
CL = 3
CL = 2
CL = 1
tXSR
Exit SELF REFRESH to ACTIVE command
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
32
MIN
-10
MAX
6
9
27
1
2
3
3
8
12
30
1
2
1
2
1
2
MIN
1
3
3.5
3.5
10
15
30
1
3
1
3
1
3
6
7
15
1
3
50
80
20
120,000
2
3
60
90
30
64
24
20
0.3
1
10
2
15
80
1.2
30
20
1
1
10
2
15
90
MAX
7.5
9
27
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
ns
10
ns
15
ns
ns
ns
120,000
ns
ns
ns
64
ms
ns
ns
1.2
ns
tCK
ns
tCK
ns
ns
NOTES
22
22
24
22, 24
24
10
10
10
22
22
22
7
25
26
25
26
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 34) (0°C £ TA £ +70°C)
PARAMETER
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
A1 version
A2 version
A1 version
A2 version
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
A1 version
A2 version
LOAD MODE REGISTER command to ACTIVE or REFRESH command
Data-out to high-impedance from PRECHARGE command
CL = 3
CL = 2
CL = 1
SYMBOL
tCCD
tCKED
tPED
tDQD
tDQM
tDQZ
tDWD
tDAL
tDAL
tDPL
tDPL
tBDL
tCDL
tRDL
tRDL
tMRD
tROH (3)
tROH (2)
tROH (1)
-8B
1
1
1
0
0
2
0
4
5
1
2
1
1
1
2
2
3
2
1
-10
1
1
1
0
0
2
0
3
4
1
2
1
1
1
2
2
3
2
1
UNITS
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
NOTES
17
14
14
17
17
17
17
15, 21
15, 21
16, 21
16, 21
17
17
16, 21
16, 21
27
17
17
17
ELECTRICAL TIMING CHARACTERISTICS BETWEEN -8 SPEED OPTIONS
(Notes: 5, 6, 8, 9, 11, 24; notes appear on page 34) (0°C £ TA £ +70°C)
AC CHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
Clock cycle time
ACTIVE to READ or WRITE delay
PRECHARGE command period
AUTO REFRESH, ACTIVE command period
WRITE recovery time
100 MHz Speed Reference (CL-tRCD-tRP)
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
SYM
CL = 3 tAC (3)
CL = 2 tAC (2)
CL = 1 tAC (1)
CL = 3 tCK (3)
CL = 2 tCK (2)
CL = 1 tCK (1)
tRCD
tRP
tRC
A1 version tWR
A2 version tWR
-8E
MIN MAX
6
6
27
8
10
30
20
20
70
na
2
2-2-2
33
-8D
MIN MAX
6
7
27
8
10
30
20
20
70
na
2
2-2-2
-8C
MIN MAX
6
9
27
8
12
30
20
20
70
1
2
3-2-2
-8B
MIN MAX
6
9
27
8
12
30
20
24
80
1
2
3-2-3
-8A
MIN MAX UNITS NOTES
6
ns
22
9
ns
22
27
ns
22
8
ns
22
12
ns
22
30
ns
22
24
ns
22
24
ns
22
80
ns
22
tCK
1
21
tCK
2
21
3-3-3
CLKs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
NOTES
12. Other input signals are allowed to transition no
more than once in any 30ns period (20ns on -8) and
are otherwise at valid VIH or VIL levels.
13. ICC specifications are tested after the device is
properly initialized.
14. Timing actually specified by tCKS; clock(s) specified
as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
18. The ICC current will decrease as the CAS latency is
reduced. This is due to the fact that the maximum
cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every
30ns (20ns on -8).
20. CLK must be toggled a minimum of two times
during this period.
21. Based on tCK = 100 MHz for -8 and 66 MHz for -10.
22. These five parameters vary between speed grades
and define the differences between the -8 SDRAM
speeds: -8A, -8B, -8C, -8D, and -8E. All other -8
timing parameters remain constant.
23. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width £ 10ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width £ 10ns, and the pulse
width cannot be greater than one third of the cycle
rate.
24. The clock frequency must remain constant during
access or precharge states (READ, WRITE, including
tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
25. Auto precharge mode only.
26. Precharge mode only.
27. JEDEC and PC100 specify three clocks.
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
3. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C £ TA £ 70°C) is
ensured.
6. An initial pause of 100µs is required after power-up,
followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD and
VDDQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated
any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH
and VIL (or between VIL and VIH) in a monotonic
manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
11. AC timing and ICC tests have VIL = 0V and VIH = 3V,
with timing referenced to 1.5V crossover point.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
INITIALIZE AND LOAD MODE REGISTER
T0
CLK
((
))
tCKS
CKE
T1
tCK
tCKH
((
))
((
))
Tn + 1
((
))
NOP
((
))
tCMS
PRECHARGE
((
))
((
))
To + 1
tCL
((
))
((
))
tCH
((
))
((
))
((
))
((
))
((
))
tCMH
COMMAND
((
))
((
))
((
))
NOP
NOP
((
))
AUTO
REFRESH
DQM
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ADDRESS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DQ
((
))
BANK(S)
High-Z
Tp + 2
Tp + 3
((
))
((
))
NOP
NOP
((
))
AUTO
REFRESH
Tp + 1
LOAD MODE
REGISTER
tAS
NOP
ACTIVE
tAH
BANK,
ROW
CODE
((
))
tRP
T=100µs
Power-up:
VDD and
CLK stable.
Precharge
all banks.
tRC
tRC
AUTO REFRESH
AUTO REFRESH
tMRD
1, 3, 4
Program Mode Register.
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
MIN
1
2
3
-8B
MAX
MIN
1
3
3.5
-10
MAX
UNITS
ns
ns
ns
SYMBOL*
tCKS
tCMH
tCMS
MIN
UNITS
ns
ns
3
2
90
tCK
30
ns
tMRD3
(3)
ns
ns
tRC
2
2
80
(2)
tCKH
12
1
15
1
ns
ns
tRP
24
tCK
-10
MAX
3
1
3.5
10
tCK
MIN
2
1
3
8
tCL
-8B
MAX
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1.
2.
3.
4.
The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “Don’t Care.”
JEDEC and PC100 specify three clocks.
Outputs are guaranteed High-Z after command is issued.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
POWER-DOWN MODE 1
T0
T1
T2
tCK
CLK
((
))
((
))
tCL
tCH
tCKS
CKE
Tn + 2
tCKS
((
))
tCKS
tCKH
tCMS
tCMH
COMMAND
Tn + 1
PRECHARGE
NOP
((
))
((
))
NOP
NOP
ACTIVE
((
))
((
))
DQM
tAS
ADDRESS
tAH
((
))
((
))
BANK(S)
High-Z
((
))
DQ
Two clock cycles
Precharge all
active banks.
BANK,
ROW
Input buffers gated off while
in power-down mode.
All banks idle.
All banks idle, enter
power-down mode.
Exit power-down mode.
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK
(3)
MIN
-8B
MAX
MIN
-10
MAX
UNITS
SYMBOL*
1
2
3
1
3
3.5
ns
ns
ns
tCK
3
8
3.5
10
ns
ns
tCMH
(2)
tCKH
tCKS
tCMS
MIN
-8B
MAX
MIN
-10
MAX
UNITS
12
1
15
1
ns
ns
2
1
2
3
1
3
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
CLOCK SUSPEND MODE 1
T0
T1
T2
tCK
CLK
T3
T4
T5
T6
T7
T8
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS
tCMH
COMMAND
READ
NOP
tCMS
NOP
NOP
NOP
NOP
WRITE
NOP
tCMH
DQM
tAS
A0-A9
tAH
COLUMN m2
tAS
tAH
tAS
tAH
COLUMN e2
A10
BA
BANK
BANK
tAC
tOH
tAC
DQ
DOUT m
tLZ
tHZ
DOUT m+1
tDS
tDH
DIN e
DIN e+1
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAC(3)
MIN
tAC(2)
-8B
MAX
6
MIN
-10
MAX
7.5
UNITS
ns
SYMBOL*
tCKS
MIN
2
-8B
MAX
MIN
3
-10
MAX
UNITS
ns
1
1
ns
ns
tCMH
tAH
tAS
2
3
3
3
3.5
3.5
ns
ns
ns
tDH
tHZ
(3)
6
8
8
12
10
15
ns
ns
tHZ
(2)
7
10
tLZ
1
2
ns
ns
1
1
ns
tOH
3
3
ns
tCH
tCL
tCK
(3)
tCK (2)
tCKH
9
9
tCMS
tDS
1
2
1
3
ns
ns
1
2
1
3
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.
2. Column-address A9 is a “Don’t Care” on x8 version.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
AUTO REFRESH MODE
T0
T1
CLK
T2
tCK
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
AUTO
REFRESH
NOP
NOP
DQM
tAS
ADDRESS
DQ
To + 1
((
))
((
))
tCL
((
))
CKE
COMMAND
Tn +1
((
))
((
))
((
))
((
))
( ( NOP
))
AUTO
REFRESH
NOP
((
))
( ( NOP
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ACTIVE
tAH
BANK(S)
High-Z
tRP
tRC
BANK,
ROW
tRC
Precharge all
active banks.
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK
(3)
tCK (2)
MIN
1
-8B
MAX
MIN
1
-10
MAX
UNITS
ns
SYMBOL*
tCKH
MIN
-8B
MAX
MIN
-10
MAX
UNITS
1
2
1
1
3
1
ns
ns
ns
tRC
2
80
3
90
ns
ns
tRP
24
30
ns
2
3
3
3.5
ns
ns
tCKS
3
8
12
3.5
10
15
ns
ns
ns
tCMS
tCMH
*CAS latency indicated in parentheses.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
SELF REFRESH MODE
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
> tRAS
CKE
tCKS
Tn + 1
((
))
((
))
((
))
((
))
((
))
tCKH
((
))
((
))
To + 1
To + 2
tCKS
tCMS tCMH
COMMAND
PRECHARGE
((
))
((
))
AUTO
REFRESH
NOP
DQM
tAS
ADDRESS
DQ
((
))
AUTO
REFRESH
NOP ( (
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tAH
BANK(S)
High-Z
((
))
((
))
tRP
tXSR
Precharge all
active banks.
Enter self
refresh mode.
Exit self refresh mode.
(Restart refresh time base.)
CLK stable prior to exiting
self refresh mode.
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK
(3)
(2)
tCKH
tCK
MIN
1
2
-8B
MAX
MIN
1
3
-10
MAX
UNITS
ns
ns
SYMBOL*
tCKS
tCMH
3
3
3.5
3.5
ns
ns
tCMS
8
12
1
10
15
1
ns
ns
ns
tRP
tRAS
tXSR
MIN
2
1
2
50
24
80
-8B
MAX
120,000
MIN
3
1
3
60
30
90
-10
MAX
120,000
UNITS
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
READ – WITHOUT AUTO PRECHARGE 1
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
PRECHARGE
tCMS tCMH
DQM
tAS
A0-A9
COLUMN m2
ROW
tAS
ROW
tAH
BANK 0 and 1
ROW
A10
tAS
BA
tAH
ROW
BANK 0 or 1
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK(S)
tAC
tOH
tAC
DQ
tOH
DOUT m
tLZ
tRCD
tAC
DOUT m+1
BANK
tAC
tOH
tOH
DOUT m+2
DOUT m+3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8B
SYMBOL*
tAC(3)
MIN
tAC(2)
tAH
tAS
tCH
tCL
tCK
(3)
(2)
tCKH
tCK
tCKS
-10
MAX
6
MIN
MAX
7.5
UNITS
ns
9
SYMBOL*
tCMH
MIN
1
1
3
ns
ns
ns
tCMS
1
2
3
3
3.5
3.5
ns
ns
tLZ
8
12
1
10
15
1
ns
ns
ns
tRAS
tRCD
50
80
20
2
3
ns
tRP
24
9
2
tHZ
(3)
tHZ (2)
tOH
tRC
-8B
MAX
MIN
1
-10
MAX
3
6
7
1
3
8
10
2
3
120,000
60
90
30
30
UNITS
ns
ns
ns
ns
ns
ns
120,000
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. Column-address A9 is a “Don’t Care” on x8 version.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
READ – WITH AUTO PRECHARGE
T0
T1
t CK
CLK
T2
T3
T4
T5
NOP
NOP
1
T6
T7
T8
NOP
ACTIVE
t CL
t CH
t CKS t CKH
CKE
t CMS t CMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
t CMS t CMH
DQM
tAS
A0-A9
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA
COLUMN m2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
BANK
t AC
t OH
t AC
DQ
DOUT m
t LZ
t RCD
t AC
t OH
DOUT m+1
t AC
t OH
t OH
DOUT m+2
DOUT m+3
t HZ
t RP
CAS Latency
t RAS
t RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAC(3)
tAC(2)
tAH
MIN
-8B
MAX
6
9
MIN
-10
MAX
7.5
9
-8B
UNITS
ns
ns
SYMBOL*
tCMH
tCMS
1
2
1
3
ns
ns
tHZ
3.5
3.5
10
ns
ns
ns
tLZ
(3)
3
3
8
(2)
tCKH
12
1
15
1
ns
ns
tRC
2
3
ns
tAS
tCH
tCL
tCK
tCK
tCKS
tHZ
MIN
1
2
(3)
(2)
tOH
tRAS
-10
MAX
MIN
1
3
6
7
1
3
50
120,000
2
3
60
MAX
UNITS
ns
ns
8
10
ns
ns
120,000
ns
ns
ns
tRCD
80
20
90
30
ns
ns
tRP
24
30
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. Column-address A9 is a “Don’t Care” on x8 version.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
ALTERNATING BANK READ ACCESSES
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
ACTIVE
1
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
tCMS tCMH
DQM
tAS
A0-A9
tAH
COLUMN b2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA
COLUMN m2
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
BANK 1
tAC
DQ
DOUT m
tLZ
tRCD - BANK 0
BANK 1
tAC
tOH
tAC
tOH
DOUT m+1
BANK 0
tAC
tOH
tAC
tOH
DOUT m+2
tAC
tOH
DOUT m+3
DOUT
tRP - BANK 0
CAS Latency - BANK 0
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 1
tRRD
CAS Latency - BANK 1
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8B
SYMBOL*
tAC(3)
MIN
tAC(2)
tAH
tAS
tCH
tCL
tCK
(3)
tCK (2)
tCKH
tCKS
-10
MAX
6
MIN
9
MAX
7.5
UNITS
ns
9
tCMS
SYMBOL*
tCMH
1
2
1
3
ns
ns
ns
3
3
3.5
3.5
ns
ns
tRAS
8
12
1
10
15
1
ns
ns
ns
tRCD
2
3
ns
tLZ
tOH
tRC
MIN
1
-8B
MAX
2
1
3
50
80
MIN
1
-10
MAX
3
2
120,000
3
60
90
UNITS
ns
ns
ns
120,000
ns
ns
ns
tRP
20
24
30
30
ns
ns
tRRD
20
20
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. Column-address A9 is a “Don’t Care” on x8 version.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
READ – FULL-PAGE BURST 1
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
((
))
((
))
tCK
tCH
tCKS
Tn + 1
Tn + 2
Tn + 3
Tn + 4
tCKH
((
))
((
))
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
tCMS tCMH
A0-A9
tAH
tAS
A10
tAH
BA
NOP
NOP
((
))
((
))
ROW
tAS
BURST TERM
((
))
((
))
COLUMN m2
ROW
NOP
((
))
((
))
DQM
tAS
((
))
((
))
NOP
tAH
BANK
((
))
((
))
BANK
tAC
tAC
OH
DOUT m
DQ
tAC
tOH
DOUT m+1
tLZ
tAC ( (
tOH ) )
((
))
((
))
DOUT m+2
tAC
tAC
tOH
tOH
DOUT m-1
tOH
DOUT m
DOUT m+1
tHZ
1,024 (x4), 512 (x8) locations within
the same row.
tRCD
Full page completed.
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.3
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8B
SYMBOL*
tAC(3)
MIN
tAC(2)
tAH
tAS
tCH
tCL
tCK
(3)
(2)
tCKH
tCK
-10
MAX
6
MIN
-8B
MAX
7.5
UNITS
ns
9
SYMBOL*
tCKS
MIN
2
-10
MAX
MIN
3
MAX
UNITS
ns
1
3
ns
ns
ns
tCMH
1
2
tHZ
(3)
6
8
3
3
3.5
3.5
ns
ns
tHZ
(2)
7
10
tLZ
1
2
ns
ns
8
12
1
10
15
1
ns
ns
ns
tOH
3
20
3
30
ns
ns
9
tCMS
tRCD
1
2
1
3
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. Column-address A9 is a “Don’t Care” on x8 version.
3. Page left open; no tRP.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
READ – DQM OPERATION 1
T0
T1
T2
tCK
CLK
tCKS
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
tCMS tCMH
DQM
tAS
A0-A9
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA
COLUMN m2
ROW
tAS
A10
tAH
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
tAC
tOH
DQ
DOUT m
tLZ
tRCD
tAC
tOH
tOH
DOUT m+2
DOUT m+3
tLZ
tHZ
tHZ
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8B
SYMBOL*
MIN
tAC(3)
tAS
tCH
tCL
tCK
(3)
tCK (2)
tCKH
MIN
6
9
-8B
SYMBOL*
MIN
-10
MAX
UNITS
MAX
MIN
7.5
9
tCKS
2
3
MAX
UNITS
ns
tCMH
1
2
1
3
ns
ns
1
2
1
3
ns
ns
ns
ns
3
3
3.5
3.5
ns
ns
tHZ
tLZ
1
2
ns
ns
ns
8
12
1
10
15
1
ns
ns
ns
tOH
3
20
3
30
ns
ns
tAC(2)
tAH
-10
MAX
tCMS
tHZ
(3)
(2)
tRCD
6
7
8
10
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. Column-address A9 is a “Don’t Care” on x8 version.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
WRITE – WITHOUT AUTO PRECHARGE 1
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
NOP
NOP
NOP
T7
T8
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
tCMS tCMH
DQM
tAS
A0-A9
ROW
tAH
ALL BANKs
ROW
tAS
BA
COLUMN m 3
ROW
tAS
A10
tAH
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
tDS
tDH
DIN m
DQ
tDH
DIN m+1
tDS
tDH
DIN m+2
tDS
BANK
tDH
DIN m+3
t WR 2
tRCD
tRAS
tRP
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8B
SYMBOL*
MIN
tAH
1
tAS
2
tCH
(3)
3
3
8
(2)
tCKH
12
1
2
1
tCL
tCK
tCK
tCKS
tCMH
MAX
-10
MIN
-8B
ns
SYMBOL*
tCMS
3
ns
tDH
3.5
3.5
10
ns
ns
ns
tDS
15
1
ns
ns
tRCD
3
1
ns
ns
tWR
1
MAX
UNITS
MIN
2
1
2
50
tRAS
tRC
tRP
[A1]
tWR [A2]
MAX
120,000
-10
MIN
3
1
3
60
MAX
120,000
UNITS
ns
ns
ns
ns
80
20
90
30
ns
ns
24
10
15
30
10
15
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE with the A1
version.
2. 10ns (A1) or 15ns (A2) are required between <DIN m+3> and the PRECHARGE command, regardless of frequency.
3. Column-address A9 is a “Don’t Care” on x8 version.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
WRITE – WITH AUTO PRECHARGE
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
1
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
A0-A9
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA
COLUMN m 3
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
tDS
BANK
tDH
tDS
DIN m
DQ
tDH
tDS
DIN m+1
tDH
DIN m+2
tDS
tDH
DIN m+3
tWR 2
tRCD
tRAS
tRP
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAH
MIN
1
tAS
-8B
MAX
MIN
1
-10
MAX
UNITS
ns
SYMBOL*
tCMS
2
3
3
3.5
ns
ns
tDH
3
8
12
3.5
10
15
ns
ns
ns
tRAS
1
3
ns
ns
tRP
tCKS
1
2
tWR
tCMH
1
1
ns
tWR
tCH
tCL
tCK
(3)
tCK (2)
tCKH
MIN
-8B
MAX
2
1
2
tDS
50
80
tRC
tRCD
MIN
-10
MAX
3
1
3
120,000
60
90
UNITS
ns
ns
ns
120,000
ns
ns
[A1]
20
24
1
30
30
1
ns
ns
tCK
[A2]
2
2
tCK
*CAS latency indicated in parentheses.
NOTE: 1.
2.
3.
4.
For this example, the burst length = 4 with the A2 version, i.e., two-clock minimum for tWR.
The A1 version requires one clock between <DIN m+3> and the PRECHARGE command, provided tWR is met.
Column-address A9 is a “Don’t Care” on x8 version.
With AUTO PRECHARGE.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
ALTERNATING BANK WRITE ACCESSES 1
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQM
tAS
A0-A9
tAH
COLUMN b 3
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA
COLUMN m 3
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
tDS
BANK 1
tDH
tDS
DIN m
DQ
tDH
DIN m+1
tDS
BANK 1
tDH
tDS
DIN m+2
tDH
tDS
DIN m+3
BANK 0
tDH
tDS
DIN b
tDS
DIN b+1
tWR 2- BANK 0
tRCD - BANK 0
tDH
tDH
DIN b+2
tRCD - BANK 0
tRP - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 1
tRRD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-8B
SYMBOL*
tAH
tAS
tCH
tCL
tCK
(3)
tCK
(2)
tCKH
tCKS
tCMH
tCMS
MIN
1
2
3
MAX
-10
MIN
1
3
3.5
MAX
-8B
UNITS
ns
ns
ns
SYMBOL*
tDH
tDS
tRAS
3
8
3.5
10
ns
ns
tRC
12
1
2
15
1
3
ns
ns
ns
tRP
tWR
1
2
1
3
ns
ns
tWR
MIN
1
2
50
MAX
120,000
-10
MIN
1
3
60
MAX
UNITS
ns
ns
120,000
ns
80
20
90
30
ns
ns
[A1]
24
20
Note 2
30
20
Note 2
ns
ns
–
[A2]
Note 2
Note 2
–
tRCD
tRRD
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4 with the A2 version, i.e., one-clock minimum for tWR.
2. The A1 version requires one clock with AUTO PRECHARGE or 10ns with PRECHARGE between <DIN m+3> and the
PRECHARGE command. The A2 version requires two clocks with AUTO PRECHARGE or 15ns with PRECHARGE.
3. Column-address A9 is a “Don’t Care” on x8 version.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
WRITE – FULL-PAGE BURST
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
tCMS tCMH
ACTIVE
NOP
WRITE
NOP
NOP
NOP
tCMS tCMH
A0-A9
A10
((
))
((
))
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m1
tAH
((
))
((
))
ROW
tAS
BA
tAH
ROW
tAS
Tn + 3
((
))
((
))
DQM
tAS
Tn + 2
((
))
((
))
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
tDS
DIN m+1
tDH
tDS
DIN m+2
tDH
DIN m+3
tRCD
((
))
((
))
tDS
tDH
tDS
tDH
DIN m-1
1,024 (x4), 512 (x8) locations
within the same row.
Full page completed.
Full-page burst does not
self-terminate. Can use
2, 3
BURST TERMINATE command.
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK
(3)
tCK (2)
tCKH
MIN
1
-8B
MAX
MIN
1
-10
MAX
SYMBOL*
UNITS
ns
tCKS
2
3
3
3.5
ns
ns
tCMH
3
8
12
3.5
10
15
ns
ns
ns
tDH
1
1
ns
tCMS
tDS
tRCD
MIN
-8B
MAX
MIN
-10
MAX
UNITS
2
1
2
3
1
3
ns
ns
ns
1
2
1
3
ns
ns
20
30
ns
*CAS latency indicated in parentheses.
NOTE: 1. Column-address A9 is a “Don’t Care” on x8 version.
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open, no tRP.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
WRITE – DQM OPERATION 1
T0
T1
T2
tCK
CLK
tCKS
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
A0-A9
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA
COLUMN m2
ROW
tAS
A10
tAH
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m+2
tDS
tDH
DIN m+3
tRCD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK
(3)
tCK (2)
tCKH
MIN
1
-8B
MAX
MIN
1
-10
MAX
UNITS
ns
SYMBOL*
tCKS
2
3
3
3.5
ns
ns
tCMH
3
8
12
3.5
10
15
ns
ns
ns
tDH
1
1
ns
tCMS
tDS
tRCD
MIN
-8B
MAX
MIN
-10
MAX
UNITS
2
1
2
3
1
3
ns
ns
ns
1
2
1
3
ns
ns
20
30
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. Column-address A9 is a “Don’t Care” on x8 version.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
16 MEG: x4, x8
SDRAM
44-PIN PLASTIC TSOP (400 mil)
.728 (18.49)
.722 (18.34)
.0315 (0.80)
44
.467 (11.86)
SEE DETAIL A
.459 (11.66)
.402 (10.21)
.398 (10.11)
1
22
PIN #1 ID
.0315 (0.80) TYP
.007 (0.18)
.018 (0.45)
TYP
.012 (0.30)
.005 (0.13)
.010 (0.25)
.004 (0.10)
GAGE
PLANE
.047 (1.2) MAX
.006 (0.20)
.002 (0.05)
.024 (0.60)
.016 (0.40)
DETAIL A
.0315 (0.80)
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.