MICRON MT48LC32M16A2

512Mb: x4, x8, x16 SDRAM
Features
Synchronous DRAM
MT48LC128M4A2 – 32 Meg x 4 x 4 banks
MT48LC64M8A2 – 16 Meg x 8 x 4 banks
MT48LC32M16A2 – 8 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site
Features
Options
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
and auto refresh modes
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
Table 1:
Address Table
Parameter
32 Meg x 4 32 Meg x 8 32 Meg x 16
32 Meg x 4 16 Meg x 8
x 4 banks
x 4 banks
8K
8K
Refresh count
8K (A0–A12) 8K (A0–A12)
Row
addressing
4 (BA0, BA1) 4 (BA0, BA1)
Bank
addressing
4K (A0–A9, 2K (A0–A9,
Column
A11, A12)
A11)
addressing
Configuration
Table 2:
Speed
Grade
-7E
-75
-7E
-75
• Configurations
– 128 Meg x 4 (32 Meg x 4 x 4 banks)
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
• WRITE recovery (tWR)
– tWR = “2 CLK”1
• Plastic package – OCPL2
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free
• Timing (cycle time)
– 7.5ns @ CL = 2 (PC133)
– [email protected] CL = 3 (PC133)
• Self refresh
– Standard
– Low power
• Operating temperature range
– Commercial (0oC to +70oC)
– Industrial (–40oC +85oC)
• Revision
8 Meg x 16
x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
Notes: 1.
2.
3.
4.
1K (A0–A9)
Key Timing Parameters
Access Time
Clock
Frequency CL = 2 CL = 3
143 MHz
133 MHz
133 MHz
100 MHz
–
–
5.4ns
6ns
Setup
Time
Hold
Time
1.5ns
1.5ns
1.5ns
1.5ns
0.8ns
0.8ns
0.8ns
0.8ns
5.4ns
5.4ns
–
–
Marking
128M4
64M8
32M16
A2
TG
P
-7E4
-75
None
L3
None
IT
:C
Refer to Micron technical note: TN-48-05.
Off-center parting line.
Contact factory for availability.
Available on x4 and x8 only.
Part Number Example:
MT48LC32M16A2P-75:C
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAMfront.fm - Rev. L 10/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512Mb: x4, x8, x16 SDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
WRITE Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Burst READ/Single WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAMTOC.fm - Rev. L 10/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure 50:
Figure 51:
Figure 52:
128 Meg x 4 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
64 Meg x 8 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
32 Meg x 16 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Assignment (Top View) 54-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Activating a Specific Row In a Specific Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Example Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK ≤ 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
CLOCK SUSPEND During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
CLOCK SUSPEND During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
READ with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
READ with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
WRITE with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
WRITE with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Auto-Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Single READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
READ – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
READ DQM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Single WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Single WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Alternating Bank WRITE Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
WRITE – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
54-Pin Plastic TSOP (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
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512MbSDRAMLOF.fm - Rev. L 10/07 EN
3
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512Mb: x4, x8, x16 SDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Truth Table 1 – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Truth Table 3 – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Summary of Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
DC Electrical Characteristics And Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .45
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512MbSDRAMLOT.fm - Rev. L 10/07 EN
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512Mb: x4, x8, x16 SDRAM
General Description
General Description
The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous
interface (all signals are registered on the positive edge of the clock signal, CLK). Each of
the x4’s 134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each
of the x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by 8 bits.
Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by
16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A12 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the PRECHARGE cycles and provide seamless, high-speed, random-access
operation.
The 512Mb SDRAM is designed to operate at 3.3V. An auto refresh mode is provided,
along with a power-saving, power-down mode. All inputs and outputs are LVTTLcompatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time, and
the capability to randomly change column addresses on each clock cycle during a burst
access.
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512Mb: x4, x8, x16 SDRAM
General Description
Figure 1:
128 Meg x 4 SDRAM Functional Block Diagram
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 13
COUNTER
12
ROWADDRESS
MUX
13
13
BANK0
ROWADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 4,096 x 4)
1
DQM
SENSE AMPLIFIERS
4
16384
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
4
4
4096
(x4)
1
DQ0–
DQ3
DATA
INPUT
REGISTER
COLUMN
DECODER
12
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512MbSDRAM.fm - Rev. L 10/07 EN
COLUMNADDRESS
COUNTER/
LATCH
12
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512Mb: x4, x8, x16 SDRAM
General Description
Figure 2:
64 Meg x 8 SDRAM Functional Block Diagram
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 13
COUNTER
12
ROWADDRESS
MUX
13
13
BANK0
ROWADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 2,048 x 8)
1
DQM
SENSE AMPLIFIERS
8
16384
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
8
8
2048
(x8)
1
DQ0–
DQ7
DATA
INPUT
REGISTER
COLUMN
DECODER
11
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512MbSDRAM.fm - Rev. L 10/07 EN
COLUMNADDRESS
COUNTER/
LATCH
11
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512Mb: x4, x8, x16 SDRAM
General Description
Figure 3:
32 Meg x 16 SDRAM Functional Block Diagram
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 13
COUNTER
12
ROWADDRESS
MUX
13
13
BANK0
ROWADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 1,024 x 16)
2
DQML,
DQMH
SENSE AMPLIFIERS
16
16384
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A12,
BA0, BA1
15
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
16
16
1024
(x16)
2
DQ0–
DQ15
DATA
INPUT
REGISTER
COLUMN
DECODER
10
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512MbSDRAM.fm - Rev. L 10/07 EN
COLUMNADDRESS
COUNTER/
LATCH
10
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512Mb: x4, x8, x16 SDRAM
General Description
Figure 4:
Pin Assignment (Top View) 54-Pin TSOP
x4 x8 x16
-
-
NC DQ0
-
-
NC NC
DQ0 DQ1
-
-
NC NC
NC DQ2
-
-
NC NC
DQ1 DQ3
Note:
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512MbSDRAM.fm - Rev. L 10/07 EN
-
-
NC
NC
-
-
NC
NC
-
-
VDD
DQ0
VDDQ
DQ1
DQ2
VssQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VssQ
DQ7
VDD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
x16 x8 x4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15 DQ7
VssQ DQ14 NC
DQ13 DQ6
VDDQ DQ12 NC
DQ11 DQ5
VssQ DQ10 NC
DQ9 DQ4
VDDQ DQ8 NC
Vss
NC
DQMH DQM
CLK
CKE A12 A11 A9
A8
A7
A6
A5
A4
Vss
-
NC
NC
DQ3
NC
NC
NC
DQ2
NC
DQM
-
The # symbol indicates signal is active LOW. A dash (-) indicates x8 and x4 pin function is
same as x16 pin function.
9
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512Mb: x4, x8, x16 SDRAM
General Description
Table 3:
Pin Descriptions
Pin
Numbers
Symbols
Type
Description
38
CLK
Input
37
CKE
Input
19
CS#
Input
18, 17, 16
RAS#,
CAS#, WE#
x4, x8:
DQM
x16:
DQML,
DQMH
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE power-down and SELF REFRESH
operation (all banks idle), ACTIVE power-down (row active in any bank), or CLOCK
SUSPEND operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers, including CLK,
are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered.
Input/output mask: DQM is an input mask signal for write accesses and an output
enable signal for read accesses. Input data is masked when DQM is sampled HIGH
during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML
(Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0–DQ7,
and DQMH corresponds to DQ8–DQ15. DQML and DQMH are considered same
state when referenced as DQM.
Bank address inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE,
or PRECHARGE command is being applied.
Address inputs: A0–A12 are sampled during the ACTIVE command (row-address
A0–A12) and READ/WRITE command (column-address A0–A9, A11, A12 [x4]; A0–
A9, A11 [x8]; A0–A9 [x16]; with A10 defining auto precharge) to select one location
out of the memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether all banks are to be precharged (A10
[HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the opcode during a LOAD MODE REGISTER command.
Data input/output: Data bus for x16 (4, 7, 10, 13, 15, 42, 45, 48, and 51 are NCs for
x8; 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NCs for x4).
39
15, 39
Input
20, 21
BA0, BA1
Input
23–26, 29–
34, 22, 35,
36
A0–A12
Input
2, 4, 5, 7, 8, DQ0–DQ15
10, 11, 13,
42, 44, 45,
47, 48, 50,
51, 53
2, 5, 8, 11, DQ0–DQ7
44, 47, 50,
53
DQ0–DQ3
5, 11, 44,
50
40
NC
3, 9, 43, 49
VDDQ
6, 12, 46,
VSSQ
52
1, 14, 27
VDD
28, 41, 54
VSS
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512MbSDRAM.fm - Rev. L 10/07 EN
x16: I/O
x8: I/O
Data input/output: Data bus for x8 (2, 8, 47, and 53 are NCs for x4).
x4: I/O
Data input/output: Data bus for x4.
–
Supply
Supply
No connect: This pin should be left unconnected.
DQ power: Isolated DQ power to the die for improved noise immunity.
DQ ground: Isolated DQ ground to the die for improved noise immunity.
Supply
Supply
Power supply: +3.3V ±0.3V.
Ground.
10
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512Mb: x4, x8, x16 SDRAM
Functional Description
Functional Description
The 512Mb SDRAMs (32 Meg x 4 x 4 banks, 16 Meg x 8 x 4 banks, and 8 Meg x 16 x 4
banks) are quad-bank DRAMs that operate at 3.3V and include a synchronous interface
(all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s
134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each of the
x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by 8 bits. Each of
the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A12 select the row). The address bits (x4: A0–A9, A11, A12; x8: A0–A9,
A11; x16: A0–A9) registered coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. After power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
After the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
If desired, the two AUTO REFRESH commands can be issued after the LMR command.
The recommended power-up sequence for SDRAMs:
1. Simultaneously apply power to VDD and VDDQ.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTLcompatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
constraints specified for the clock pin.
4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT
or NOP.
5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least
through the end of this period, one or more COMMAND INHIBIT or NOP commands
must be applied.
6. Perform a PRECHARGE ALL command.
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512Mb: x4, x8, x16 SDRAM
Functional Description
7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands
are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LMR command, program the mode
register. The mode register is programmed via the MODE REGISTER SET command
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again
or the device loses power. Not programming the mode register upon initialization will
result in default settings which may not be desired. Outputs are guaranteed High-Z
after the LMR command is issued. Outputs should be High-Z already before the LMR
command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are
allowed.
At this point the DRAM is ready for any valid command.
Note:
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512MbSDRAM.fm - Rev. L 10/07 EN
If desired, more than two AUTO REFRESH commands can be issued in the sequence.
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
REFRESH + tRFC loops is achieved.
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512Mb: x4, x8, x16 SDRAM
Register Definition
Register Definition
Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of BL, a burst type, CL, an operating mode, and a write
burst mode, as shown in Figure 5 on page 14. The mode register is programmed via the
LOAD MODE REGISTER command and will retain the stored information until it is
programmed again or the device loses power.
Mode register bits M0–M2 specify BL, M3 specifies the type of burst (sequential or interleaved), M4–M6 specify CL, M7 and M8 specify the operating mode, M9 specifies the
write burst mode, and M10 and M11 are reserved for future use. Address A12 (M12) is
undefined but should be driven LOW during loading of the mode register.
The mode register must be loaded when all banks are idle, and the controller must wait
the specified time before initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with BL being programmable,
as shown in Figure 5 on page 14. BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4,
or 8 locations are available for both the sequential and the interleaved burst types, and a
full-page burst is available for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used because unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to BL is effectively
selected. All accesses for that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is uniquely selected by A1–
A9, A11, A12 (x4); A1–A9, A11 (x8); or A1–A9 (x16) when BL = 2; by A2–A9, A11, A12 (x4);
A2–A9, A11 (x8) or A2–A9 (x16) when the BL = 4; and by A3–A9, A11, A12 (x4); A3–A9, A11
(x8) or A3–A9 (x16) when the BL = 8. The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. Full-page bursts wrap within
the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed either to be sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by BL, the burst type and the
starting column address, as shown in Table 4 on page 15.
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512Mb: x4, x8, x16 SDRAM
Register Definition
Figure 5:
Mode Register Definition
A12 A11 A10
12
11
A9
9
10
Reserved1
A8
8
A5
5
CAS Latency
A4
A3
4
3
BT
A1
A2
1
2
Address Bus
A0
0
Mode Register (Mx)
Burst Length
Burst Length
Write Burst Mode
0
Programmed burst length
1
Single location access
M2 M1 M0
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard operation
–
–
–
All other states reserved
M6 M5 M4
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6
7
WB Op Mode
M9
Notes:
A6
A7
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
M3
Burst Type
0
1
1
3
0
Sequential
1
0
0
Reserved
1
Interleaved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
1. Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices.
14
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Register Definition
Table 4:
Burst Definition
Burst
Length
Starting Column
Address
2
–
–
A0
–
–
0
–
–
1
–
A1
A0
–
0
0
–
0
1
–
1
0
–
1
1
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
n = A0–A12/11/9
(location 0–y)
4
8
Full
page (y)
Notes:
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1,
Cn + 2
Cn + 3,
Cn + 4…,
…Cn - 1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
1. For full-page accesses: y = 4,096 (x4); y = 2,048 (x8); y = 1,024 (x16).
2. For BL = 2, A1–A9, A11, A12 (x4); A1–A9, A11 (x8); or A1–A9 (x16) select the block-of-two
burst; A0 selects the starting column within the block.
3. For BL = 4, A2–A9, A11, A12 (x4); A2–A9, A11 (x8); or A2–A9 (x16) select the block-of-four
burst; A0–A1 select the starting column within the block.
4. For BL = 8, A3–A9, A11, A12 (x4); A3–A9, A11 (x8); or A3–A9 (x16) select the block-of-eight
burst; A0–A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or
A0–A9 (x16) select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
7. For BL = 1, A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) select the unique column
to be accessed, and mode register bit M3 is ignored.
CAS Latency (CL)
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n and the latency is m clocks, the data will
be available by clock edge n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data
will be valid by clock edge n + m. For example, assuming that the clock cycle time is such
that all relevant access times are met, if a READ command is registered at T0 and the
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Register Definition
latency is programmed to two clocks, the DQs will start driving after T1 and the data will
be valid by T2, as shown in Figure 6. Table 5 indicates the operating frequencies at which
each CL setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Figure 6:
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
NOP
NOP
NOP
CLK
COMMAND
READ
tLZ
tOH
DOUT
DQ
tAC
CL = 3
Don’t Care
Undefined
Table 5:
CAS Latency
Allowable Operating
Frequency (MHz)
Speed
CL = 2
CL = 3
-7E
-75
≤ 133
≤ 100
≤ 143
≤ 133
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
WRITE Burst Mode
When M9 = 0, BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed burst length applies to READ bursts, but write accesses
are single-location (nonburst) accesses.
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Commands
Commands
Table 6 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear in the Operations
section, beginning on page 35; these tables provide current state/next state information.
Table 6:
Truth Table 1 – Commands and DQM Operation
Notes 1–2 apply to entire table; notes appear below
Name (Function)
CS#
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
RAS# CAS#
WE#
DQM
Address
DQs
Notes
H
L
L
L
L
X
H
L
H
H
X
H
H
L
L
X
H
H
H
L
X
X
X
L/H8
L/H8
X
X
Bank/row
Bank/col
Bank/col
X
X
X
X
Valid
3
4
4
L
L
L
H
L
L
H
H
L
L
L
H
X
X
X
X
Code
X
Active
X
X
5
6, 7
L
–
–
L
–
–
L
–
–
L
–
–
X
L
H
Op-code
–
–
X
Active
High-Z
4
8
8
CKE is HIGH for all commands shown except SELF REFRESH.
A0–A11 define the op-code written to the mode register, and A12 should be driven LOW.
A0–A12 provide row address, and BA0, BA1 determine which bank is made active.
A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) provide column address; A10 HIGH
enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
and BA0, BA1 are “Don’t Care.”
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay).
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
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Commands
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11 (A12 should be driven LOW). See “Mode
Register” on page 13. The LOAD MODE REGISTER command can only be issued when
all banks are idle, and a subsequent executable command cannot be issued until tMRD
is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A12 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9, A11,
A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) selects the starting column location. The value
on input A10 determines whether auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for subsequent accesses. Read data
appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a
given DQM signal was registered HIGH, the corresponding DQs will be High-Z two
clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9, A11,
A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) selects the starting column location. The value
on input A10 determines whether auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for subsequent accesses. Input data
appearing on the DQs is written to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM signal is registered LOW, the
corresponding data will be written to memory; if the DQM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
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Commands
Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst,
except in the full-page burst mode, where auto precharge does not apply. Auto precharge
is nonpersistent in that it is either enabled or disabled for each individual READ or
WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in the “Operations”
section on page 20.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page
bursts. The most recently registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated, as shown in the “Operations” section on
page 20. The BURST TERMINATE command does not precharge the row; the row will
remain open until a PRECHARGE command is issued.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is
nonpersistent, so it must be issued each time a refresh is required. All active banks must
be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum tRP has been met after the
PRECHARGE command as shown in the “Operations” section on page 20.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 512Mb SDRAM requires
8,192 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a
distributed AUTO REFRESH command every 7.81µs will meet the refresh requirement
and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands
can be issued in a burst at the minimum cycle rate (tRC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
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Operations
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. When CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for tXSR because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every
7.81µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 7).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 8 on page 21, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3 (the same procedure is used to convert other
specification limits from time units to clock cycles). A subsequent ACTIVE command to
a different row in the same bank can only be issued after the previous active row has
been “closed” (precharged). The minimum time interval between successive ACTIVE
commands to the same bank is defined by tRC.
Figure 7:
Activating a Specific Row In a Specific Bank
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A12
BA0, BA1
ROW
ADDRESS
BANK
ADDRESS
Don’t Care
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Operations
Figure 8:
Example Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK ≤ 3
T0
T1
T2
NOP
NOP
T4
T3
CLK
COMMAND
ACTIVE
READ or
WRITE
tRCD
Don’t Care
READs
READ bursts are initiated with a READ command, as shown in Figure 9.
The starting column and bank addresses are provided with the READ command, and
auto precharge either is enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following CL after the READ command. Each subsequent data-out element
will be valid by the next positive clock edge. Figure 10 on page 22 shows general timing
for each possible CL setting.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
Figure 9:
READ Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9, A11, A12: x4
A0–A9, A11: x8
A0–A9: x16
COLUMN
ADDRESS
A12: x8
A11, A12: x16
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0, BA1
BANK
ADDRESS
Don't Care
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Operations
Figure 10:
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 3
Don’t Care
Undefined
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A full-page burst will continue until terminated (at the end of the page, it
will wrap to the start address and continue). Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may
be immediately followed by data from a READ command.
In either case, a continuous flow of data can be maintained. The first data element from
the new burst either follows the last element of a completed burst or the last desired data
element of a longer burst that is being truncated. The new READ command should be
issued x cycles before the clock edge at which the last desired data element is valid,
where x = CL - 1. This is shown in Figure 10 for CL = 2 and CL = 3; data element n + 3 is
either the last of a burst of four or the last desired of a longer burst.
The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n
rule associated with a prefetch architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-speed random read accesses can
be performed to the same bank, as shown in Figure 12 on page 24, or each subsequent
READ may be performed to a different bank.
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Operations
Figure 11:
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
x = 1 cycle
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
READ
NOP
NOP
NOP
x = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CL = 3
Transitioning Data
Note:
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Don’t Care
Each READ command may be to any bank. DQM is LOW.
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Operations
Figure 12:
Random READ Accesses
T0
T1
T2
T3
T4
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
T5
CLK
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CL = 2
T0
T1
T2
T3
T4
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
T5
T6
CLK
NOP
DOUT
n
DQ
NOP
DOUT
a
DOUT
x
NOP
DOUT
m
CL = 3
Transitioning Data
Note:
Don’t Care
Each READ command may be to any bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 13 on page 25 and
Figure 14 on page 25. The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress dataout from the READ. After the WRITE command is registered, the DQs will go High-Z (or
remain High-Z), regardless of the state of the DQM signal, provided the DQM was active
on the clock just prior to the WRITE command that truncated the READ command. If
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 in Figure 14 on page 25, then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
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Operations
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 14 shows the case where the additional NOP is
needed.
Figure 13:
READ-to-WRITE
T0
T1
T2
T3
T4
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
WRITE
BANK,
COL b
tCK
tHZ
DQ
DOUT n
DIN b
tDS
Transitioning Data
Note:
Figure 14:
Don’t Care
A CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank. If a burst of 1 is used, then DQM is not required.
READ-to-WRITE with Extra Clock Cycle
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
WRITE
BANK,
COL b
tHZ
DQ
DOUT n
DIN b
tDS
Transitioning Data
Note:
Don’t Care
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a fullpage burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 15 on page 26 for
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512Mb: x4, x8, x16 SDRAM
Operations
each possible CL; data element n + 3 is either the last of a burst of four or the last desired
of a longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 16 on page 27 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
Figure 15:
READ-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
BANK a,
ROW
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CAS Latency = 3
TRANSITIONING DATA
DON’T CARE
NOTE: DQM is LOW.
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Operations
Figure 16:
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
x = 1 cycle
DOUT
n+1
DOUT
n
DQ
DOUT
n+2
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
x = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 3
Transitioning Data
Note:
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512MbSDRAM.fm - Rev. L 10/07 EN
Don’t Care
DQM is LOW.
27
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512Mb: x4, x8, x16 SDRAM
Operations
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 17.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z and any additional input
data will be ignored (see Figure 18 on page 29). A full-page burst will continue until
terminated (at the end of the page, it will wrap to the start address and continue). Data
for any WRITE burst may be truncated with a subsequent WRITE command, and data
for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 19 on page 29. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 20 on page 30, or each subsequent WRITE may be
performed to a different bank.
Figure 17:
WRITE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9, A11, A12: x4
A0–A9, A11: x8
A0–A9: x16
COLUMN
ADDRESS
A12: x8
A11, A12: x16
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BANK
ADDRESS
BA0, BA1
Don’t Care
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Operations
Figure 18:
WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
DQ
DIN
n+1
DIN
n
Transitioning Data
Note:
Don’t Care
BL = 2. DQM is LOW.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
After the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 21 on page 30. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Figure 19:
WRITE-to-WRITE
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
Transitioning Data
Note:
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512MbSDRAM.fm - Rev. L 10/07 EN
DIN
b
Don’t Care
DQM is LOW. Each WRITE command may be to any bank.
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Operations
Figure 20:
Random WRITE Cycles
T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DIN
n
DIN
a
DIN
x
DIN
m
CLK
DQ
Transitioning Data
Note:
Figure 21:
Don’t Care
Each WRITE command may be to any bank. DQM is LOW.
WRITE-to-READ
T0
T1
T2
COMMAND
WRITE
NOP
READ
ADDRESS
BANK,
COL n
T3
T4
T5
NOP
NOP
NOP
DOUT
b
DOUT
b+1
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
Transitioning Data
Note:
Don’t Care
The WRITE or READ commands may be to any bank. DQM is LOW.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to
the same bank. The PRECHARGE command should be issued tWR after the clock edge at
which the last desired input data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regardless of frequency. In addition, when
truncating a WRITE burst, the DQM signal must be used to mask input data for the clock
edge prior to, and the clock edge coincident with, the PRECHARGE command. An
example is shown in Figure 22 on page 31. Data n + 1 is either the last of a burst of two or
the last desired of a longer burst. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met. The precharge can be
issued coincident with the first coincident second clock (Figure 22 on page 31). In the
case of a fixed-length burst being executed to completion, a PRECHARGE command
issued at the optimum time (as described above) provides the same operation that
would result from the same fixed-length burst with auto precharge. The disadvantage of
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512Mb: x4, x8, x16 SDRAM
Operations
the PRECHARGE command is that it requires that the command and address buses be
available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 23 on page 32, where data n is
the last desired data element of a longer burst.
Figure 22:
WRITE-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
NOP
ACTIVE
NOP
CLK
tWR @ tCLK > 15ns
DQM
t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
tWR = tCLK < 15ns
DQM
t RP
COMMAND
ADDRESS
WRITE
NOP
NOP
PRECHARGE
NOP
BANK
(a or all)
BANK a,
COL n
NOP
ACTIVE
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
Transitioning Data
Note:
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512MbSDRAM.fm - Rev. L 10/07 EN
Don’t Care
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
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Operations
Figure 23:
Terminating a WRITE Burst
T0
T1
T2
COMMAND
WRITE
BURST
TERMINATE
ADDRESS
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
CLK
DQ
Transitioning Data
Note:
NEXT
COMMAND
Don’t Care
DQMs are LOW.
PRECHARGE
The PRECHARGE command shown in Figure 24 is used to deactivate the open row in a
particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued.
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Figure 24:
PRECHARGE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9, A11, A12
All Banks
A10
Bank Selected
BA0, BA1
BANK
ADDRESS
Don’t Care
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512Mb: x4, x8, x16 SDRAM
Operations
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (64ms) since no refresh operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 25.
Figure 25:
Power-Down
((
))
((
))
CLK
tCKS
CKE
>tCKS
((
))
COMMAND
((
))
((
))
NOP
NOP
ACTIVE
tRCD
All banks idle
Input buffers gated off
Enter power-down mode.
Exit power-down mode.
tRAS
tRC
Don’t Care
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended (see
examples in Figures 26 and 27 on page 34).
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
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Operations
Figure 26:
CLOCK SUSPEND During WRITE Burst
T0
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN
n+1
DIN
n+2
CLK
CKE
INTERNAL
CLOCK
COMMAND
BANK,
COL n
ADDRESS
DIN
n
DIN
Transitioning Data
Note:
Figure 27:
Don’t Care
BL = 4 or greater. DM is LOW.
CLOCK SUSPEND During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
ADDRESS
BANK,
COL n
DQ
NOP
NOP
NOP
NOP
DOUT
n+1
DOUT
n
Transitioning Data
Note:
DOUT
n+2
NOP
DOUT
n+3
Don’t Care
CL = 2, BL = 4 or greater. DQM is LOW.
Burst READ/Single WRITE
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
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Operations
Concurrent Auto Precharge
An access command to (READ or WRITE) another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
READ with Auto Precharge
• Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CL later. The PRECHARGE to bank n will begin when the
READ to bank m is registered (see Figure 28).
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered (see Figure 29 on page 36).
Figure 28:
READ with Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
READ - AP
BANK n
Page Active
READ - AP
BANK m
NOP
READ with Burst of 4
NOP
NOP
NOP
Idle
Interrupt Burst, Precharge
tRP - BANK m
t RP - BANK n
BANK m
ADDRESS
Page Active
BANK n,
COL a
NOP
Precharge
READ with Burst of 4
BANK m,
COL d
DOUT
a
DQ
DOUT
a+1
DOUT
d
DOUT
d+1
CL = 3 (BANK n)
CL = 3 (BANK m)
Transitioning Data
Note:
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512MbSDRAM.fm - Rev. L 10/07 EN
Don’t Care
DQM is LOW.
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Operations
Figure 29:
READ with Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
WRITE - AP
BANK m
READ with Burst of 4
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK n,
COL a
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
CL = 3 (BANK n)
Notes:
DIN
d+1
DIN
d+2
Transitioning Data
DIN
d+3
Don’t Care
1. DQM is HIGH at T2 to prevent DOUT - a + 1 from contending with DIN - d at T4.
WRITE with Auto Precharge
• Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The
PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ
to bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (see Figure 30).
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (see Figure 31 on page 37).
Figure 30:
WRITE with Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
BANK m
ADDRESS
NOP
WRITE - AP
BANK n
Page Active
READ - AP
BANK m
NOP
WRITE with Burst of 4
Page Active
DIN
a
NOP
NOP
Interrupt Burst, Write-Back
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
DQ
NOP
BANK m,
COL d
DIN
a+1
DOUT
d
DOUT
d+1
CL = 3 (BANK m)
Transitioning Data
Note:
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512MbSDRAM.fm - Rev. L 10/07 EN
Don’t Care
DQM is LOW.
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Operations
Figure 31:
WRITE with Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Write-Back
Precharge
tRP - BANK n
tWR - BANK n
BANK m
ADDRESS
Page Active
DQ
DIN
a
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK n,
COL a
BANK m,
COL d
DIN
a+1
DIN
a+2
DIN
d
DIN
d+1
DIN
d+2
Transitioning Data
Note:
Table 7:
NOP
DIN
d+3
Don’t Care
DQM is LOW.
Truth Table 2 – CKE
Notes 1–4 apply to entire table; notes appear below
CKEn - 1
CKEn
Current State
COMMANDn
ACTIONn
Notes
L
L
L
H
L
Maintain power-down
Maintain self refresh
Maintain clock suspend
Exit power-down
Exit self refresh
Exit clock suspend
Power-down entry
Self refresh entry
Clock suspend entry
H
H
X
X
X
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
AUTO REFRESH
WRITE or NOP
See Table 8 on page 38
5
6
7
H
Power-down
Self refresh
Clock suspend
Power-down
Self refresh
Clock suspend
All banks idle
All Banks idle
Reading or writing
Notes:
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512MbSDRAM.fm - Rev. L 10/07 EN
1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during tXSR
period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
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Operations
Table 8:
Truth Table 3 – Current State Bank n, Command to Bank n
Notes: 1–6 apply to entire table; notes appear below and on next page
Current
State
Any
Idle
Row active
Read
(auto
precharge
disabled)
Write
(auto
precharge
disabled)
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS# CAS#
X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
Notes:
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
WE#
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
Command (Action)
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
Notes
7
7
11
10
10
8
10
10
8
9
10
10
8
9
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 7 on page 37) and
after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, that is, the current state is for a specific
bank and the commands shown are those allowed to be issued to that bank when in that
state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled and has
not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 8 and according to Table 9 on page 40.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP
is met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. After tRCD is met, the bank will be in the row active state.
Read with auto Starts with registration of a READ command with auto precharge
precharge enabled: enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
Write w/auto Starts with registration of a WRITE command with auto precharge
precharge enabled: enabled and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
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Operations
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
t
RC is met. After tRC is met, the SDRAM will be in the all banks idle
state.
Accessing mode Starts with registration of a LOAD MODE REGISTER command and ends
register: when tMRD has been met. After tMRD is met, the SDRAM will be in the
all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. After tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
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Operations
Table 9:
Truth Table 4 – Current State Bank n, Command to Bank m
Notes 1–6 apply to entire table; notes appear below and on next page
Current State
CS#
RAS#
CAS#
WE#
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Idle
Row
activating,
active, or
precharging
Read
(auto
precharge
disabled)
Write
(auto
precharge
disabled)
Read
(with auto
precharge)
Write
(with auto
precharge)
Notes:
Command (Action)
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7, 10
7, 11
9
7, 12
7, 13
9
7, 8, 14
7, 8, 15
9
7, 8, 16
7, 8, 17
9
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 7 on page 37) and
after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; that is, the current state
is for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Read with auto Starts with registration of a READ command with auto precharge
precharge enabled: enabled, and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
Write with auto Starts with registration of a WRITE command with auto precharge
precharge enabled: enabled, and ends when tRP has been met. After tRP is met, the bank
will be in the idle state.
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
when all banks are idle.
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Operations
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 11 on
page 23).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 13
and Figure 14 on page 25). DQM should be used one clock prior to the WRITE command to
prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 21
on page 30), with the data-out appearing CL later. The last valid WRITE to bank n will be
data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered
(Figure 19 on page 29). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n
will begin when the READ to bank m is registered (Figure 28 on page 35).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE
to bank n will begin when the WRITE to bank m is registered (Figure 29 on page 36).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the READ to bank m is registered. The last valid WRITE to bank n will be datain registered one clock prior to the READ to bank m (Figure 30 on page 36).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE
to bank m (Figure 31 on page 37).
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Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 10:
Absolute Maximum Ratings
Parameter
Symbol
VDD supply voltage relative to VSS
VDDQ supply voltage relative to VSS
Voltage on any pin relative to VSS
SDRAM device temperatures
TA
Power dissipation
Note:
VDD
VDDQ
VIN, VOUT, NC
Commercial
Industrial
Storage (plastic)
–
Min
Max
Units
–1.0
–1.0
–1.0
0
–40
–55
–
+4.6
+4.6
+4.6
+70
+85
+155
+1
V
V
V
°C
°C
°C
W
Notes
1
1
1
For further information, refer to technical note TN-00-08: Thermal Applications, available
on Micron’s Web site.
Temperature and Thermal Impedance
It is imperative that the SDRAM device’s temperature specifications, shown in Table 11
on page 43, be maintained to ensure the junction temperature is in the proper operating
range to meet data sheet specifications. An important step in maintaining the proper
junction temperature is using the device’s thermal impedances correctly. The thermal
impedances are listed in Table 12 on page 43 for the applicable die revision and packages being made available. These thermal impedance values vary according to the
density, package, and particular design used for each device.
Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications” prior to using the thermal impedances
listed in Table 12 on page 43. To ensure the compatibility of current and future designs,
contact Micron Applications Engineering to confirm thermal impedance values. The
SDRAM device’s safe junction temperature range can be maintained when the TC specification is not exceeded. In applications where the device’s ambient temperature is too
high, use of forced air and/or heat sinks may be required to satisfy the case temperature
specifications.
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Electrical Specifications
Table 11:
Temperature Limits
Parameter
Symbol
Table 12:
Max
0
–40
80
90
0
–40
85
95
0
–40
–
70
85
260
TC
Operating case temperature:
Commercial
Industrial
Junction temperature:
Commercial
Industrial
Ambient temperature:
Commercial
Industrial
Peak reflow temperature
Notes:
Min
TJ
TA
TPEAK
Units
Notes
°C
1, 2, 3, 4
°C
3
°C
3, 5
°C
1. MAX operating case temperature, TC, is measured in the center of the package on the top
side of the device, as shown on page 47.
2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
3. Both temperature specifications must be satisfied.
4. The case temperature should be measured by gluing a thermocouple to the top center of
the component. This should be done with a 1mm bead of conductive epoxy, as defined by
the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is
touching the case.
5. Operating ambient temperature surrounding the package.
Summary of Thermal Impedance
θJA
θJMA
θJMA
θJB
θJC
Die Size
(mm2)
Number of
Leads
Test
Board
(°C/W)
0m/s
(°C/W)
1m/s
(°C/W)
2m/s
(°C/W)
(°C/W)
Package
94
TSOP
54
2-layer
4-layer
62.6
39.2
48.4
32.3
44.2
30.6
19.2
19.3
6.7
Figure 32:
Example Temperature Test Point Location, 54-Pin TSOP: Top View
22.22mm
11.11mm
Test point
10.16mm
5.08mm
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Electrical Specifications
Table 13:
DC Electrical Characteristics And Operating Conditions
Notes 1, 5, and 6 apply to entire table; notes appear on page 47; VDD, VDDQ = +3.3V ±0.3V
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Input leakage current: Any input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
Output leakage current: DQs are disabled;
0V ≤ VOUT ≤ VDDQ
Output levels:
Output high voltage (IOUT = –4mA)
Output low voltage (IOUT = 4mA)
Table 14:
Symbol
Min
Max
Units
Notes
VDD, VDDQ
VIH
VIL
II
3
2
–0.3
–5
3.6
VDD + 0.3
0.8
5
V
V
V
µA
22
22
IOZ
–5
5
µA
VOH
2.4
–
V
26
VOL
–
0.4
V
26
IDD Specifications and Conditions
Notes 1, 5, 6, 11, and 13 apply to entire table; notes appear on page 47; VDD, VDDQ = +3.3V ±0.3V
Max
Parameter/Condition
Operating current: Active mode;
Burst = 2; READ or WRITE; tRC = tRC (MIN)
Standby current: power-down mode;
CKE = LOW; All banks idle
Standby current: Active mode; CS# = HIGH;
CKE = HIGH; All banks active after tRCD met;
No accesses in progress
Operating current: Burst mode; Page burst;
READ or WRITE; All banks active
tRFC = tRFC (MIN)
Auto refresh current:
tRFC = 7.81µs
CS# = HIGH; CKE = HIGH
Self refresh current: CKE ≤ 0.2V
Standard
Low power (L)
Table 15:
Symbol
-7E
-75
Units
Notes
IDD1
120
110
mA
IDD2
3.5
3.5
mA
3, 18, 19,
29
29
IDD3
45
45
mA
3, 12, 19,
29
IDD4
125
115
mA
IDD5
IDD6
IDD7
IDD7
255
6
6
3
255
6
6
3
mA
mA
mA
mA
3, 18, 19,
29
3, 18, 19,
29, 30
Symbol
Min
Max
Units
CI1
CI2
CIO
2.5
2.5
4.0
3.5
3.8
6.0
pF
pF
pF
•
Capacitance
Note 2 applies to entire table; notes appear on page 47
Parameter
Input capacitance: CLK
Input capacitance: All other input-only pins
Input/output capacitance: DQs
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Electrical Specifications
Table 16:
Electrical Characteristics and Recommended AC Operating Conditions
Notes 5, 6, 7, 8, 9, and 11 apply to entire table; notes appear on page 47
AC Characteristics
-7E
Parameter
Access time from CLK (positive edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
Symbol
CL = 3
CL = 2
CL = 3
CL = 2
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
CL = 3
Data-out High-Z time
CL = 2
Data-out Low-Z time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE command period
ACTIVE-to-READ or WRITE delay
Refresh period (8,192 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time
Exit SELF REFRESH-to-ACTIVE command
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t
AC(3)
AC(2)
t
AH
t
AS
t
CH
t
CL
tCK(3)
tCK(2)
t
CKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ(3)
tHZ(2)
tLZ
tOH
tOHN
tRAS
tRC
tRCD
tREF
tRFC
tRP
tRRD
tT
tWR
t
tXSR
45
-75
Min
Max
Min
Max
Units
Notes
–
–
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
1.5
0.8
1.5
–
–
1
2.7
1.8
37
60
15
–
66
15
14
0.3
1 CLK +
7ns
14
67
5.4
5.4
–
–
–
–
–
–
–
–
–
–
–
–
5.4
5.4
–
–
–
120,000
–
–
64
–
–
–
1.2
–
–
–
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
0.8
1.5
–
–
1
2.7
1.8
44
66
20
–
66
20
15
0.3
1 CLK +
7.5ns
15
75
5.4
6
–
–
–
–
–
–
–
–
–
–
–
–
5.4
6
–
–
–
120,000
–
–
64
–
–
–
1.2
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
–
27
–
–
ns
ns
–
–
23
23
10
10
28
7
24
14, 25
20
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Electrical Specifications
Table 17:
AC Functional Characteristics
Notes 5, 6, 7, 8, 9, and 11 apply to entire table; notes appear below
Parameter
Symbol
READ/WRITE command-to-READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
CL = 3
Data-out to High-Z from PRECHARGE command
CL = 2
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46
t
CCD
CKED
t
PED
t
DQD
tDQM
t
DQZ
t
DWD
t
DAL
t
DPL
t
BDL
t
CDL
tRDL
tMRD
tROH(3)
tROH(2)
t
-7E
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
-75
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
Units
t
CK
CK
t
CK
t
CK
tCK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
tCK
tCK
tCK
tCK
t
Notes
17
14
14
17
17
17
17
15, 21
16, 21
17
17
16, 21
26
17
17
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Notes
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test
biased at 1.4V.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (0°C ≤ TA ≤ 70°C for commercial; –40°C ≤ TA
≤ 85°C for industrial) is ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. Refer
to Micron technical note TN-48-09.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease in a proportional amount by the amount the
frequency is altered for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -75 and -7E.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Notes
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one-third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤ 3ns for all inputs. VIH overshoot for pin A12 is limited to VDDQ + 1V for
a pulse width ≤ 3ns, and the pulse width cannot be greater than one-third of the cycle
rate.
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after
the first clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For -75, CL = 3, tCK = 7.5ns; for -7E, CL = 2, tCK = 7.5ns.
30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Timing Diagrams
Figure 33:
Initialize and Load Mode Register
T0
CK
((
))
CKE
((
))
((
))
COMMAND
((
))
((
))
tCK
T1
tCKH
tCKS
Tn + 1
((
))
((
))
tCH
tCMS tCMH
((
))
NOP
NOP
((
))
AUTO
REFRESH
AUTO
REFRESH
((
))
NOP
NOP
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0–A9,
A11, A12
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0, BA1
DQ
ALL BANKS
SINGLE BANK
((
))
((
))
ALL
BANKS
High-Z
((
))
T = 100µs
MIN
Power-up:
VDD and
CLK stable
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Tp + 3
LOAD MODE
REGISTER
tAS
NOP
ACTIVE
tAH 5
ROW
CODE
tAS
tAH
ROW
CODE
BANK
((
))
tRP
Notes:
Tp + 2
((
))
((
))
((
))
DQM/
DQML, DQMH
Tp + 1
tCMS tCMH
((
))
PRECHARGE
((
))
NOP
((
))
((
))
((
))
((
))
((
))
tCMS tCMH
To + 1
tCL
((
))
((
))
Precharge
all banks
1.
2.
3.
4.
5.
tRFC
tRFC
AUTO REFRESH
AUTO REFRESH
tMRD
Program mode register 2, 3, 4
Don’t Care
If CS is HIGH at clock high time, all commands applied are NOP.
The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
JEDEC and PC100 specify three clocks.
Outputs are guaranteed High-Z after command is issued.
A12 should be a LOW at Tp + 1.
49
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512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 34:
Power-Down Mode
T0
T1
T2
Tn + 1
Tn + 2
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DQM/
DQML, DQMU
((
))
((
))
((
))
((
))
A0–A9,
A11, A12
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
BANK
((
))
((
))
tCK
CLK
tCL
tCKS
tCH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
PRECHARGE
NOP
NOP
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
tCKS
NOP
ACTIVE
tAH
BANK(S)
High-Z
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
Don’t Care
Note:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Violating refresh requirements during power-down may result in a loss of data.
50
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 35:
Clock Suspend Mode
T0
T1
T2
tCK
CLK
T3
T4
T5
T6
T7
T8
NOP
WRITE
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
tCMS tCMH
DQM/
DQML, DQMU
A0–A9,
A11, A12
tAS
tAH
COLUMN m
tAS
2
COLUMN e 2
tAH
A10
tAS
BA0, BA1
tAH
BANK
BANK
tAC
tOH
tAC
DOUT m
DQ
tHZ
DOUT m + 1
tDS
tDH
Din e
Din + 1
tLZ
Don’t Care
Undefined
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
51
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 36:
Auto-Refresh Mode
T0
CLK
T1
tCK
T2
((
))
((
))
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
NOP
AUTO
REFRESH
NOP
A0–A9,
A11, A12
ALL BANKS
A10
SINGLE BANK
tAS
DQ
((
))
( ( NOP
))
((
))
((
))
DQM /
DQML, DQMH
BA0, BA1
((
))
((
))
((
))
CKE
COMMAND
Tn + 1
tCL
((
))
AUTO
REFRESH
NOP
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
tAH
BANK(S)
High-Z
t RP
((
))
((
))
((
))
((
))
((
))
((
))
tRFC
Precharge all
active banks
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
To + 1
BANK
tRFC
Don’t Care
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 37:
Self Refresh Mode
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
CKE
tCKS
tCKH
tCMS
tCMH
COMMAND
PRECHARGE
((
))
((
))
Tn + 1
≥ tRAS(MIN)1
((
))
((
))
((
))
NOP
AUTO
REFRESH
((
))
((
))
((
) ) or COMMAND
NOP ( (
((
))
((
))
A0–A9,
A11,A12
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ALL BANKS
A10
SINGLE BANK
DQ
High-Z
((
))
((
))
tRP
Precharge all
active banks
tXSR2
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
CLK stable prior to exiting
self refresh mode
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
AUTO
REFRESH
tAH
BANK(S)
Notes:
INHIBIT
))
((
))
((
))
BA0, BA1
To + 2
((
))
DQM/
DQML, DQMU
tAS
To + 1
Don’t Care
1. No maximum time limit for self refresh; tRAS (MIN) applies to non-self refresh mode.
2. tXSR requires minimum of two clocks regardless of frequency or timing.
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 38:
READ – Without Auto Precharge
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
PRECHARGE
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAS
COLUMN m 2
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
SINGLE BANK
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
DOUT m
tAC
tOH
DOUT m + 1
BANK
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tLZ
tRCD
tHZ
tRP
CAS Latency
tRAS
tRC
Don’t Care
Undefined
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
54
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 39:
READ – With Auto Precharge
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAS
A10
COLUMN m 2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DOUT m
DQ
t
tAC
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
tLZ
tRCD
tOH
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
Don’t Care
Undefined
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 4, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
55
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 40:
Single READ – Without Auto Precharge
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQM/
DQML, DQMH
tAS
A0–A9,
A11, A12
tAS
COLUMN m2
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANKS
BANK
BANK(S)
BANK
tOH
tAC
DOUT m
DQ
tLZ
tRCD
tHZ
tRP
CAS Latency
tRAS
tRC
Don’t Care
Undefined
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
56
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 41:
Single READ – With Auto Precharge
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
T6
T7
T8
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
NOP3
NOP3
READ
tCMS
NOP
NOP
ACTIVE
NOP
tCMH
DQM/
DQML, DQMH
tAS
A0–A9, A12
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
BANK
tAC
t OH
DOUT m
DQ
tRCD
CAS Latency
tHZ
tRP
tRAS
tRC
Don’t Care
Undefined
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 1, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
3. READ command is not allowed else tRAS would be violated.
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 42:
Alternating Bank Read Accesses
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAS
A10
COLUMN m 2
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
BANK 3
BANK 3
tAC
tOH
tAC
DOUT m
DQ
tAC
tOH
DOUT m + 1
BANK 0
tAC
tOH
DOUT m + 2
tAC
tOH
DOUT m + 3
tAC
tOH
DOUT b
tLZ
tRCD - BANK 0
tRP - BANK 0
CAS Latency - BANK 0
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 3
tRRD
CAS Latency - BANK 3
Don’t Care
Undefined
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 4, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
58
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 43:
READ – Full-Page Burst
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
((
))
((
))
tCK
tCH
tCKS
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAH
tAH
NOP
BURST TERM
NOP
NOP
((
))
((
))
ROW
tAS
((
))
((
))
((
))
((
))
COLUMN m 2
ROW
tAS
BA0, BA1
Tn + 4
((
))
((
))
DQM/
DQML, DQMH
A10
Tn + 3
((
))
((
))
tCMS
A0–A9,
A11, A12
Tn + 2
tCKH
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tAC
tAC
tOH
DOUT m
DQ
tLZ
tRCD
CAS Latency
tAC
tAC ( (
tOH ) )
tOH
DOUT m+1
DOUT
((
))
m+2
((
))
tAC
tAC
tOH
tOH
tOH
DOUT m-1
Dout m
DOUT m+1
1,024 (x16) locations within same row
2,048 (x8) locations within same row
4,096 (x4) locations within same row
tHZ
Full page completed
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Don’t Care
Undefined
1. For this example, CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
3. Page left open; no tRP.
59
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 44:
READ DQM Operation
T0
T1
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
tCL
tCH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
tOH
DQ
tAC
DOUT m
tLZ
tRCD
tHZ
tAC
tOH
DOUT m + 2
tLZ
tOH
DOUT m + 3
tHZ
CAS Latency
Don’t Care
Undefined
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 4, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
60
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 45:
WRITE – Without Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
NOP
NOP
NOP
NOP
T7
T8
T9
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
ACTIVE
tCMS tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
ROW
tAH
ALL BANKs
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 3
tRCD
tRAS
BANK
tRP
tRC
Don’t Care
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
61
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 46:
WRITE – With Auto Precharge
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM/
DQML, DQMH
tAS
A0–A9,
A11, A12
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
tDS
tDH
DIN m
DQ
BANK
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tRAS
tDS
tDH
DIN m + 3
tWR
tRP
tRC
Don’t Care
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 4.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
62
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©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 47:
Single WRITE – Without Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
NOP
NOP
NOP
NOP
T7
T8
T9
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
ACTIVE
tCMS tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
ROW
tAH
ALL BANKs
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 3
tRCD
tRAS
BANK
tRP
tRC
Don’t Care
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
4. PRECHARGE command not allowed else tRAS would be violated.
63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 48:
Single WRITE with Auto Precharge
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
tCL
T2
T3
T4
T5
T6
T7
NOP4
WRITE
NOP
NOP
NOP
T8
T9
tCH
CKE
COMMAND
NOP4
ACTIVE
NOP4
tCMS
ACTIVE
NOP
tCMH
DQM/
DQML, DQMH
tAS
A0–A9,
A11, A12
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
ROW
tAS
BA0, BA1
COLUMN m3
ROW
tAS
A10
tAH
tAH
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD3
tRAS
tWR2
tRP
tRC
Don’t Care
Undefined
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
4. WRITE command not allowed else tRAS would be violated.
64
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 49:
Alternating Bank WRITE Accesses
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAS
A10
COLUMN m 3
tAH
COLUMN b 3
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
tDS
tDH
DIN m
DQ
BANK 1
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
BANK 1
tDS
tDH
DIN m + 3
tDS
tDH
DIN b
tWR - BANK 0
tRCD - BANK 0
BANK 0
tDS
tDH
DIN b + 1
tDS
tDH
DIN b + 2
tDS
tDH
DIN b + 3
tRP - BANK 0
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 1
tRRD
tWR - BANK 1
Don’t Care
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 4.
2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns
with PRECHARGE.
3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
65
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 50:
WRITE – Full-Page Burst
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
COMMAND
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
((
))
((
))
NOP
tCMS tCMH
tAS
A10
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m1
tAH
((
))
((
))
ROW
tAS
BA0, BA1
tAH
ROW
tAS
Tn + 3
((
))
((
))
DQM/
DQML, DQMH
A0–A9,
A11, A12
Tn + 2
((
))
((
))
CKE
tCMS
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tRCD
tDS
tDH
DIN m + 2
tDS
tDH
DIN m +
((
))
3( (
))
tDS
tDH
DIN m - 1
1,024 (x16) locations within same row
2,048 (x8) locations within same row
4,096 (x4) locations within same row
Full-page burst does
not self-terminate.
Can use BURST TERMINATE
command to stop.2, 3
Full page completed
Don’t Care
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1.
2.
3.
x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
must be satisfied prior to PRECHARGE command.
Page left open; no tRP.
tWR
66
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 51:
WRITE – DQM Operation
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM/
DQML, DQMU
tAS
A0–A9,
A11, A12
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
tAH
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DON’T CARE
Notes:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
1. For this example, BL = 4.
2. x16: A11 and A12 = “Don’t Care;” x8: A12 = “Don’t Care.”
67
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Package Dimensions
Package Dimensions
Figure 52:
54-Pin Plastic TSOP (400 mil)
22.22 ±0.08
SEE DETAIL A
0.71
0.80 TYP
0.375 ±0.075
11.76 ±0.20
10.16 ±0.08
0.15 +0.03
–0.02
PIN #1 ID
GAGE PLANE
0.25
0.10
0.10 +0.10
–0.05
1.2 MAX
LEAD FINISH: TIN/LEAD PLATE
PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC
PACKAGE WIDTH AND LENGTH DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.25 PER SIDE.
Notes:
0.50 ±0.10
0.80
TYP
DETAIL A
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
set forth herein. Although considered final, these specifications are subject to change, as further product development and
data characterization sometimes occur.
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
68
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.