V827332N04S 2.5 VOLT 32M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE MOSEL VITELIC PRELIMINARY Features Description ■ 184 Pin Registered 33,554,432 x 72 bit Organization DDR SDRAM Modules ■ Utilizes High Performance 32M x 4 DDR SDRAM in TSOPII-66 Packages ■ Single +2.5V (± 0.2V) Power Supply ■ Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) ■ Auto Refresh (CBR) and Self Refresh ■ All Inputs, Outputs are SSTL-2 Compatible ■ 4096 Refresh Cycles every 64 ms ■ Serial Presence Detect (SPD) ■ DDR SDRAM Performance The V827332N04S memory module is organized 33,554,432 x 72 bits in a 184 pin memory module. The 32M x 72 memory module uses 18 MoselVitelic 32M x 4 DDR SDRAM. The x72 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. Component Used tCK tAC Clock Frequency (max.) Clock Access Time CAS Latency = 2.5 -7 -75 -8 Units 143 133 125 MHz (PC266A) (PC266B) (PC200) 7 7.5 8 ns Module Speed A1 PC1600 (100MHz @ CL2) B0 PC2100B (133MHz @ CL2.5) B1 PC2100A (133MHz @ CL2) Standard Module Low Profile Module V827332N04S Rev. 1.1 May 2002 1 V827332N04S MOSEL VITELIC Part Number Information V 8 2 73 32 N 0 4 S X T (L) - XX SPEED A1 (100MHZ@CL2) B0 ([email protected]) B1 (133MHZ@CL2) MOSEL VITELIC MANUFACTURED DDRSDRAM Low Profile 2.5V COMPONENT PACKAGE, T = TSOP WIDTH DEPTH COMPONENT REV LEVEL 184 PIN Registered DIMM X4 COMPONENT STTL REFRESH RATE 4K V827332N04S Rev. 1.1 May 2002 2 4 BANKS V827332N04S MOSEL VITELIC Block Diagram VSS RS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ8 DQ9 DQ10 DQ11 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ16 DQ17 DQ18 DQ19 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ32 DQ33 DQ34 DQ35 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ40 DQ41 DQ42 DQ43 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ48 DQ49 DQ50 DQ51 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ56 DQ57 DQ58 DQ59 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQ4 DQ5 DQ6 DQ7 D0 DQS1 CS DM DQS2 DM DQS3 DM DQS4 DM DQ36 DQ37 DQ38 DQ39 CS DM DQ44 DQ45 DQ46 DQ47 CS DM D6 CS DM BA0-BAN A0-A13 RAS CAS CKE0 WE PCK PCK V827332N04S Rev. 1.1 May 2002 DQS16 (DM7) DQ60 DQ61 DQ62 DQ63 D7 DQS8 R E G I S T E R DQS15 (DM6) DQ52 DQ53 DQ54 DQ55 DQS7 S0 DQS14 (DM5) D5 DQS6 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS13 (DM4) D4 DQS5 CB0 CB1 CB2 CB3 DQS12 (DM3) DQ28 DQ29 DQ30 DQ31 D3 CS DQS11 (DM2) DQ20 DQ21 DQ22 DQ23 D2 CS DQS10 (DM1) DQ12 DQ13 DQ14 DQ15 D1 CS DQS9 (DM0) CS D8 DM DQS17 (DM8) CB4 CB5 CB6 CB7 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0 D10 DQS I/O 3 I/O 2 I/O 1 I/O 0 D11 DQS I/O 3 I/O 2 I/O 1 I/O 0 D12 DQS I/O 3 I/O 2 I/O 1 I/O 0 D13 DQS I/O 3 I/O 2 I/O 1 I/O 0 D14 CS CS CS CS CS DQS I/O 3 I/O 2 I/O 1 I/O 0 D15 DQS I/O 3 I/O 2 I/O 1 I/O 0 D16 DQS I/O 3 I/O 2 I/O 1 I/O 0 RS0A RS0B RBA0 - RBAn RA0 - RA12 RRAS RCAS RCKE0A RCKE0B RWE CS BA0 -BAn : SDRAMs DQ0 - D17 A0 -An : SDRAMs D0 - D17 RAS : SDRAMs D0 - D17 CAS : SDRAMs DQ0 - D17 CKE : SDRAMs D0 - D8 CKE : SDRAMs D9 - D17 WE: SDRAMs D0 - D17 RESET 3 DM D9 CS DM DM DM DM DM Serial PD DM SCL SDA WP CS DM V DDSPD CS D17 A0 A1 A2 SA0 SA1 SA2 SPD VD D /V DDQ D0 - D17 VREF D0 - D17 V SS D0 - D17 DM D0 - D17 V827332N04S MOSEL VITELIC Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 Vss A1 CB0* CB1* VDD DQS8* A0 CB2* VSS CB3* BA1 Key Key DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC A13* VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ BA2* DQ20 A12* VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4* CB5* VDDQ CK0* CK0* VSS DM8* A10 CB6* VDDQ CB7* Key key VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 RAS DQ45 VDDQ CS0 CS1 DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD 53 54 55 56 57 58 59 60 61 145 146 147 148 149 150 151 152 153 Notes: * These pins are not used in this module. Pin Names Pin Pin Description VDD Power Supply Pin Pin Description VDDQ DQs Power Supply CK1, CK1, CK2, CK2 Differential Clock Inputs VSS Ground CS0 Chip Select Input VREF Reference Power Supply CKE0 Clock Enable Input VDDSPD Power Supply for SPD RAS, CAS, WE Commend Sets Inputs SA0~SA2 E2 PROM Address Inputs A0 ~ A11 Address SCL E2 PROM Clock BA0, BA1 Bank Address SDA E2 PROM Data I/O DQ0~DQ63 Data Inputs/Outputs VDDID VDD Identification Flag DQS0~DQS7 Data Strobe Inputs/Outputs DU Do not Use DM0~DM7 Data-in Mask NC No Connection V827332N04S Rev. 1.1 May 2002 4 V827332N04S MOSEL VITELIC Serial Presence Detect Information Bin Sort: A1 (PC1600 @ CL2) B0 (PC2100B @ CL2.5) B1 (PC2100A @ CL2) Function Supported Byte # Function described 0 Defines # of Bytes written into serial memory at module manufacturer 128bytes 80h 1 Total # of Bytes of SPD memory device 256bytes 08h 2 Fundamental memory type SDRAM DDR 07h 3 # of row address on this assembly 12 0Ch 4 # of column address on this assembly 11 0Bh 5 # of module Rows on this assembly 1 Bank 01h 6 Data width of this assembly 72 bits 48h 7 .........Data width of this assembly - 00h 8 VDDQ and interface standard of this assembly SSTL 2.5V 04h 9 DDR SDRAM cycle time at CAS Latency =2.5 10 DDR SDRAM Access time from clock at CL=2.5 11 DIMM configuration type(Non-parity, Parity, ECC) 12 Refresh rate & type 13 A1 B0 8ns 7.5ns ±0.8ns B1 Hex value 7ns ±0.75n ±0.75n A1 B0 B1 80h 75h 70h 80h 75h 75h Non-parity, ECC 02h 15.6us & Self refresh 80h Primary DDR SDRAM width x4 04h 14 Error checking DDR SDRAM data width x4 04h 15 Minimum clock delay for back-to-back random column address tCCD =1CLK 01h 16 DDR SDRAM device attributes : Burst lengths supported 2,4,8 0Eh 17 DDR SDRAM device attributes : # of banks on each DDR SDRAM 4 banks 04h 18 DDR SDRAM device attributes : CAS Latency supported 2,2.5 0Ch 19 DDR SDRAM device attributes : CS Latency 0CLK 01h 20 DDR SDRAM device attributes : WE Latency 1CLK 02h 21 DDR SDRAM module attributes Registered address& control inputs and On-card DLL 26h 22 DDR SDRAM device attributes : General +/-0.2V voltage tolerance 00h 23 DDR SDRAM cycle time at CL =2 24 DDR SDRAM Access time from clock at CL =2 25 10ns 10ns 7.5ns A0h A0h 75h ±0.8ns ±08n ±0.75 80h 80h 75h DDR SDRAM cycle time at CL =1.5 - - - 00h 26 DDR SDRAM Access time from clock at CL =1.5 - - - 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 18ns 50h 50h 48h 28 Minimum row activate to row active delay(=tRRD) 15ns 15ns 14ns 3Ch 3Ch 38h V827332N04S Rev. 1.1 May 2002 5 V827332N04S MOSEL VITELIC Serial Presence Detect Information (cont.) Function Supported Byte # Function described Hex value A1 B0 B1 A1 B0 B1 29 Minimum RAS to CAS delay(=tRCD) 20ns 20ns 18ns 50h 50h 48h 30 Minimum active to precharge time(=tRAS) 50ns 45ns 45ns 32h 2Dh 2Dh 31 Module Row density 32 Command and address signal input setup time 1.1ns 0.9ns 0.9ns B0h 90h 90h 33 Command and address signal input hold time 1.1ns 0.9ns 0.9ns B0h 90h 90h 34 Data signal input setup time 0.6ns 0.5ns 0.5ns 60h 50h 50h 35 Data signal input hold time 0.6ns 0.5ns 0.5ns 60h 50h 50h 36-40 256MB Superset information (may be used in future) 40h - 00h 41 SDRAM device minimum active to active/auto-refresh time (=tRC ) 70ns 65ns 60ns 46h 41h 3Ch 42 SDRAM device minimum active to autorefresh to active/auto-refresh time (=tRFC) 80ns 75ns 67ns 50h 4Bh 43h 43 SDRAM device maximum device cycle time (=tCK MAX) 12ns 12ns 12ns 30h 30h 30h 44 SDRAM device maximum skew between DQS and DQ signals (=tDQSQ) 0.6ns 0.5ns 0.5ns 3Ch 32h 32h 45 SDRAM device maximum read datahold skew factor (=tQHS) 1ns 0.75ns 0.75ns A0h 75h 75h 62 SPD data revision code 63 Checksum for Bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65 -71 72 73-90 Initial release Mosel Vitelic ....... Manufacturer JEDEC ID code 00h F5 3B 40h 00h Manufacturing location 02=Taiwan 05=China 0A=S-CH Module part number (ASCII) V827332N04S 91 Manufacturer revison code (For PCB) 0 00 92 Manufacturer revison code (For component) 0 00 93 Manufacturing date (Week) - - 94 Manufacturing date (Year) - - Assembly serial # - - Undefined 00h Undefined 00h 95~98 99~127 Manufacturer specific data (may be used in future) 128~255 Open for customer use V827332N04S Rev. 1.1 May 2002 6 DA V827332N04S MOSEL VITELIC DC Operating Conditions (TA = 0 to 70°C, Voltage referenced to VSS = 0V) Parameter Symbol Min Typ. Max Unit Power Supply Voltage VDD 2.3 2.5 2.7 V Power Supply Voltage VDDQ 2.3 2.5 2.7 V Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V Input Low Voltage VIL -0.3 - VREF - 0.15 V I/O Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V VREF 1.15 1.25 1.35 V II -2 - 2 µA Output Leakage Current IOz -5 - 5 µA Output High Current (VOUT = 1.95V) IOH -16.8 - - mA Output Low Current (VOUT = 0.35V) IOL 16.8 - - mA Reference Voltage Input Leakage Current Note 1 2 3 Notes: 1. VDDQ must not exceed the level of VDD . 2. VIL (min) is acceptable -1.5V AC pulse width with ð 5ns of duration. 3. The value of VREF is approximately equal to 0.5VDDQ. AC Operating Conditions (TA = 0 to 70 °C, Voltage referenced to VSS = 0V) Parameter Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) Input Differential Voltage, CK and CK inputs VID(AC) Input Crossing Point Voltage, CK and CK inputs VIX(AC) Max Unit Note V VREF - 0.31 V 0.7 VDDQ + 0.6 V 1 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. V827332N04S Rev. 1.1 May 2002 7 V827332N04S MOSEL VITELIC AC Operating Test Conditions (TA = 0 to 70°C, Voltage referenced to VSS = 0V) Parameter Value Unit Reference Voltage VDDQ x 0.5 V Termination Voltage VDDQ x 0.5 V AC Input High Level Voltage (VIH, min) VREF + 0.31 V AC Input Low Level Voltage (VIL, max) VREF - 0.31 V VREF V Output Timing Measurement Reference Level Voltage VTT V Input Signal maximum peak swing 1.5 V Input minimum Signal Slew Rate 1 V/ns Termination Resistor (RT) 50 Ohm Series Resistor (R S) 25 Ohm Output Load Capacitance for Access Time Measurement (C L) 30 pF Input Timing Measurement Reference Level Voltage Vtt=0.5*VDDQ RT=50Ω Output Z0=50Ω CLOAD=30pF VREF =0.5*V DDQ Output Load Circuit (SSTL_2) Input/Output Capacitance (VDD = 2.5V, VDDQ = 2.5V, TA = 25°C, f = 1MHz) Parameter Symbol Min Max Unit Input capacitance (A0 ~ A11, BA0 ~ BA1, RAS, CAS, WE) CIN1 60 75 pF Input capacitance (CKE0) CIN2 40 48 pF Input capacitance (CS0) CIN3 40 48 pF Input capacitance (CLK1, CLK2) CIN4 30 32 pF Data & DQS input/output capacitance (DQ 0~DQ63) COUT 10 12 pF Input capacitance (DM0~DM8) CIN5 10 12 pF V827332N04S Rev. 1.1 May 2002 8 V827332N04S MOSEL VITELIC DDR SDRAM IDD SPEC TABLE A1(PC1600@CL=2) B0(PC2100B@CL=2.5) B1(PC2100A@CL=2) Typical Worst Typical IDD0 1450 1440 IDD1 1650 IDD2P Symbol Unit Worst Typical Worst 1350 1440 1080 1170 mA 1710 1575 1710 1280 1395 mA 750 720 675 720 540 585 mA IDD2F 895 945 655 945 720 765 mA IDD2Q 830 810 765 810 630 675 mA IDD3P 980 765 720 765 585 630 mA IDD3N 900 990 900 990 720 810 mA IDD4R 1980 2250 1980 2250 1620 1845 mA IDD4W 2115 2385 2115 2385 1710 1890 mA IDD5 2115 2385 2115 2385 1710 1890 mA Normal 36 36 36 36 36 36 mA Low power 18 18 18 18 18 18 mA 3375 3825 3375 3825 2745 3150 mA IDD6 IDD7 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Detailed test conditions for DDR SDRAM IDD1 & IDD IDD1 : Operating current: One bank operation 1. Typical Case : Vdd = 2.5V, T=25’ C 2. Worst Case : Vdd = 2.7V, T= 10’ C 3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP V827332N04S Rev. 1.1 May 2002 9 V827332N04S MOSEL VITELIC AC Characteristics (AC operating conditions unless otherwise noted) (PC2100A) (PC2100B) Symbol Min Min Max Min Max Unit Row Cycle Time tRC 60 - 65 - 70 - ns Auto Refresh Row Cycle Time tRFC 67 - 75 - 80 - ns Row Active Time tRAS 45 120K 48 120K 50 120K ns Row Address to Column Address Delay tRCD 18 - 20 - 20 - ns Row Active to Row Active Delay tRRD 14 - 15 - 15 - ns Column Address to Column Address Delay tCCD 1 - 1 - 1 - CLK Row Precharge Time tRP 18 - 20 - 20 - ns Write Recovery Time tWR 15 - 15 - 15 - ns Last Data-In to Read Command tDRL 1 - 1 - 1 - CLK Auto Precharge Write Recovery + Precharge Time tDAL 35 - 35 - 35 - ns System Clock Cycle Time tCK 7 12 7.5 12 8 12 ns 7.5 12 10 12 10 12 ns Parameter CAS Latency = 2.5 CAS Latency = 2 Max (PC1600) Note Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CLK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CLK Data-Out edge to Clock edge Skew tAC -0.75 0.75 -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Clock edge Skew tDQSCK -0.75 0.75 -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Data-Out edge Skew tDQSQ - 0.5 - 0.5 - 0.6 ns Data-Out hold time from DQS tQH tHPmin -0.75ns - tHPmin -0.75ns - tHPmin -0.75ns - ns 1 Clock Half Period tHP tCH/L min - tCH/L min - tCH/L min - ns 1 Input Setup Time (fast slew rate) tIS 0.9 - 0.9 - 1.1 - ns 2,3,5,6 Input Hold Time (fast slew rate) tIH 0.9 - 0.9 - 1.1 - ns 2,3,5,6 Input Setup Time (slow slew rate) tIS 1.0 - 1.0 - 1.1 - ns 2,4,5,6 Input Hold Time (slow slew rate) tIH 1.0 - 1.0 - 1.1 - ns 2,4,5,6 tIPW 2.2 - 2.2 - - - ns 6 Write DQS High Level Width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 CLK Write DQS Low Level Width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 CLK CLK to First Rising edge of DQS-In tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 CLK Data-In Setup Time to DQS-In (DQ & DM) tDS 0.5 - 0.5 - 0.6 - ns 7 Data-in Hold Time to DQS-In (DQ & DM) tDH 0.5 - 0.5 - 0.6 - ns 7 DQ & DM Input Pulse Width tDIPW 1.75 - 1.75 - 2 - ns Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 CLK Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK Input Pulse Width V827332N04S Rev. 1.1 May 2002 10 V827332N04S MOSEL VITELIC AC Characteristics (cont.) (PC2100A) (PC2100B) Symbol Min Min Max Min Max Unit Write DQS Preamble Setup Time tWPRES 0 - 0 - 0 - CLK Write DQS Preamble Hold Time tWPREH 0.25 - 0.25 - 0.25 - CLK Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 CLK Mode Register Set Delay tMRD 2 - 2 - 2 - CLK Power Down Exit Time tPDEX 10 - 10 - 10 - ns Exit Self Refresh to Non-Read Command tXSNR 75 - 75 - 80 - ns Exit Self Refresh to Read Command tXSRD 200 - 200 - 200 - CLK Average Periodic Refresh Interval tREFI - 15.6 - 15.6 - 15.6 us Parameter Max (PC1600) Note 8 Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE. 3. For command/address input slew rate >=1.0V/ns 4. For command/address input slew rate >=0.5V/ns and <1.0V/ns 5. CK, CK slew rates are >=1.0V/ns 6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM 8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Absolute Maximum Ratings Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 °C Storage Temperature TSTG -55 ~ 125 °C VIN , V OUT -0.5 ~ 3.6 V VDD -0.5 ~ 3.6 V VDDQ -0.5 ~ 3.6 V Output Short Circuit Current IOS 50 mA Power Dissipation PD 8 W TSOLDER 260 • 10 °C • Sec Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to V SS Soldering Temperature • Time Note: Operation at above absolute maximum rating can adversely affect device reliability V827332N04S Rev. 1.1 May 2002 11 V827332N04S MOSEL VITELIC Module Dimensions (Standard) FRONT VIEW .125 (3.175) MAX 5.256 (133.50) 5.244 (133.20) U10 U1 U2 U3 U4 U5 U6 U8 U7 U9 1.705 (43.31) 1.695 (43.05) .079 (2.00) R (4X) U11 U13 U12 .700 (17.78) TYP. .098 (2.50) D (2X) .091 (2.30) TYP. .035 (0.90) R PIN 1 .050 (1.27) TYP. 2.55 (64.77) .091 (2.30) TYP. .040 (1.02) TYP. .394 (10.00) TYP. .250 (6.35) TYP. 1.95 (49.53) PIN 92 4.750 (120.65) BACK VIEW U14 U15 U16 U17 U18 U19 U20 PIN 184 U22 PIN 93 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN V827332N04S Rev. 1.1 May 2002 U21 12 .054 (1.37) .046 (1.17) V827332N04S MOSEL VITELIC Module Dimensions (Low Profile) FRONT VIEW .125 (3.175) MAX 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (4X) U11 U1 U2 U3 U4 U5 U6 U7 U8 U9 1.205 (30.61) 1.195 (30.35) U12 .700 (17.78) TYP. .098 (2.50) D (2X) .091 (2.30) TYP. .035 (0.90) R PIN 1 .050 (1.27) TYP. 2.55 (64.77) .091 (2.30) TYP. .040 (1.02) TYP. .394 (10.00) TYP. .250 (6.35) TYP. 1.95 (49.53) PIN 92 4.750 (120.65) BACK VIEW U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U10 PIN 93 PIN 184 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN V827332N04S Rev. 1.1 May 2002 13 .054 (1.37) .046 (1.17) V827332N04S MOSEL VITELIC Label Information Module Density MOSEL VITELIC Part Number Criteria of PC2100 or PC1600 (refer to MVI datasheet) DIMM manufacture date code V827332N04SXXX-XX PC2100R-2533-080-A XXXX-XXXXXXX Assembly in Taiwan 256MB PC2100 R - 2533 - 08 0 - A REGISTERED DIMM Gerber file JEDEC CL = 2.5 (CLK) tRCD = 3 (CLK) tRP = 3 (CLK) V827332N04S Rev. 1.1 May 2002 14 SPD Revision 0 V827332N04S MOSEL VITELIC WORLDWIDE OFFICES U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-6323-1801 FAX: 65-6323-7013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 U.S. SALES OFFICES WEST CENTRAL / EAST 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029 © Copyright , MOSEL VITELIC Corp. Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. V827332N04S Rev. 1.1 May 2002 15