SCDS119A − JANUARY 2003 − REVISED OCTOBER 2003
D Output Voltage Translation Tracks VCC
D Supports Mixed-Mode Signal Operation On
D
D
D
D
D
D
D VCC Operating Range From 2.3 V to 3.6 V
D Data I/Os Support 0 to 5-V Signaling Levels
All Data I/O Ports
− 5-V Input Down To 3.3-V Output Level
Shift With 3.3-V VCC
− 5-V/3.3-V Input Down To 2.5-V Output
Level Shift With 2.5-V VCC
5-V Tolerant I/Os With Device Powered-Up
or Powered-Down
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low ON-State Resistance (ron)
Characteristics (ron = 5 Ω Typical)
Low Input/Output Capacitance Minimizes
Loading (Cio(OFF) = 4.5 pF Typical)
Data and Control Inputs Provide
Undershoot Clamp Diodes
Low Power Consumption
(ICC = 20 µA Max)
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D Control Inputs Can be Driven by TTL or
D
D
D
D
D
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
Supports Digital Applications: Level
Translation, USB Interface, Bus Isolation
Ideal for Low-Power Portable Equipment
DCT OR DCU PACKAGE
(TOP VIEW)
1OE
1A
1B
GND
1
8
2
7
3
6
4
5
VCC
2OE
2B
2A
description/ordering information
The SN74CB3T3306 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),
allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O
ports by providing voltage translation that tracks VCC. The SN74CB3T3306 supports systems using 5-V TTL,
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
The SN74CB3T3306 is organized as two 1-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. It
can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch
is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high,
the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
SSOP − DCT
Tape and reel
TOP-SIDE
MARKING‡
SN74CB3T3306DCTR
WA6_ _ _
−40°C to 85°C
VSSOP − DCU
Tape and reel SN74CB3T3306DCUR
WA6_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
‡ DCT: The actual top-side marking has three additional characters that designate the year, month, and
assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &/* &*#$' "! *0%' '&#)$*&'
'&%.%#. 1%##%&2 #".)(&" +#"(*''3 ."*' "& *(*''%#-2 (-).*
&*'&3 "! %-- +%#%$*&*#'
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1
SCDS119A − JANUARY 2003 − REVISED OCTOBER 2003
description/ordering information (continued)
VCC
5.5 V
VCC
IN
≈VCC − 1 V
≈VCC
OUT
≈VCC − 1 V
CB3T
0V
0V
Input Voltages
Output Voltages
NOTE A: If the input high voltage (VIH) level is greater than or equal to VCC − 1 V, and less than or equal to 5.5 V, then the output high voltage
(VOH) level will be equal to approximately the VCC voltage level.
Figure 1. Typical DC Voltage-Translation Characteristics
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each bus switch)
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
logic diagram (positive logic)
3
2
1A
1OE
1B
SW
1
5
2A
6
SW
7
2OE
2
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2B
SCDS119A − JANUARY 2003 − REVISED OCTOBER 2003
simplified schematic, each FET switch (SW)
† Gate Voltage (VG) is approximately
equal to VCC + VT when the switch is ON
and VI > VCC + VT.
A
B
VG†
Control
Circuit
EN‡
‡ EN is the internal enable signal applied to the switch.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)§
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
§ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
TA
Data input/output voltage
MIN
MAX
2.3
3.6
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
1.7
5.5
2
5.5
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
−40
85
°C
Operating free-air temperature
UNIT
V
V
V
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCDS119A − JANUARY 2003 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VCC = 3 V,
II = −18 mA
VOH
See Figures 3 and 4
IIN
Control inputs
IOZ‡
VCC = 3.6 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0,
ICC
∆ICC§
Control inputs
Cin
Control inputs
TYP†
VCC = 3.6 V,
VIN = 3.6 V to 5.5 V or GND
VCC = 3.6 V,
Switch ON,
VIN = VCC or GND
II
MIN
VCC = 3.6 V,
II/O = 0,
Switch ON or OFF,
VIN = VCC or GND
VCC = 3 V to 3.6 V,
One input at VCC − 0.6 V,
Other inputs at VCC or GND
MAX
UNIT
−1.2
V
±10
µA
±20
VI = VCC − 0.7 V to 5.5 V
VI = 0.7 V to VCC − 0.7 V
−40
±10
µA
10
µA
VI = VCC or GND
20
VI = 5.5 V
20
A
µA
300
VCC = 3.3 V,
VIN = VCC or GND
µA
3
pF
4.5
pF
Cio(OFF)
VCC = 3.3 V,
VI/O = 5.5 V, 3.3 V, or GND,
Switch OFF,
VIN = VCC or GND
VCC = 3.3 V,
Switch ON,
VIN = VCC or GND
VI/O = 5.5 V or 3.3 V
Cio(ON)
VI/O = GND
15
VCC = 2.3 V,
TYP at VCC = 2.5 V,
VI = 0
IO = 24 mA
5
8
IO = 16 mA
5
8
VCC = 3 V,
VI = 0
IO = 64 mA
IO = 32 mA
5
7
5
7
ron¶
µA
±5
VI = 0 to 0.7 V
4
pF
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
¶ Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.
4
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SCDS119A − JANUARY 2003 − REVISED OCTOBER 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
PARAMETER
tpd†
ten
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
OE
A or B
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
0.15
1
8.5
1
UNIT
MAX
0.25
ns
6.5
ns
tdis
OE
A or B
1
9
1
9
ns
† The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
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SCDS119A − JANUARY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
Input Generator
VI
S1
RL
VO
50 Ω
VG2
CL
(see Note A)
RL
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
Output
Control
(VIN)
V∆
VCC
VCC/2
VCC
VCC/2
0V
tPLH
VOH
Output
VCC/2
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VCC/2
0V
tPZL
VCC/2
Open
GND
50 Ω
Output
Control
(VIN)
2 × VCC
VOL + V∆
VOL
tPHZ
VCC/2
VOH − V∆
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: B. CL includes probe and jig capacitance.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
E. The outputs are measured one at a time with one transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
I. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
6
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SCDS119A − JANUARY 2003 − REVISED OCTOBER 2003
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
4.0
VCC = 2.3 V
IO = 1 µA
TA = 25°C
3.0
V − Output Voltage − V
O
V − Output Voltage − V
O
4.0
2.0
1.0
VCC = 3 V
IO = 1 µA
TA = 25°C
3.0
2.0
1.0
0.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0.0
1.0
VI − Input Voltage − V
2.0
3.0
4.0
5.0
6.0
VI − Input Voltage − V
Figure 3. Data Output Voltage vs Data Input Voltage
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SCDS119A − JANUARY 2003 − REVISED OCTOBER 2003
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
3.5
4.0
VCC = 2.3 V ~ 3.6 V
VI = 5.5 V
TA = 85°C
VOH − Output Voltage High − V
VOH − Output Voltage High − V
4.0
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = 25°C
3.5
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.5
2.7
2.9
3.1
3.3
3.5
3.7
2.3
2.5
2.7
2.9
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
V
− Output Voltage High − V
OH
4.0
3.5
3.1
VCC − Supply Voltage − V
VCC − Supply Voltage − V
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = −40°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
VCC − Supply Voltage − V
Figure 4. VOH Values
8
100 µA
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3.5
3.7
3.3
3.5
3.7
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
SN74CB3T3306DCTR
ACTIVE
SM8
DCT
8
3000
TBD
CU SNPB
Level-1-235C-UNLIM
SN74CB3T3306DCUR
ACTIVE
US8
DCU
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
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