DATA SHEET MOS INTEGRATED CIRCUIT µPD16448A SOURCE DRIVER FOR 240-OUTPUT TFT-LCD (NAVIGATION, AUTOMOBILE LCD-TV) µPD16448A is a source driver for TFT liquid crystal panels. This IC consists of a multiplexer circuit supporting a variety of pixel arrays, a shift register that generates sampling timing, and two sample and hold circuits that sample analog voltages. Because the two sample and hold circuits alternately execute sampling and holding, a high definition can be obtained. In addition, simultaneous sampling and successive sampling are automatically selected according to the pixel array of the LCD panel. It is ideal for a wide range of applications, including navigation systems and automobile LCDTVs. FEATURES • Can be driven on 5 V (Dynamic range: 4.3 V, VDD2 = 5.0 V) • 240-output • fmax. = 18 MHz (VDD1 = 3.0 V) • Simultaneous/successive sampling selectable according to pixel array Simultaneous sampling: vertical stripe Successive sampling: delta array, mosaic array • Two sample and hold circuits • Low output deviation between pins (± 20 mV MAX.) • Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit • Left and right shift selected by R/L pin • Single-side mounting possible ORDERING INFORMATION Part Number Package µPD16448AN-××× TCP (TAB package) Remark The dimensions of TCP are custom-made. Please consult NEC for details. The information in this document is subject to change without notice. Document No. S11712EJ3V0DS00 (3rd edition) Date Published August 1998 NS CP(K) Printed in Japan The mark ★ shows major revised points. © 1998 µPD16448A BLOCK DIAGRAM CLI1 to 3 R/L 3 STHR 240-bit shift register STHL INH VDD1 240-bit level shifter +3.3 V RESET VSS1 GND VSS2 C1 C2 VSS3 Multiplexer 240-bit sample and hold buffer VDD2 C3 MP/TH ..................................................................................................... MP/1.5 H1 H240 SAMPLE AND HOLD CIRCUIT AND OUTPUT CIRCUIT VIDEO LINE – + Swa1 Swb1 CH1 Hn – + Swa2 CH2 2 Swb2 +5.0 V µPD16448A ★ PIN CONFIGRATION (µ PD16448A N-xxx) C1 H240 C2 H239 C3 H238 VDD2 H237 VDD1 • STHL • MP/TH Copper Foll • MP/1.5 suface • R/L • RESET • INH • CLI1 • CLI2 • CLI3 • TEST H5 STHR H4 VSS1 H3 VSS3 H2 VSS2 H1 Remark This figure does not spesify the TCP package. 3 µPD16448A 1. PIN DESCRIPTION Symbol Name Function C1 to C3 Video signal input Input R, G, and B video signals. H1 to H240 Video signal output Video signal output pins. Output sampled and held video signals during horizontal period. STHR STHL Cascade I/O Start pulse I/O pins of sample hold timing. STHR serves as an input pin and STHL, as an output pin, in the case of right shift. In the case of left shift, STHL serves as an input pin, and STHR, as an output pin. CLI1 CLI2 CLI3 Shift clock input A start pulse is read at the rising edge of CLI1. Sampling pulse SHPn is generated at the rising edge of CLI1 through CLI3 during successive sampling, and at the rising edge of CLI1 during simultaneous sampling (for details, refer to the Timing charts in 2.FUNCTION DESCRIPTION). INH Inhibit input Selects a multiplexer and one of the two sample and hold circuits at the falling edge. RESET Reset input Resets the select counter of the multiplexer and the selector circuit of the two sample and hold circuits when it goes high. After reset, the multiplexer is turned OFF, so sure to input one pulse of the INH signal before inputting the video signal. If the video signal is input without the INH signal, sampling is not executed. MP/TH Multiplexer circuit select input (1) Four types of color filter arrays can be supported by combination of MP/TH and MP/1.5. Mode MP/1.5 Multiplexer circuit select input (2) MP/TH Vertical stripe array L L Single-side delta array L H Mosaic array H L Double-side delta array H H R/L = H; right shift: STHR → H1 → H240 → STHL R/L = L; left shift: STHL → H240 → H1 → STHR R/L Shift direction select input VDD1 Logic power supply 3.0 V to 5.5 V VDD2 Driver power supply 5.0 V ± 0.5 V VSS1 Logic ground Connect this pin to ground of system. VSS2 Driver ground Connect this pin to ground of system. VSS3 Driver ground Connect this pin to ground of system. TEST Test pin Fix this pin to L. 4 MP/1.5 µPD16448A 2. FUNCTION DESCRIPTION 2.1 Multiplexer Circuit This circuit selects RGB video signals input to the C1, C2, and C3 pins according to the pixel array of the liquid crystal panel, and outputs the signals to the H1 through H240 pins. Vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the MP/TH and MP/1.5 pins. 2.1.1 Vertical stripe array mode (MP/TH = L, MP/1.5 = L) In this mode, the relation between video signals C1, C2, and C3, and output pins is as shown below. This mode is used to drive a panel of vertical stripe array. In this mode, the multiplexer circuit is in the through status. Relation between video signals C1, C2, and C3, and output pins (during right shift) Line No. (number of INHs) RESET INH H1 (H240) H2 (H239) H3 (H238) H4 (H237) H239 (H2) H240 (H1) 0 H L Sampling C1 (C3) Sampling C2 (C2) Sampling C3 (C1) Sampling C1 (C3) Sampling C2 (C2) Sampling C3 (C1) 1 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) Output C2 (C2) Output C3 (C1) 2 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) Output C2 (C2) Output C3 (C1) 3 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) Output C2 (C2) Output C3 (C1) : : : : : : : : : : : : : : : : : : ( ) indicates the case of left shift. Pixel arrangement of vertical stripe array and multiplexer operation R → C1 B → C2 G → C3 µ PD16448A Right shift (R/L = "H"), MP/TH = "L", MP/1.5 = "L" H1 H2 H3 H4 H5 H6 H7 R B G R B G R R B G R B G R R B G R B G R R B G R B G R R B G R B G R 5 µPD16448A Timing chart of vertical stripe array RESET INH H1 (H240) sampling input data Output H2 (H239) sampling input data Output 6 C2 (C2) Undefined C3 (C1) Undefined Output H240 (H1) sampling input data Undefined Undefined Output H239 (H2) sampling input data C1 (C3) Undefined Output H3 (H238) sampling input data Undefined Undefined C2 (C2) Undefined Undefined C3 (C1) Undefined C1 (C3) C1 (C3) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C1 (C3) C1 (C3) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C1 (C3) C1 (C3) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C1 (C3) C1 (C3) C1 (C3) C2 (C2) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C3 (C1) C2 (C2) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C3 (C1) µPD16448A 2.1.2 Single-side delta array mode (MP/TH = L, MP/1.5 = H) Relation between video signals C1, C2, and C3, and output pins Line No. (number of INHs) RESET INH H1 (H240) H2 (H239) H3 (H238) H4 (H237) H239 (H2) H240 (H1) 0 H L Undefined Undefined Undefined Undefined Undefined Undefined 1 L ↓ Sampling C1 (C3) Sampling C2 (C2) Sampling C3 (C1) Sampling C1 (C3) Sampling C2 (C2) Sampling C3 (C1) 2 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) Output C2 (C2) Output C3 (C1) 3 L ↓ Output C2 (C1) Output C3 (C3) Output C1 (C2) Output C2 (C1) Output C3 (C3) Output C1 (C2) 4 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) Output C2 (C2) Output C3 (C1) 5 L ↓ Output C2 (C1) Output C3 (C3) Output C1 (C2) Output C2 (C1) Output C3 (C3) Output C1 (C2) ( ) indicates the case of left shift. Pixel arrangement of single-side delta array and multiplexer operation R → C1 B → C2 G → C3 µ PD16448A Right shift (R/L = H), MP/TH = "L", MP/1.5 = "H" H1 H2 H3 H4 H5 H6 H7 R B G R B G R B G R B R B G R B G R B G R B R B G R B G B G R B G R G R B G R B R B G R B G G R B G G R 7 µPD16448A Timing chart of single-side delta array RESET INH H1 (H240) sampling input data Undefined Undefined Output H2 (H239) sampling input data Undefined Output H3 (H238) sampling input data Output 8 Undefined Undefined Undefined Undefined Output H240 (H1) sampling input data Undefined Undefined Output H239 (H2) sampling input data C1 (C3) Undefined Undefined Undefined Undefined Undefined Undefined C2 (C2) Undefined C3 (C1) Undefined C2 (C2) Undefined C3 (C1) Undefined C2 (C1) C1 (C3) C3 (C3) C2 (C2) C1 (C2) C3 (C1) C3 (C3) C2 (C2) C1 (C2) C3 (C1) C1 (C3) C2 (C1) C2 (C2) C3 (C3) C3 (C1) C1 (C2) C2 (C2) C3 (C3) C3 (C1) C1 (C2) C2 (C1) C1 (C3) C2 (C1) C3 (C3) C2 (C2) C3 (C3) C1 (C2) C3 (C1) C1 (C2) C3 (C3) C2 (C2) C3 (C3) C1 (C2) C3 (C1) C1 (C2) µPD16448A 2.1.3 Double-side delta array mode (MP/TH = H, MP/1.5 = H) Because the pad pitch of the µPD16448A is designed so that the IC is mounted on one side, the output pitch must be expanded on the TCP if the IC is mounted on both sides. Relation between video signals C1, C2, and C3, and output pins Line No. (number of INHs) RESET INH H1 (H240) H2 (H239) H3 (H238) H4 (H237) H239 (H2) H240 (H1) 0 H L Undefined Undefined Undefined Undefined Undefined Undefined 1 L ↓ Sampling C2 (C3) Sampling C3 (C2) Sampling C1 (C1) Sampling C2 (C3) Sampling C3 (C2) Sampling C1 (C1) 2 L ↓ Output C2 (C3) Output C3 (C2) Output C1 (C1) Output C2 (C3) Output C3 (C2) Output C1 (C1) 3 L ↓ Output C1 (C1) Output C2 (C3) Output C3 (C2) Output C1 (C1) Output C2 (C3) Output C3 (C2) 4 L ↓ Output C2 (C3) Output C3 (C2) Output C1 (C1) Output C2 (C3) Output C3 (C2) Output C1 (C1) 5 L ↓ Output C1 (C1) Output C2 (C3) Output C3 (C2) Output C1 (C1) Output C2 (C3) Output C3 (C2) ( ) indicates the case of left shift. Pixel arrangement of double-side delta array and multiplexer operation R → C1 B → C2 G → C3 µ PD16448A Right shift (R/L = "H"), MP/TH = "H", MP/1.5 = "H" H1 R B B B G G R R B H3 B G G R R B G R B G R B G R R B G R B G R G H240 G → C1 R → C2 B → C3 H3 H2 µ PD16448A R B H239 G R B H238 G H237 Left shift (R/L = "L"), MP/TH = "H", MP/1.5 = "H" 9 µPD16448A Timing chart of double-side delta array RESET INH H1 (H240) sampling input data Undefined Undefined Output H2 (H239) sampling input data Undefined Output H3 (H238) sampling input data Output 10 Undefined Undefined Undefined Undefined Output H240 (H1) sampling input data Undefined Undefined Output H239 (H2) sampling input data C2 (C3) Undefined Undefined Undefined Undefined Undefined Undefined C3 (C2) Undefined C1 (C1) Undefined C3 (C2) Undefined C1 (C1) Undefined C1 (C1) C2 (C3) C2 (C3) C3 (C2) C3 (C2) C1 (C1) C2 (C3) C3 (C2) C3 (C2) C1 (C1) C2 (C3) C1 (C1) C3 (C2) C2 (C3) C1 (C1) C3 (C2) C3 (C2) C2 (C3) C1 (C1) C3 (C2) C1 (C1) C2 (C3) C1 (C1) C2 (C3) C3 (C2) C2 (C3) C3 (C2) C1 (C1) C3 (C2) C2 (C3) C3 (C2) C2 (C3) C3 (C2) C1 (C1) C3 (C2) µPD16448A 2.1.4 Mosaic array mode (MP/TH = H, MP/1.5 = L) Relation between video signals C1, C2, and C3, and output pins Line No. (number of INHs) RESET INH H1 (H240) H2 (H239) H3 (H238) H4 (H237) H239 (H2) H240 (H1) 0 H L Undefined Undefined Undefined Undefined Undefined Undefined 1 L ↓ Sampling C1 (C3) Sampling C2 (C2) Sampling C3 (C1) Sampling C1 (C3) Sampling C2 (C2) Sampling C3 (C1) 2 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) Output C2 (C2) Output C3 (C1) 3 L ↓ Output C3 (C2) Output C1 (C1) Output C2 (C3) Output C3 (C2) Output C1 (C1) Output C2 (C3) 4 L ↓ Output C2 (C1) Output C3 (C3) Output C1 (C2) Output C2 (C1) Output C3 (C3) Output C1 (C2) 5 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) Output C2 (C2) Output C3 (C1) : : : : : : : : : : : : : : : : : : ( ) indicates the case of left shift. Pixel arrangement of mosaic array and multiplexer operation R → C1 G → C2 B → C3 µ PD16448A Right shift (R/L = "H"), MP/TH = "H", MP/1.5 = "L" H1 H2 H3 H4 H5 H6 H7 R G B R G B R B R G B R G B G B R G B R G R G B R G B R B R G B R G B 11 µPD16448A Timing chart of mosaic array RESET INH H1 (H240) sampling input data Undefined Undefined Output H2 (H239) sampling input data Undefined Output H3 (H238) sampling input data Output 12 Undefined Undefined Undefined Undefined Output H240 (H1) sampling input data Undefined Undefined Output H239 (H2) sampling input data C1 (C3) Undefined Undefined Undefined Undefined Undefined Undefined C2 (C2) Undefined C3 (C1) Undefined C2 (C2) Undefined C3 (C1) Undefined C3 (C2) C1 (C3) C1 (C1) C2 (C2) C2 (C3) C3 (C1) C1 (C1) C2 (C2) C2 (C3) C3 (C1) C2 (C1) C3 (C2) C3 (C3) C1 (C1) C1 (C2) C2 (C3) C3 (C3) C1 (C1) C1 (C2) C2 (C3) C1 (C3) C2 (C1) C1 (C3) C2 (C2) C3 (C3) C2 (C2) C3 (C1) C1 (C2) C3 (C1) C2 (C2) C3 (C3) C2 (C2) C3 (C1) C1 (C2) C3 (C1) µPD16448A 2.1.5 Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn (1) Simultaneous sampling (( ) indicates the case of left shift.) CLI1 STHR (STHL) SHP1 (SHP240) C1 sampling SHP2 (SHP239) C2 sampling SHP3 (SHP238) C3 sampling SHP4 (SHP237) C1 sampling SHP5 (SHP236) C2 sampling SHP6 (SHP235) C3 sampling Remark C1 through C3 are sampled while SHPn is H. (2) Successive sampling (( ) indicates the case of left shift.) CLI1 CLI2 3-phase clock CLI3 STHR (STHL) SHP1 (SHP240) C1 sampling SHP2 (SHP239) C2 sampling SHP3 (SHP238) C3 sampling SHP4 (SHP237) C1 sampling SHP5 (SHP236) C2 sampling SHP6 (SHP235) C3 sampling Remarks 1. Input a three-phase clock to shift clock pins CLI1 through CLI3. 2. The video signals (C1, C2, and C3) are sampled while SHPn is H. 13 µPD16448A 2.2 Sample and Hold Circuit The sample and hold circuit samples and holds the video input signals C1 through C3 selected by the multiplexer circuit in the timing shown below. Swa1 through Swb2 are reset by the RESET signal and change at the rising and falling edges of the INH signal. (Refer to BLOCK DIAGRAM.) RESET Data Undefined Undefined INH Swa1 Swa2 Swb1 Swb2 14 on on µPD16448A ★ 2.3 Write Operation Timing The sampled video signals are written to the LCD panel by output currents IVOL and IVOH via output buffer. The dynamic range is 4.3 VMIN. (VDD2 = 5.0 V). While INH = H, do not stop shift clocks CLI1 through CLI3. The output operation of this IC is controlled by INH signals. INH = Hiz INH = Connected with internal circuit (switch sample and hold circuit at the falling edge.) Therefore, performing Vcom inversion while INH = L causes current flow to these IC output pins, which may result in malfunction. Perform Vcom in version during INH = H (Hi-z) and start output operation of the next line after the Vcom signal is stable enough to operate. Make sure to evaluate this output operation sufficiently. INH Output voltage 1 horizontal period 1 horizontal period Vcom 15 µPD16448A [Cautions on Use] 1. Turn ON power to VDD1, logic input, VDD2, and video signal input in that order to prevent destruction due to latchup, and turn off power in the reverse sequence. Observe this power sequence even during the transition period. 2. This IC is designed to input successive signals such as chrome signals. The input band of the video signals is designed to be 9 MHz MAX. If video signals faster than that are input, display is not performed correctly. 3. Insert a bypass capacitor of 0.1 µF between VDD1 and VSS1 and between VDD2 and VSS2. If the power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage fluctuates. 4. Display may not be correctly performed if noise is superimposed on the start pulse pin. Therefore, be sure to input a reset signal during the vertical blanking period. 5. Even if the start pulse width is extended by half a clock or more, sampling start timing SHP1 is not affected, and the sampling operation is performed normally. 6. When the multiplexer circuit is used in the vertical stripe mode, C 1, C2, and C3 are simultaneously sampled at the rising edge of SHPn. Internally, however, only CLI1 is valid. Therefore, input a shift clock to CLI1 only. At this time, keep the CLI2 and CLI3 pins to "L". When using the multiplexer circuit in the delta array mode or mosaic array mode, C1, C2, and C3 are sequentially sampled. Input a three-phase clock to CLI1 through CLI3. (For the sampling timing, refer to 2. FUNCTION DESCRIPTION.) 7. The recommended timing of tR-1 and PWRES on starting is shown below. (The following timing chart shows simultaneous sampling.) An INH pulse width of at least 5 clocks is required to reset the internal logic. Unless the INH pulse is input after reset, sampling is not performed in the correct sequence. CLI1 1 2 3 4 5 1 2 3 PWRES RESET tISETUP tR–I tIHOLD PWINH: 5 clocks MIN. INH 3 clocks MIN. STHR (STHL) SHP1 to 3 SHP4 to 6 SHP7 to 9 16 µPD16448A 3.ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, VSS1 = VSS2 = 0 V) Parameter Symbol Condition Ratings Unit Logic supply voltage VDD1 -0.5 to +7.0 V Driver supply voltage VDD2 -0.5 to +7.0 V -0.5 to VDD1 +0.5 V Logic input voltage VI Video input voltage VVI +0.5 V Logic output voltage V01 -0.5 to VDD1 +0.5 V Driver output voltage V02 -0.5 to VDD2 +0.5 V Driver output current IO2 ±10 mA Operating temperature range TA -30 to +85 °C Storage temperature range Tstg -65 to +125 °C C1, C2, C3 -0.5 to VDD2 Caution If the absolute maximum rating of even one of the above parameters is exceeded eve momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. RECOMMENDED OPERATING CONDITIONS (TA = -30 to +85 °C, VSS1 = VSS2 = 0 V) Parameter Symbol MIN. TYP. MAX. Unit Logic supply voltage VDD1 3.0 3.3 5.5 V Driver supply voltage VDD2 4.5 5.0 5.5 V Video input voltage VVI VSS2 + 0.35 VDD2 - 0.35 V Driver output voltage V02 VSS2 + 0.35 VDD2 - 0.35 V Input voltage, high VIH 0.7•VDD1 VDD1 V Input voltage, low VIL 0 0.3•VDD1 V 17 µPD16448A ELECTRICAL CHARACTERISTICS (TA = -30 to +85 °C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ±0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Maximum video signal output voltage VVOH Condition MIN. TYP. MAX. VDD2 - 0.35 Minimum video signal output voltage VVOL Logic output voltage, high VLOH STHL, STHR pins IOH = -1.0 mA Logic output voltage, low VLOL STHL, STHR pins IOL = 1.0 mA Video signal output current, high IVOH INH = L VO = VDD2 - 0.5 V Video signal output current, low IVOL INH = L Vof = 1.0 V, VO = 0.5 V V 0.35 0.9•VDD1 V V -0.20 -0.08 Unit 0.1•VDD1 V -0.08 mA 0.20 mA Reference voltage 1 VREF1 VDD2 = 5.0 V, TA = 25 °C VVI = 0.5 V 0.49 V Reference voltage 2 VREF2 VDD2 = 5.0 V, TA = 25 °C VVI = 2.0 V 1.99 V Reference voltage 3 VREF3 VDD2 = 5.0 V, TA = 25 °C VVI = 3.5 V 3.49 V Output voltage deviation 1 ∆VVO1 VDD2 = 5.0 V, TA = 25 °C VVI = 0.5 V ±20 mV Output voltage deviation 2 ∆VVO2 VDD2 = 5.0 V, TA = 25 °C VVI = 2.0 V ±20 mV ±20 mV Output voltage deviation 3 ∆VVO3 VDD2 = 5.0 V, TA = 25 °C VVI = 3.5 V Logic input leakage current ILL ±1.0 µA Video input leakage current IVL ±10 µA Logic dynamic current consumption IDD1 VDD1 = 3.3 ±0.3 V 2.5 mA VDD1 = 5.0 ±0.5 V 4.0 Driver dynamic current consumption IDD2 fCLI = 14 MHz VVI = 2.0 V, no load fINH = 15.4 kHz PWINH = 5.0 µs fCLI = 14 MHz VVI = 2.0 V, no load fINH = 15.4 kHz PWINH = 5.0 µs 10.0 mA Remarks 1. Vof: output applied voltage, VO: output voltage without load 2. The reference values are typical values only. The output deviation is only guaranteed within the chip. 18 µPD16448A SWITCHING CHARACTERISTICS (TA = -30 to +85 °C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 ±0.5 V, VSS1 = VSS2 = 0 V) Parameter Start pulse propagation delay time Symbol Condition MIN. TYP. MAX. Unit tPHL CL = 20 pF 10 54 ns tPLH CL = 20 pF 10 54 ns Maximum clock frequency 1 fmax. 1 Maximum clock frequency 2 15 MHz fmax. 2 With 3-phase clock input Logic input capacitance CI1 Other than STHL, STHR 8 15 MHz pF STHL, STHR input capacitance CI2 STHL, STHR 20 pF Video input capacitance C3 C1 to C3, VVI = 2.0 V 50 pF TIMING REQUIREMENTS (TA = -30 to +85 °C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 ± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Clock pulse width PWCLI Start pulse setup time Start pulse hold time Condition Duty = 50 % MIN. TYP. MAX. Unit 33 ns tSETUP 8 ns tHOLD 8 ns Reset pulse width PWRES 66 ns INH setup time tISETUP 33 ns INH hold time tIHOLD 33 ns Reset-INH time tR-I 81 ns INH pulse width PWINH 5 CLK Remark Keep the rise and fall times of the logic input signals to within tr = tf = 5 ns (10 to 90%). As an example, the switching characteristic wave of CLI1 is defined on the next page. 19 µPD16448A SWITCHING CHARACTERISTIC WAVE (simultaneous/successive sampling) Start Pulse Input Timing PWCLI1 PWCLI1 VDD1 CLI1 50 % 50 % VSS1 tSETUP tHOLD VDD1 STHR (STHL) 50 % 50 % VSS1 VDD1 SHP1 (SHP240) VSS1 Start Pulse Output Timing VDD1 CLI1 50 % 50 % VSS1 tPLH tPHL VOH STHL (STHR) 50 % 50 % VOL Remark The input/output timing of the start pulse is the same for simultaneous/successive sampling. 20 µPD16448A ★ RESET INH Pulse Timing 50% CLI1 PWRES RESET 50% 50% tISETUP tIIHOLD 50% INH 50% tR-I PWINH 21 µPD16448A 4. RECOMMENDED CONDITIONS FOR INSTALLATION This product should be installed under the following recommended conditions. Consult one of our sales representatives for installation under conditions other than those recommended. Installation Condition Thermocompression bonding Installation Method Condition Soldering Heat with heating tool at 300 °C to 350 °C under pressure of 100 g (per pin) for 2 to 3 seconds ACF (sheet type adhesive agent) Temporary adhesion at 70 °C to 100 °C under pressure of 3 to 2 8 kg/cm for 3 to 5 seconds Permanent adhesion at 165 °C to 180 °C under pressure of 25 to 2 45 kg/cm for 30 to 40 seconds (when aeolotropic conductive film SUMIZAC 1003 from Sumitomo Bakelite Co., Ltd. is used) Caution For installation conditions for the ACF part, contact the ACF manufacturer beforehand. Do not mix different installation methods. 22 µPD16448A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 23 µPD16448A REFERENCE NEC Semiconductor Device Reliability/Quality Control System C10983E Quality Grade on NEC Semiconductor Devices C11531E The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC’s Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5