TI TPS2080

 SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
D 80-mΩ High-Side MOSFET Switch
D 500 mA Continuous Current per Channel
D Independent Thermal and Short-Circuit
D
D
D
D
D
D
D
D
D
TPS2080, TPS2081, AND TPS2082
D PACKAGE
(TOP VIEW)
GND
IN1
IN2
EN1†
Protection With Overcurrent Logic Output
Operating Range . . . 2.7-V to 5.5-V
CMOS- and TTL-Compatible Enable Inputs
2.5-ms Typical Rise Time
Undervoltage Lockout
10 µA Maximum Standby Supply Current
Bidirectional Switch
Available in 8-Pin and 16-Pin SOIC
Packages
Ambient Temperature Range, 0°C to 85°C
ESD Protection
1
8
2
7
3
6
4
5
OC
OUT1
OUT2
EN2†
† See Available Options table
TPS2085, TPS2086 AND TPS2087
D PACKAGE
(TOP VIEW)
GNDA
IN1
IN2
EN1†
GNDB
IN3
IN4
EN3†
description
1
16
2
15
3
14
4
13
5
12
6
11
OCA
OUT1
OUT2
EN2†
OCB
OUT3
OUT4
EN4†
The TPS2080, TPS2081, and TPS2082 dual and
7
10
the TPS2085, TPS2086 and TPS2087 quad
8
9
power-distribution switches are intended for
applications where heavy capacitive loads and
† See Available Options table
short circuits are likely to be encountered. The
TPS208x devices incorporate 80-mΩ N-channel
MOSFET high-side power switches for power-distribution systems that require multiple power switches in a
single package. Each switch is controlled by an independent logic enable input. Gate drive is provided by an
internal charge pump designed to control the power-switch rise times and fall times to minimize current surges
during switching. The charge pump requires no external components and allows operation from supplies as low
as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS208x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from
a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present. The TPS208x devices are designed to current limit at 1.0-A load.
GENERAL SWITCH CATALOG
33 mΩ, single TPS201xA 0.2 A − 2 A
TPS202x
TPS203x
80 mΩ, single TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055
80 mΩ, dual
0.2 A − 2 A
0.2 A − 2 A
600 mA
1A
500 mA
500 mA
250 mA
250 mA
260 mΩ
IN1
OUT
IN2
1.3 Ω
TPS2042
TPS2052
TPS2046
TPS2056
500 mA
500 mA
250 mA
250 mA
TPS2100/1
IN1 500 mA
IN2 10 mA
TPS2102/3/4/5
IN1
500 mA
IN2
100 mA
80 mΩ, dual
TPS2080
TPS2081
TPS2082
TPS2090
TPS2091
TPS2092
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
80 mΩ, triple
TPS2043
TPS2053
TPS2047
TPS2057
500 mA
500 mA
250 mA
250 mA
80 mΩ, quad
TPS2044
TPS2054
TPS2048
TPS2058
500 mA
500 mA
250 mA
250 mA
80 mΩ, quad
TPS2085
TPS2086
TPS2087
TPS2095
TPS2096
TPS2097
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
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1
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
AVAILABLE OPTIONS
DUAL POWER DISTRIBUTION SWITCHES
RECOMMENDED
MAXIMUM
CONTINUOUS
LOAD CURRENT
(A)
ENABLE
TA
0°C
0
C to 85
85°C
C
EN1
EN2
Active high
Active high
Active high
Active low
Active low
Active low
TYPICAL
SHORT-CIRCUIT
CURRENT LIMIT
AT 25°C
(A)
PACKAGED
DEVICES
SMALL OUTLINE
(D)†
TPS2080D
0.5
TPS2081D
1.0
TPS2082D
QUAD POWER DISTRIBUTION SWITCHES
RECOMMENDED
MAXIMUM
CONTINUOUS
LOAD CURRENT
(A)
ENABLE
TA
0°C
0
C to 85
85°C
C
EN1
EN2
EN3
EN4
Active high
Active high
Active high
Active high
Active high
Active low
Active high
Active low
Active low
Active low
Active low
Active low
TYPICAL
SHORT-CIRCUIT
CURRENT LIMIT
AT 25°C
(A)
PACKAGED
DEVICES
SMALL OUTLINE
(D)†
TPS2085D
0.5
TPS2086D
1.0
TPS2087D
† The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2081DR)
TPS2082 functional block diagram
OC
Thermal
Sense
GND
EN1‡
Current
Limit
Driver
Charge
Pump
†
CS
IN1
VCC Select
and UVLO
OUT1
Power Switch
†
CS
IN2
Charge
Pump
Driver
EN2§
Thermal
Sense
† Current sense
‡ Active high for TPS2080 and TPS2081
§ Active high for TPS2080
2
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Current
Limit
OUT2
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
TPS2087 functional block diagram
OCA
Thermal
Sense
GNDA
EN1‡
Current
Limit
Driver
Charge
Pump
†
CS
IN1
VCC Select
and UVLO
OUT1
Power Switch
†
CS
IN2
OUT2
Charge
Pump
Current
Limit
Driver
EN2§
Thermal
Sense
OCB
Thermal
Sense
GNDB
EN3‡
Current
Limit
Driver
Charge
Pump
†
CS
IN3
VCC Select
and UVLO
OUT3
Power Switch
†
CS
IN4
OUT4
Charge
Pump
Driver
Current
Limit
EN4§
Thermal
Sense
† Current sense
‡ Active high for TPS2085 and TPS2086
§ Active high for TPS2085
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3
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
Terminal Functions
DUAL POWER-DISTRIBUTION SWITCHES
TERMINAL
NO.
NAME
TPS2080
TPS2081
EN1
EN2
5
I/O
DESCRIPTION
TPS2082
4
I
Enable input. Active low turns on power switch.
5
I
Enable input. Active low turns on power switch.
I
Enable input. Active high turns on power switch.
I
Enable input. Active high turns on power switch.
EN1
4
EN2
5
4
GND
1
1
1
I
Ground
IN1
2
2
2
I
N-Channel MOSFET Drain
IN2
3
3
3
I
N-Channel MOSFET Drain
OC
8
8
8
O
Overcurrent. Open drain output active low
OUT1
7
7
7
O
Power-switch output
OUT2
6
6
6
O
Power-switch output
QUAD POWER-DISTRIBUTION SWITCHES
TERMINAL
NO.
NAME
TPS2085
TPS2086
EN1
EN2
13
EN3
EN4
9
I/O
DESCRIPTION
TPS2087
4
I
Enable input. Active low turns on power switch.
13
I
Enable input. Active low turns on power switch.
8
I
Enable input. Active low turns on power switch.
9
I
Enable input. Active low turns on power switch.
I
Enable input. Active high turns on power switch.
I
Enable input. Active high turns on power switch.
I
Enable input. Active high turns on power switch.
I
Enable input. Active high turns on power switch.
EN1
4
4
EN2
13
EN3
8
EN4
9
GNDA
1
1
1
GNDB
5
5
5
IN1
2
2
2
I
N-channel MOSFET drain
IN2
3
3
3
I
N-channel MOSFET drain
IN3
6
6
6
I
N-channel MOSFET drain
8
Ground for IN1 and IN2 switch and circuitry
Ground for IN3 and IN4 switch and circuitry
IN4
7
7
7
I
N-channel MOSFET drain
OCA
16
16
16
O
Overcurrent indicator for switch 1 and switch 2. Active-low open drain output.
OCB
12
12
12
O
Overcurrent indicator for switch 3 and switch 4. Active low open drain output
OUT1
15
15
15
O
Power-switch output
OUT2
14
14
14
O
Power-switch output
OUT3
11
11
11
O
Power-switch output
OUT4
10
10
10
O
Power-switch output
4
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SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when
disabled. The power switch supplies a minimum of 500 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (ENx or ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic high is present on ENx or a logic low is present on ENx. A
logic low input on ENx or logic high on ENx restores bias to the drive and control circuits and turns the power
on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OCx)
The OCx open drain output is asserted (active low) when an overcurrent or over temperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
The TPS208x implements a dual thermal trip to allow fully independent operation of the power distribution
switches. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature
rises to approximately 140°C, the internal thermal sense circuitry checks to determine which power switch is
in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the
adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled approximately
20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The
(OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
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5
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI(IN) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Output voltage range, VO(OUTx) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VI(IN) + 0.3 V
Input voltage range, VI(ENx) or VI(ENx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Continuous output current, IO(OUTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
Electrostatic discharge (ESD) protection: Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V
Charged device model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . 750 V
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D-8
725 mW
5.8 mW/°C
464 mW
377 mW
D-16
1123 mW
9 mW/°C
719 mW
584 mW
PACKAGE
recommended operating conditions
Input voltage, VI(IN)
MIN
MAX
2.7
5.5
UNIT
V
Input voltage, VI(ENx) or VI(ENx)
0
5.5
V
Continuous output current, IO (per switch)
0
500
mA
Operating virtual junction temperature, TJ
0
125
°C
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(ENx) = 0 V, VI(ENx) = VI(INx) (unless otherwise noted)
supply current
PARAMETER
TEST CONDITIONS
MIN
TJ = 25°C
TYP
MAX
0.025
1
UNIT
Supply current, low-level
output
No Load on OUT
VI(ENx) = VI(IN),
VI(ENx) = 0 V
Supply current,
high-level output
No Load on OUT
VI(ENx) = 0 V,
VI(ENx) = VI(IN)
TJ = 25°C
−40°C ≤ TJ ≤ 125°C
100
Leakage current
OUT connected to ground
VI(ENx) = VI(IN),
VI(ENx) = 0 V
−40°C ≤ TJ ≤ 125°C
100
µA
Reverse leakage current
INx = high impedance
VI(ENx) = 0 V,
VI(ENx) = VI(IN)
TJ = 125°C
0.3
µA
6
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−40°C ≤ TJ ≤ 125°C
10
85
110
µA
A
µA
A
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(ENx) = 0 V, VI(ENx) = VI(INx) (unless otherwise noted) (continued)
power switch
TEST CONDITIONS†
PARAMETER
rDS(on)
Static drain-source on-state resistance
tr
Rise time, output
tf
Fall time, output
TYP
MAX
VI(IN) = 5 V,
VI(IN) = 5 V,
TJ = 25°C,
TJ = 85°C,
IO = 0.5 A
IO = 0.5 A
MIN
80
100
90
120
VI(IN) = 5 V,
VI(IN) = 3.3 V,
TJ = 125°C,
TJ = 25°C,
IO = 0.5 A
IO = 0.5 A
100
135
90
125
VI(IN) = 3.3 V,
VI(IN) = 3.3 V,
TJ = 85°C,
TJ = 125°C,
IO = 0.5 A
IO = 0.5 A
110
145
120
165
VI(IN) = 5.5 V,
RL=10 Ω
TJ = 25°C,
CL = 1 µF,
2.5
VI(IN) = 2.7 V,
RL=10 Ω
TJ = 25°C,
CL = 1 µF,
3
VI(IN) = 5.5 V,
RL=10 Ω
TJ = 25°C,
CL = 1 µF,
4.4
VI(IN) = 2.7 V,
RL=10 Ω
TJ = 25°C,
CL = 1 µF,
2.5
UNIT
mΩ
ms
ms
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input VI(ENx) or VI(ENx)
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
TEST CONDITIONS
2.7 V ≤ VI(IN) ≤ 5.5 V
MIN
TYP
MAX
2
V
4.5 V ≤ VI(IN) ≤ 5.5 V
0.8
2.7 V≤ VI(IN) ≤ 4.5 V
0.4
II
Input current
VI(ENx) = 0 V and VI(ENx) = VI(IN), or
VI(ENx) = VI(IN) and VI(ENx) = 0 V
ton
toff
Turnon time
CL = 100 µF,
Turnoff time
CL = 100 µF,
UNIT
−0.5
RL=10 Ω
RL=10 Ω
V
0.5
µA
20
ms
40
current limit
TEST CONDITIONS†
PARAMETER
IOS
Short-circuit output current
VI(IN) = 5 V, OUT connected to GND,
Device enabled into short circuit
MIN
0.7
TYP
1
MAX
1.3
UNIT
A
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
undervoltage lockout
PARAMETER
TEST CONDITIONS
Low-level input voltage
Hysteresis
MIN
TYP
2
TJ = 25°C
MAX
2.5
100
UNIT
V
mV
overcurrent OCx
PARAMETER
Sink current†
Output low voltage
Off-state current†
TEST CONDITIONS
VO = 5 V
IO = 5 mA,
VO = 5 V,
MIN
TYP
MAX
10
VOL(OCx)
VO = 3.3 V
UNIT
mA
0.5
V
1
µA
† Specified by design, not production tested.
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7
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
PARAMETER MEASUREMENT INFORMATION
OUTx
RL
tf
tr
CL
VO(OUTx)
90%
10%
90%
10%
TEST CIRCUIT
50%
VI(ENx)
50%
toff
ton
50%
toff
ton
90%
VO(OUTx)
50%
VI(ENx)
90%
VO(OUTx)
10%
10%
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
VI(EN)
(5 V/div)
VI(EN)
(5 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
RL = 10 Ω
VO(OUT)
(2 V/div)
0
1
2
3
4
5
6
7
8
9
VO(OUT)
(2 V/div)
10
t − Time − ms
Figure 2. Turnon Delay and Rise Time
With 0.1-µF Load
8
VI(IN) = 5 V
TA = 25°C
CL = 0.1 µF
RL = 10 Ω
0
2
4
6
8
10 12
t − Time − ms
14
16
18
Figure 3. Turnoff Delay and Fall Time
With 0.1-µF Load
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20
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
PARAMETER MEASUREMENT INFORMATION
VI(EN)
(5 V/div)
VI(EN)
(5 V/div)
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω
VO(OUT)
(2 V/div)
0
1
2
3
4
5
6
7
8
9
VI(IN) = 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω
VO(OUT)
(2 V/div)
0
10
2
4
6
8
10
12
14
16
18
20
t − Time − ms
t − Time − ms
Figure 4. Turnon Delay and Rise Time
With 1-µF Load
Figure 5. Turnoff Delay and Fall Time
With 1-µF Load
VI(IN) = 5 V
TA = 25°C
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
VI(IN) = 5 V
TA = 25°C
IO(OUT)
(0.5 A/div)
0
1
2
3
4
5
6
7
8
9
IO(OUT)
(0.5 A/div)
10
0
10
20
30
40
50
60
70
80
90 100
t − Time − ms
t − Time − ms
Figure 6. TPS2080, Short-Circuit Current,
Device Enabled Into Short
Figure 7. TPS2080, Threshold Trip Current
With Ramped Load on Enabled Device
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9
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
PARAMETER MEASUREMENT INFORMATION
VI(EN)
(5 V/div)
VO(OC)
(5 V/div)
470 µF
220 µF
100 µF
VI(IN) = 5 V
TA = 25°C
Ramp = 1 A/100 ms
IO(OUT)
(0.5 A/div)
0
20
40
60
VI(IN) = 5 V
TA = 25°C
RL = 10 Ω
IO(OUT)
(0.2 A/div)
80 100 120 140 160 180 200
0
2
4
t − Time − ms
6
8
10
12
Figure 8. OC Response With Ramped Load
on Enabled Device
VO(OC)
(5 V/div)
IO(OUT)
(0.5 A/div)
IO(OUT)
(1 A/div)
2000
3000
4000
5000
t − Time − µs
0
200
400
600
800
t − Time − µs
Figure 10. 4-Ω Load Connected to Enabled Device
10
18 20
VI(IN) = 5 V
TA = 25°C
VO(OC)
(5 V/div)
1000
16
Figure 9. Inrush Current With 100-µF, 220-µF
and 470-µF Load Capacitance
VI(IN) = 5 V
TA = 25°C
0
14
t − Time − ms
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Figure 11. 1-Ω Load Connected
to Enabled Device
1000
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
TURNON DELAY TIME
vs
INPUT VOLTAGE
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
3.5
12
CL = 1 µF
RL = 10 Ω
TA = 25°C
Turnon Delay Time − ms
Turnon Delay Time − ms
3.2
CL = 1 µF
RL = 10 Ω
TA = 25°C
2.9
2.6
10
8
6
2.3
2
2.5
3
3.5
4
4.5
5
5.5
4
2.5
6
3
VI − Input Voltage − V
3.5
4
4.5
5
VI − Input Voltage − V
Figure 12
5.5
6
5.5
6
Figure 13
RISE TIME
vs
INPUT VOLTAGE
FALL TIME
vs
INPUT VOLTAGE
3
2.2
CL = 1 µF
RL = 10 Ω
TA = 25°C
2.1
CL = 1 µF
RL = 10 Ω
TA = 25°C
f t − Fall Time − ms
r t − Rise Time − ms
2.7
2.4
2
1.9
1.8
1.7
2.1
1.6
1.8
2.5
3
3.5
4
4.5
5
5.5
1.5
2.5
6
VI − Input Voltage − V
Figure 14
3
3.5
4
4.5
5
VI − Input Voltage − V
Figure 15
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11
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
160
100
I I(IN) − Supply Current, Output Disabled − nA
I I(IN) − Supply Current, Output Enabled − µ A
110
VI(IN) = 5.5 V
VI(IN) = 5 V
90
VI(IN) = 4.5 V
80
70
VI(IN) = 3.3 V
VI(IN) = 2.7 V
60
50
−40
0
25
85
TJ − Junction Temperature − °C
140
VI(IN) = 5.5 V
120
100
VI(IN) = 4.5 V
VI(IN) = 3.3 V
80
60
VI(IN) = 2.7 V
40
20
0
−40
125
VI(IN) = 5 V
0
125
Figure 17
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
INPUT-TO-OUTPUT VOLTAGE
vs
LOAD CURRENT
160
40
VI(IN) − VI(OUT) − Input-to-Output Voltage − mV
r DS(on) − Static Drain-Source On-State Resistance − m Ω
85
TJ − Junction Temperature − °C
Figure 16
VI(IN) = 2.7 V
140
120
VI(IN) = 3 V
100
VI(IN) = 3.3 V
80
VI(IN) = 4.5 V
VI(IN) = 5 V
60
40
20
0
25
85
125
TJ − Junction Temperature − °C
TA = 25°C
VI(IN) = 2.7 V
35
VI(IN) = 3.3 V
30
25
VI(IN) = 5 V
20
VI(IN) = 4.5 V
15
10
5
0
100
150
200
IL − Load Current − mA
Figure 18
12
25
Figure 19
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250
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
1.2
TA = 25°C
Load Ramp = 1 A/10 ms
VI(IN) = 5.5 V
1.1
VI(IN) = 5 V
1.16
VI(IN) = 4.5 V
Threshold Trip Current − A
I OS − Short-Circuit Output Current − A
1.2
1
VI(IN) = 3.3 V
0.9
VI(IN) = 2.7 V
0.8
1.08
1.04
0.7
0.6
−40
1.12
25
85
0
TJ − Junction Temperature − °C
1
2.5
125
3
Figure 20
5.5
6
Figure 21
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
CURRENT LIMIT RESPONSE
vs
PEAK CURRENT
2.35
250
VI(IN) = 5 V
TA = 25°C
2.3
Start Threshold
Current Limit Response − µ s
UVLO − Undervoltage Lockout − V
3.5
4
4.5
5
VI − Input Voltage − V
2.25
Stop Threshold
2.2
200
150
100
50
2.15
2.1
0
−40
0
25
85
TJ − Junction Temperature − °C
125
0
2.5
5
7.5
10
12.5
Peak Current − A
Figure 22
Figure 23
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13
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
APPLICATION INFORMATION
TPS2082
Power Supply
2.7 V to 5.5 V
2
OUT1
8
4
5
Power Supply
2.7 V to 5.5 V
IN1
0.1 µF
3
0.1 µF
7
Load
0.1 µF
22 µF
0.1 µF
22 µF
OC
EN1
6
Load
OUT2
EN2
IN2
GND
1
Figure 24. Typical Application
power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.
overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do
not increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs
only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS208x senses the short and
immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figure 10 and
11). After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 8). The TPS208x is capable of delivering current up to the current-limit threshold without
damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.
OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. The TPS208x devices are
designed to reduce false overcurrent reporting. An internal overcurrent transient filter eliminates the need to use
external components to remove unwanted pulses. Using low-ESR electrolytic capacitors on the output lowers
the inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.
14
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SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
APPLICATION INFORMATION
OC response (continued)
V+
Rpullup
TPS2082
GND
OC
IN1
OUT1
IN2
OUT2
EN1
EN2
Figure 25. Typical Circuit for OC Pin
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to that of power packages; it is
good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of
the N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power
dissipation per switch can be calculated by:
P
D
+r
DS(on)
I2
Multiply this number by the total number of switches being used, to get the total power dissipation coming from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
T +P
J
D
R
qJA
)T
A
Where:
TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W (for 8 pin), 111°C/W (for 16 pin)
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS208x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal
to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The
protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal
sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch
continues to cycle in this manner until the load fault or input power is removed.
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15
SLVS202A − SEPTEMBER 2000 − REVISED MARCH 2001
APPLICATION INFORMATION
thermal protection (continued)
The TPS208x implements a dual thermal trip to allow fully independent operation of the power distribution
switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die temperature
rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is in an overcurrent
condition and turns that power switch off, thus isolating the fault without interrupting operation of the adjacent
power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach 160°C, both
switches turn off. The OC open-drain output is asserted (active low) when overtemperature or overcurrent
occurs.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.
generic hot-plug applications (see Figure 26)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS208x, these devices can be used
to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the
TPS208x also ensures the switch will be off after the card has been removed, and the switch will be off during
the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card
or module.
Overcurrent Response
Power
Supply
1000 µF
Optimum
0.1 µF
2.7 V to 5.5 V
1000 µF
Optimum
0.1 µF
PC Board
TPS2082
OC
GND
IN1
OUT1
IN2
EN1
Block of
Circuitry
OUT2
EN2
Block of
Circuitry
Figure 26. Typical Hot-Plug Implementation
By placing the TPS208x between the VCC input and the rest of the circuitry, the input power will reach these
devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing a slow voltage
ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
16
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