TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com 3A, 60V STEP DOWN DC/DC CONVERTER WITH LOW Iq Check for Samples: TPS54362-Q1, TPS54362A-Q1 FEATURES • 1 • 2 • • • • • • • • • • • Withstands Transients up to 60V With an Operating Range of 3.6V to 48V Asynchronous Switch Mode Regulator With External Components (L and C), Load Current up to 3A (max) 0.8V ± 1.5% Voltage Reference 200kHz to 2.2MHz Switching Frequency High Voltage Tolerant Enable Input for ON/OFF State Soft Start on Enable Cycle Slew Rate Control on Internal Power Switch External Clock Input for Synchronization Pulse Skip Mode (PFM) During Light Output Loads With Quiescent Current = 65μA Typical (LPM Operation) External Compensation for Wide Bandwidth Error Amplifier Internal Undervoltage Lock Out UVLO Programmable Reset Power on Delay Reset Function Filter Time for Fast Negative Transients Programmable Overvoltage Output Monitoring Programmable Undervoltage Output Monitoring, Issuance of Reset if Output Falls Below Threshold Thermal Shutdown During Excessive Power Dissipation Switch Current Limit Protection Short Circuit and Overcurrent Protection of FET Junction Temperature Range: –40°C to 150°C Package: 20-pin HTSSOP PowerPAD™ Qualified for Automotive Applications • • • • • • • • APPLICATIONS • • • • Automotive Telematics Navigation systems In-Dash Instrumentation Battery Powered Applications DESCRIPTION The TPS54362/TPS54362A is a step down switch mode power supply with voltage supervisor. Integrated input voltage line feed forward topology improves line transient regulation of the voltage mode buck regulator. The regulator has a cycle-by cycle current limit. A pulse skip mode operation under no load reduces the supply current to 65μA. Using the enable pin, the supply shutdown current is reduced to 1μA. VIN LPM Supply VIN 95% 90% Rslew Rslew = 5kW EN SS 90% 85% VIN = 6 V SYNC TPS54362 80% VReg BOOT PH Vreg Rslew = 35kW 75% VIN = 12 V, VReg = 5 V, Fsw = 500 kHz, L = 22 mH CO = 100 mF, TA = 25oC 70% Cdly VSENSE COMP RST_TH GND 65% 80% VIN = 20 V VReg = 5 V, Fsw = 500 kHz, L = 22 mH CO = 100 mF 75% 70% Rslew = 5 kW, o TA = 25 C 65% 60% 60% 0 OV_TH Efficency (%) RT Efficency (%) nRST 85% 0.5 1 1.5 2 IL - Load Current - A 2.5 3 0 0.5 1 1.5 2 2.5 3 IL - Load Current - A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) An open drain reset signal indicates when the nominal output drops below the threshold set by an external resistor divider network. The output voltage start up ramp is controlled by a soft start capacitor. There is an internal undervoltage shut down which is activated when the input supply ramps down to 2.6V. The device is protected during an overload conditions on the output by frequency fold back operation, and also has thermal shutdown protection due to excessive power dissipation. Table 1. ORDERING INFORMATION DEVICE NUMBER CURRENT OUTPUT ORDERABLE NUMBER TPS54362 3A TPS54362QPWPRQ1 TPS54362A 3A TPS54362AQPWPRQ1 ABSOLUTE MAXIMUM RATINGS (1) Input voltage Output voltage VALUE UNIT EN –0.3 to 60 V VIN –0.3 to 60 VReg –0.3 to 20 LPM –0.3 to 5.5 OV_TH –0.3 to 5.5 RST_TH –0.3 to 5.5 SYNC –0.3 to 5.5 VSENSE –0.3 to 5.5 BOOT –0.3 to 65 PH –0.3 to 60 V -2 for 30ns -1 for 200ns -0.85 at TJ= -40°C -0.5 at TJ= 125°C RT –0.3 to 5.5 RST –0.3 to 5.5 Cdly –0.3 to 8 SS –0.3 to 8 –0.3 to 7 COMP Temperature Electrostatic discharge HBM (1) (2) 2 Operating virtual junction temperature range, TJ –40 to 150 Storage temperature range, TS –55 to 165 °C 2 kV (2) °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN MAX VI Unregulated Buck supply input voltage (VIN, EN) 3.6 48 UNIT V VReg Regulator voltage range 0.9 18 V VReg Power up in Low Power Mode (LPM) or Discontinuous Mode (DCM) 0.9 5.5 V Bootstrap Capacitor (BOOT) 3.6 56 V Switched outputs (PH) 3.6 48 V Logic level inputs (RST, VSENSE, OV_TH, RST_TH, Rslew, SYNC, RT) 0 5.25 V Logic level inputs (SS, Cdly, COMP) 0 6.5 V θJA Thermal resistance junction to ambient (1) 35 °C/W θJC Thermal resistance junction to case (2) 10 °C/W 150 °C TJ (1) (2) (3) Operating junction temperature range (3) –40 This assumes a JEDEC JESD 51-5 standard board with thermal vias with High K profile – See PowerPAD section and application note from Texas Instruments (SLMA002) for more information. This assumes junction to exposed PAD. This assumes TA = TJ – Power dissipation × θJA (Junction to Ambient). Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 3 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com DC ELECTRICAL CHARACTERISTICS VIN = 7V to 48V, EN=VIN, TJ = –40°C to 150°C (unless otherwise noted) TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT POWER SUPPLY Normal mode–Buck mode after initial start up 3.6 48 V Low power mode: Info VIN Supply voltage on VIN line Falling threshold (LPM disabled) 8 Rising threshold (LPM activated) 8.5 High voltage threshold (LPM disabled) PT Iq-Normal Quiescent current normal mode 25 Open loop test – max duty cycle VIN = 7V to 48V ILOAD < 1mA, VIN = 12V, TA = 25°C PT PT Iq-LPM ISD Quiescent current; low power mode Shutdown V V 27 30 V 5 10 mA 65 75 μA –40 < TJ < 150°C 75 μA ILOAD < 1mA, VIN = 24V, TA = 25°C 85 μA –40 < TJ < 150°C 85 μA EN = 0V, device is OFF, TA = –40°C to 125°C, VIN = 24V 10 μA EN = 0V, device is OFF, TA = 25°C, VIN = 12V 1 4 TRANSITION TIMES (LOW POWER – NORMAL MODES) (1) CT td1 Transition delay between normal mode to low power mode VIN = 12V, VReg = 5V, ILoad = 1A to 1mA 100 μs CT td2 Transition delay between low power mode to normal mode VIN = 12V, VReg = 5V ILoad = 1mA to 1A 5 μs SWITCH MODE SUPPLY; VReg Info VReg CT VSENSE Feedback voltage Regulator output VSENSE = 0.8V ref VReg = 0.9 to 18, VIN = 7 V to 48 V 0.9 PT RDS(on) Internal switch resistance Measured across VIN and PH, ILoad = 500mA Info ICL Switch current limit cycle by cycle VIN = 12 V Info tON-Min Duty cycle pulse width Info tOFF-Min PT fsw Switch mode frequency PT fsw Internal oscillator frequency Info ISink Start up condition OV_TH = 0V, VReg = 10V Info ILimit Prevent overshoot 0V < OV_TH < 0.8V, VReg = 10V 0.788 18 0.8 0.812 500 4 6 8 Bench CHAR only 50 100 150 Bench CHAR only 100 200 250 Set using external resistor on RT pin 0.2 2.2 –10% 10% V V mΩ A ns MHz 1 mA 80 mA PT: Production Tested CT: Characterization Tested Only, NOT Production Tested Info: User Information only, NOT Production Tested (1) 4 This test is for characterization only Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com DC ELECTRICAL CHARACTERISTICS VIN = 7V to 48V, EN=VIN, TJ = –40°C to 150°C (unless otherwise noted) TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENABLE (EN) PT VIL Low input threshold PT VIH High input threshold PT Ilkg Leakage into EN terminal 0.7 V 1.7 V EN = 60V 100 135 μA EN = 12V 8 15 μA 2 2.6 μA RESET DELAY (Cdly) PT IO External capacitor charge current EN = high PT VThreshold Switching threshold Output voltage in regulation 1.4 2 V LOW POWER MODE (LPM) PT VIL Low input threshold VIN = 12V PT VIH High input threshold VIN = 12V PT Ilkg Leakage into LPM terminal LPM = 5V 0.7 V 95 μA 3.6 7 ms 00.768 0.832 V 1.7 V 65 RESET OUTPUT (RST) PT trdly POR delay timer Based on Cdly capacitor, Cdly = 4.7nF PT RST_TH Reset threshold for VReg Check RST output PT tnRSTdly Filter time Delay before RST is asserted low 10 20 35 μs 40 50 60 μA 0.7 V 95 μA 2200 kHz SOFT START (SS) PT ISS Soft-start source current SYNCHRONIZATION (SYNC) (1) PT VSYNC PT VIL VIH 1.7 V PT Ilkg Leakage SYNC = 5V 65 CT SYNC Input clock VIN= 12 V, Vreg = 5 V, fsw < fext < 2 × fsw Info SYNCtrans Ext clock to internal clock No external clock, VIN = 12 V, VReg = 5 V 32 μs Info SYNCtrans Int clock to external clock External clock = 1 MHz, VIN = 12 V, VReg = 5 V 2.5 μs CT SYNCCLK Min duty cycle CT SYNCCLK Max duty cycle CT IRslew Rslew = 50k 20 μA CT IRslew Rslew = 10k 100 μA 180 30% 70% Rslew OVERVOLTAGE SUPERVISORS (OV_TH) PT OV_TH Threshold for VReg during OV Internal Switch is turned OFF VReg = 5V Internal pull down on Vreg, with OV_TH = 1V 0.768 0.832 V 70 mA 175 °C 30 °C THERMAL SHUTDOWN CT CT TSD Thermal shutdown junction temperature THYS Hysteresis PT: Production Tested CT: Characterization Tested Only, NOT Production Tested (1) The SYNC input clock can have a maximum frequency of 2X the programmed clock frequency up to a maximum value of 1.1MHz. Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 5 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com DEVICE INFORMATION PWP 20-PIN PACKAGE TOP VIEW NC NC SYNC LPM EN RT Rslew RST Cdly GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 BOOT VIN VIN PH VReg COMP VSENSE RST_TH OV_TH SS PIN FUNCTIONS PIN NAME NO. I/O DESCRIPTION NC 1 NC Connect to ground NC 2 NC Connect to ground SYNC 3 I External synchronization clock input to override the internal oscillator clock. An internal pull down resistor of 62kΩ (typical) is connected to the ground. LPM 4 I Low-power mode control using digital input signal. An internal pull down resistor of 62kΩ (typical) is connected to the ground. EN 5 I Enable pin, internally pulled up. Must be externally pulled up or down to enable/disable the device. RT 6 O External resistor to ground to program the internal oscillator frequency. Rslew 7 O External resistor to ground to control the slew rate of internal switching FET. RST 8 O Active low, open drain reset output connected to external bias voltage through a resistor, asserted high after the device starts regulating. Cdly 9 O External capacitor to ground to program power on reset delay. GND 10 O Ground pin, must be electrically connected to the exposed pad on the PCB for proper thermal performance. SS 11 O External capacitor to ground to program soft start time. OV_TH 12 I Sense input for overvoltage detection on regulated output, an external resisitor network is connected between VReg and ground to program the overvoltage threshold. RST_TH 13 I Sense input for overvoltage detection on regulated output, an external resisitor network is connected between VReg and ground to program the reset and undervoltage threshold. VSENSE 14 I Inverting node of error amplifier for voltage mode control COMP 15 O Error amplifier output to connect external compensation components. VReg 16 I Internal low-side FET to load output during startup or limit overshoot. PH 17 O Source of the internal switching FET VIN 18 I Unregulated input voltage. Pin 18 and pin 19 must be connected externally. VIN 19 I Unregulated input voltage. Pin 18 and pin 19 must be connected externally. BOOT 20 O External bootstrap capacitor to PH to drive the gate of the internal switching FET. 6 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM 20 Bandgap ref LPM 4 D1 VIN Vsupply 18 R11 C1 7 R7 Internal supply 19 16 Gate Drive with Over-Current Limit for Internal Switch 5 R10 Rslew 0.8 V ref 0.2 V ref Internal Voltage Rail EN BOOT VIN VReg C3 L PH Vreg 17 RT R8 6 Selectable Oscillator Thermal Sensor D2 Error amp SYNC 3 Cdly 14 + 0.8 V ref 9 C2 R9 - 11 15 R12 RST + 0.8 V ref - 8 Reset with Delay Timer GND Voltage comp + - 0.82 V ref SS R5 C8 COMP RST_ TH C5 R6 R1 13 + 0.8 V ref 10 R4 VSENSE C6 Vreg C4 C7 ref Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 12 OV _ TH C10 R2 R3 C9 Submit Documentation Feedback 7 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS Efficiency Data of Power Supply FET SWITCHING (SLOW SLEW RATE) FAST SLEW RATE ON SWITCHING FET 90% 95% Rslew = 5kW 90% 85% 85% Efficency (%) 80% Efficency (%) VIN = 6 V Rslew = 35kW 75% VIN = 12 V, VReg = 5 V, Fsw = 500 kHz, L = 22 mH CO = 100 mF, o TA = 25 C 70% 65% 0.5 1 1.5 2 VIN = 20 V 75% VReg = 5 V, Fsw = 500 kHz, L = 22 mH CO = 100 mF 70% 65% 60% 0 80% 2.5 Rslew = 5 kW, TA = 25oC 60% 3 0 0.5 1 IL - Load Current - A 1.5 2 2.5 3 IL - Load Current - A Figure 1. Figure 2. Output Voltage Drop Out LOAD CURRENT > 100 mA LOAD CURRENT < 100 mA 7 7 6.5 No Load 10 mA 3A 5.5 VI - Intput Voltage - V VI - Intput Voltage - V 6 5 4.5 200 mA 4 536 mA 3.5 6 5 50 mA 4 100 mA 1.4 A 3 3 2.5 Input Voltage Ramp Down Tracking (Load at 5 V Output and fsw = 500 kHz) Input Voltage Ramp Down Tracking (Load at 5 V Output and fsw = 500 kHz) 2 0 1 4 2 3 VO - Output Voltage - V 5 2 2.5 3 3.5 4 4.5 VO - Output Voltage - V Figure 3. 8 Submit Documentation Feedback 5 5.5 Figure 4. Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE TRACKING 8 VReg = 5 V at Free Air 7 Start (power up) VI - Input Voltage - V 6 5 Tracking(power down) 4 3 2 1 0 0 0.05 0.1 0.15 IL - Load Current - A 0.2 Figure 5. NOTE Tracking: The input voltage at which the output voltage drops approximately -0.7 V of the regulated voltage or for low input voltages (tracking function) over the load range. Start: The input voltage required to achieve the 5V regulation on power up with the stated load currents. LPM, QUIESCENT CURRENT VARIATION WITH TEMPERATURE LPM, QUIESCENT CURRENT VARIATION WITH TEMPERATURE 77 68 VI = 24 V VI = 12 V 76 67 75 Quiescent Current - mA Quiescent Current - mA 66 65 64 63 62 74 73 72 71 70 61 69 60 68 59 -40 -20 0 20 40 60 80 100 120 140 TA - Free-Air Temperature - °C 67 -40 -20 20 40 60 80 100 120 140 0 TA - Free-Air Temperature - °C Figure 6. Figure 7. Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 9 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SHUT DOWN CURRENT SHUT DOWN CURRENT 10 4.5 VI = 24 V 4 9 3.5 8 Shut Down Current - mA Shut Down Current - mA VI = 12 V 3 2.5 2 1.5 7 6 5 4 3 1 2 0.5 1 0 -40 -20 0 -40 0 20 40 60 80 100 120 140 TA - Free-Air Temperature - °C -20 0 20 40 60 80 100 120 140 TA - Free-Air Temperature - °C Figure 8. Figure 9. INTERNAL REFERENCE VOLTAGE VOLTAGE DROP ON Rslew FOR CURRENT REFERENCE; (SLEW RATE / Rslew) 1006 798.5 1004 Voltage Drop on Rslew - mV Internal Reference Voltage - mV VI = 12 V 798 797.5 797 796.5 796 795.5 -40 1002 1000 998 996 -20 0 20 40 60 80 100 120 140 TA - Free-Air Temperature - °C 994 -40 -20 0 20 40 60 80 100 120 140 TA - Free-Air Temperature - °C Figure 10. 10 Submit Documentation Feedback Figure 11. Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) CURRENT CONSUMPTION WITH TEMPERATURE 5.6 IIN - Current Consumption - mA 5.55 EN = High, VI = 12 V 5.5 5.45 5.4 5.35 5.3 5.25 -50 -30 -10 10 30 50 70 90 110 130 150 TA - Free-Air Temperature - °C Figure 12. Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 11 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com OVERVIEW The TPS54362/TPS54362A is a 60V, 3A dc/dc step down (buck) converter using voltage-control mode scheme. The device features supervisory function for power-on-rest during system power on. Once the output voltage has exceeded the threshold set by RST_TH, a delay of 1ms/nF (based on capacitor value on RSTDLY terminal) is invoked before RST line is released high. Conversely on power down, once the output voltage falls below the same set threshold, the RST is pulled low only after a de-glitch filter of approximately 20μs (typ) expires. This is implemented to prevent RST from being triggered due to fast transient line noise on the output supply. An overvoltage monitor function, is used to limit output voltage to the threshold set by OV_TH. Both the RST_TH and OV_TH monitoring voltages are set to be a pre-scale of the output voltage, and thresholds based on the internal bias voltages of the voltage comparators (0.8V typical). Detection of undervoltage on the output is based on the RST_TH setting and will invoke RST line to be asserted low. Detection of over-voltage on the output is based on the OV_TH setting and will NOT invoke the RST line to be asserted low. However, the internal switch is commanded to turn OFF. In systems where power consumption is critical, low power mode is implemented to reduce the non-switching quiescent current during light load conditions. The PFM operation is determined when the system enters discontinuous current mode (DCM) for at least 100μs. The operation of when the device enters discontinuous mode is dependent on the selection of external components. If thermal shutdown is invoked due to excessive power dissipation, the internal switch is disabled and the regulated output voltage will start to decrease. Depending on the load line the regulated voltage could decay and the RST_TH threshold may assert the RST output low. DETAILED DESCRIPTION The TPS54362/TPS54362A is a DC/DC Converter using a voltage-control mode scheme with an input voltage feed-forward technique. The device can be programmed for a range of output voltages with a wide input voltage range. Below are details with regard to the pin functionality. INPUT VOLTAGE The VIN pin is the input power source for the TPS54362/TPS54362A. This pin must be externally protected against voltage level greater than 60V and reverse battery. In Buck Mode the input current drawn from this pin is pulsed, with fast rise and fall times. Therefore, this input line requires a filter capacitor to minimize noise. Additionally, for EMI considerations, an input filter inductor may also be required. FUNCTION MODE FUNCTION OPERATING VOLTAGE RANGE Buck 3.6V to 48V OUTPUT CURRENT CAPABILITY VReg = 0.9V to 18V and ILoad Up to 3A; however, at higher output power the part is derated for max temperature rating COMMENTS Optimum performance: VIN/VReg ratios should always be set such that min required duty cycle pulse (ton min) >150ns. The min off time is 250ns for ALL conditions. OUTPUT VOLTAGE VReg The output voltage VReg is generated by the converter supplied from the battery voltage VIN and the external components (L, C). The output is sensed through an external resistor divider and compared with an internal reference voltage. The value of the adjustable output voltage in Buck Mode is selectable between 0.9V and 18V by choosing the external resistors, according to the relationship: VReg = Vref (1 + R4/R5) (1) Where R5 and R4 are feedback resistors. Vref = 0.8V (typical) 12 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com The internal reference voltage has a ±1.5% tolerance. The overall output voltage tolerance will be dependent on the external feedback resistors. To determine the overall output voltage tolerance, use the following relationship: tolVReg = tolVref + (R4/(R4 + R5)) × (tolR4 + tolR5) (2) Where R4 and R5 are feedback resistors. Vref = 0.8V (typical) The VReg pin is also internally connected to a load of 100Ω, which is turned ON in the following conditions: • During startup conditions, when the device is powered up with no-load, or whenever EN is toggled, the internal load connected to VReg pin is turned ON for about 100 µs to charge the bootstrap capacitor to provide gate drive voltage to the switching transistor. • During normal operating conditions, when the regulated output voltage exceeds the overvoltage threshold (preset by external resisitors R1, R2, and R3), the internal load is turned ON, and this pin is pulled down to bring the regulated output voltage down. Typically an output capacitor within the range of 10-400μF is used. This terminal will have a filter capacitor with low ESR characteristics in order to minimize output ripple voltage. OSCILLATOR FREQUENCY: (RT) Oscillator frequency is selectable by means of a resistor placed at the RT pin. The switching frequency (Fsw) can be set in the range 200 kHz – 2200 kHz. In addition, the switching frequency can be imposed externally by a clock signal (Fext) at the SYNC pin with Fsw < Fext< 2×Fsw. In this case the external clock overrides the switching frequency determined by the RT pin and the internal oscillator is clocked by the external synchronization clock. 2000 fsw - Switching Frequency - kHz 1800 1600 1400 1200 40 V 1000 24 V 800 8V 14 V 600 400 200 0 100 200 300 Resistor on RT - kW 400 500 600 Figure 13. Switching Frequency vs Resistor Value SYNCHRONIZATION (SYNC) This is an external input signal to synchronize the switching frequency using an external clock signal. The synchronization input will over-ride the internally fixed oscillator signal. The synchronization signal has to be valid for approximately 2 clock cycles (pulses) before the transition is made for synchronization with the external frequency input. If the external clock input does NOT transition low or high for 32μS (typ), the system will default to the internal clock set by the RT pin. The SYNC input clock can have a maximum frequency of 2X the programmed clock frequency up to a maximum value of 2.2MHz Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 13 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com ENABLE / SHUTDOWN:(EN) The Enable pin provides electrical on/off control of the regulator. Once the Enable pin voltage exceeds the threshold voltage, the regulator starts operation and the internal soft start begins to ramp. If the Enable pin voltage is pulled below the threshold voltage, the regulator stops switching and the internal soft start resets. Connecting the pin to ground or to any voltage less than 0.7V disables the regulator and activate the shutdown mode. This pin must have an external pull up or pull down to change the state of the device. RESET DELAY (Cdly) The Reset delay pin sets the desired delay time to assert the RESET pin high after the supply has exceeded the programmed VReg_RST voltage. The delay may be programmed in the range of 2.2ms to 200ms using capacitors in the range of 2.2nF to 200nF. The delay time is calculated using the following equation: PORdly = 1ms / nF × C, Where C = capacitor on Cdly pin (3) RESET PIN (nRST) The RESET pin is an open-drain output. The power-on reset output is asserted low until the output voltage exceeds the programmed VReg_RST voltage threshold and the reset delay timer has expired. Additionally, whenever the ENABLE pin is low or open, RESET is immediately asserted low regardless of the output voltage. There is a reset filter timer to prevent reset being invoked due to short negative transients on the output line. If a thermal shut down occurs due to excessive thermal conditions this pin is asserted low when the switching FET is commanded OFF and output falls below the reset threshold. Power On Condition/ Reset Line Power Down Condition/ Reset Line VIN VIN Css Css VReg 0.92 x VReg Set by RST_TH Terminal VReg Cdly Cdly tdelay RST RST 20 ms (Typ-Deglitch Time) BOOST CAPACITOR (BOOT) This capacitor provides the gate drive voltage for the Internal MOSFET switch. X7R or X5R grade dielectrics are recommended due to their stable values over temperature. Boost cap may need to be tweaked lower for low Vreg and/or high frequencies applications. The cap may need to be tweaked higher for high Vreg and/or low frequencies applications. (e.g. 100nF for 500kHz/5V and 220n for 500kHz/8V.) 14 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com SOFT START (SS) On 1. 2. 3. 4. powerup or after a short circuit event , the following conditions are recommended: VIN – VReg > 2.5V Load current < 1A, until RST goes high. In discontinuous mode or LPM (i.e., light loads), in addition to 1), Vreg < 5.5V also applies. Equation 4 should be satisfied. This condition also applies when there is a short circuit on the output. 1.55 × Css 50 × 10 -6 < 30 × 10-6 × D × ILOAD CO L (4) Where: D = VO/VIN duty cycle. (5) Css = 1 nF to 220 nF, providing the above equations are satisfied. If the buck converter starts up with output shorted to ground, minimum 150nF Css is required with TPS54362A. Item 3 and item 4 are not applicable for TPS54362A. L is inductance of inductor. LOW POWER MODE (LPM) The TPS54362/TPS54362A enters automatically low power mode once the regulation goes into discontinuous mode. The internal control circuitry for any transition from Low Power Mode to High Power Mode occurs within 5μs (typ). In low power mode, the converter operates as a hysteretic controller with the threshold limits set by VReg_UV = 0.82 x (R1 + R2 +R3 / (R2 + R3), for the lower limit and ~VReg for the upper limit. To ensure tight regulation in the low power mode, R2 and R3 values are set accordingly. The device operates with both automatic and digital controlled low power mode. The digital low power mode can over-ride the automatic low power mode function by applying the appropriate signal on the LPM terminal. The part goes into active or normal mode for at least 100μs, whenever RST_TH or VREG_UV is tripped. In active mode or normal mode, ALL blocks including OV function are enabled. In LPM mode, OV function is disabled. Active or Normal Mode: When part is in DCM with LPM=High or in CCM with LPM=High or Low LPM: When part is in DCM with LPM = Low Automatic and Digital LPM high: device forced normal mode, fixed frequency, even at light load current (part will do pulse skipping to keep output voltage in regulation at light loads) LPM low or open: device will automatically change between normal and low power mode dependent on load current BUCK MODE LOW POWER MODE OPERATION When operating in low power mode (Buck reg), and if the output is shorted to ground, a reset is asserted. The thermal shutdown and current limiting circuitry is activated to protect the device. The low power mode operation is initiated once the converter enters discontinuous mode of operation. EXTERNAL LPM OPERATION The low power mode (LPM) is active low, if there is an open on this terminal the IC enters the low power mode (internal pull down). To allow low power mode operation, the load current has to be low and the LPM terminal is set to ground. To inhibit low power mode, the microcontroller has to drive the terminal high, and the converter is not in discontinuous mode of operation. Part can ONLY power-up in LPM/DCM if, VReg < 5.5V AND VIN-VReg > 2.5V. Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 15 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com In active mode. the part powers-up when VIN > 3.6V (min). Note: In LPM, the OV_TH circuit is not enabled. Active or Normal Mode: When the device is in CCM or DCM with LPM = High LPM: When the device is in DCM with LPM = Low SHORT CIRCUIT PROTECTION The TPS54362/TPS54362A features an output short-circuit protection. Short-circuit conditions are detected by monitoring the RST_TH, and when the voltage on this node drops below 0.2V, the switching frequency is decreased and current limit is folded back to protect the device. The switching frequency is fold back to approximately 25kHz and the current limit is reduced to 30% of the current limit typical value. OVERCURRENT PROTECTION Overcurrent protection is implemented by sensing the current through the NMOS switch FET. The sensed current is then compared to a current reference level representing the overcurrent threshold limit. If the sensed current exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn-on noise glitches. Once overcurrent indicator is set true, overcurrent protection is triggered. The MOSFET is turned off for the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle current limiting. If the sensed current continues to increase during cycle-by-cycle current limiting, the temperature of part will start rising, the TSD will kick in and shut down switching until part cools down. SLEW RATE CONTROL (Rslew) This pin controls the switching slew rate of the internal power NMOS. The slew rate will be set by an external resistor with a slew rate range shown below for rise and fall times. The range of rise time tr = 15ns to 35ns, and fall time tf = 15ns to 200ns, with Rslew range of 10k to 50k (see plots below). 35 350 14 V 8V 30 40 V 300 tf - Fall Time - ns tr - Rise Time - ns 24 V 25 20 15 40 V 10 250 24 V 200 14 V 150 8V 100 50 5 0 10 20 30 40 50 Rslew - Slew Resistor - kW Figure 14. FET Rise Time 60 70 0 10 20 30 40 50 60 70 Rslew - Slew Resistor - kW Figure 15. FET Fall Time THERMAL SHUTDOWN The TPS54362/TPS54362A protects itself from overheating with an internal thermal shutdown circuit. If the junction temperature exceeds the thermal shutdown trip point, the MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction temperature drops below the thermal shutdown hysteretic trip point. During low power mode operation the thermal shutdown sensing circuitry is disabled for low current consumption. Once RST or VReg_UV is asserted low the thermal shutdown monitoring is activated. REGULATION VOLTAGE (VSENSE) This pin is used to program the regulated output voltage based on a resistor feedback network monitoring the VO output voltage. The selected ratio of R4 to R5 will set the VReg voltage. 16 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com RESET THRESHOLD (RST_TH) This pin is programmable for setting the output accuracy for the low power mode (LPM) to set the undervoltage monitoring of the regulated output voltage (VReg_UV), and the voltage to initiate a rest output signal (VReg_RST). The resistor combination of R1 to R3 is used to program the threshold for detection of undervoltage. Voltage bias on R2 + R3 sets the Reset threshold. Undervoltage for transient and Low Power Mode Operation: VReg_UV = 0.82V × (R1 + R2 +R3 / (R2 + R3) Reset Threshold = VReg_RST = 0.8V × (R1 + R2 + R3 / (R2 + R3) (6) (7) Recommended range: 70% to 92% of the regulation voltage. OVERVOLTAGE SUPERVISOR for VReg (OV_TH) This pin is programmable to set the overvoltage monitoring of the regulated output voltage. The resistor combination of R1 to R3 is used to program the threshold for detection of overvoltage. The bias voltage of R3 sets the OV threshold and the output voltage accuracy in hysteretic mode during transient events. Overvoltage ref = VReg _OV = 0.8V x (R1 +R2 + R3) / (R3), (8) Recommended range: 106% to 110% of the regulation voltage NOISE FILTER ON RST_TH AND OV_TH TERMINALS There is some noise sensitivity on the RST_TH and OV_TH pins and capacitance is added to filter this noise. The noise is more pronounced with fast falling edges on the PH pin. So the smaller the Rslew resistor (minimum recommended value is 10kΩ) the more capacitance may be required on RST_TH and OV_TH. Users should use the smallest capacitance necessary, because larger values will increase the loop response time and degrade short circuit protection and transient response. The upper limit is determined by the 2μs maximum time constant seen on the OVTH/RSTTH when VReg = 0 V (i.e. [R2 + R3]×[C9 + C10] < 2μs). The noise in the RST_TH / OV_TH resistor chain may change with PCB layout or application set-up, so the RST_TH and/or the OVTH capacitor may not be needed in all applications. Users can place the footprint and only populate it, if necessary. Example VReg R1 = 36K R2 = 600 R3 = 6.6k C4 R1 RST _TH VReg_RST = 0.8 × (43.2k) /7.2k) = 4.8V R2 VReg_OV = 0.8 × (43.2k) /6.6k) = 5.24V C10 OV_TH R3 C9 Typical cap values for RST_TH/OV_TH caps are between 10 pf to 100 pf range for total resistance on RSTH/OVTH divider of < 200 kΩ. Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 17 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com OUTPUT TOLERANCES BASED ON MODES OF OPERATION VReg_OV VReg (UL) VReg Output VReg (LL) VReg_UV = 0.82 x (R1 + R2 + R3) / (R2 + R3) VReg_RST = 0.8 x (R1 + R2 + R3) / (R2 + R3) Load reg/Line reg in Hysteretic mode LPM Active (Normal) Modes Of Operation empty paragraph for space between the illustration and table Mode Of Operation VO - Lower Limit VO – Upper limit Comments Hysteretic Mode 0.82V × (R1 + R2 + R3)/(R2 + R3) 0.8V × (R1+R2+R3)/(R3) Min to max ripple on output Low power Mode 0.82V × (R1 + R2 + R3)/(R2 + R3) VReg + tolVReg Min to max ripple on output Active (Normal) VReg – tolVReg VReg + tolVReg Min to max ripple on output empty paragraph for space between the two tables Supervisor Thresholds VO - Typical value Tolerance Comments Overvoltage 0.8V × (R1 + R2 + R3)/(R3) ± (tolVref + (R1 + R2/[R1 + R2 + R3]) × (tolR1 + tolR2 + tolR3) Overvoltage threshold setting Reset 0.8V × (R1 + R2 + R3)/(R2 + R3) ± (tolVref + (R1/[R1 + R2 + R3]) × (tolR1 + tolR2 + tolR3) Reset threshold setting Load reg/Line reg in Hysteretic Mode This mode of operation is when a load or line transient step occurs in the application. The converter will go into a hysteretic mode of operation until the error amplifier stabilizes and controls the output regulation to a tighter output tolerance. During the load step the regulator upper threshold is set by the VReg_OV and the lower threshold is set by the VReg_UV limit. The converter enters this mode of operation during load or line transient events if the main control loop cannot respond to regulate within the specified tolerances. The regulator exits this mode once the main control loop responds. Internal Undervoltage Lock Out (UVLO) The IC is enabled on power up once the internal bandgap and bias currents are stabile, this is typically at VI = 3.4V (min). On power down, the internal circuitry is disabled at VI = 2.6V (max). 18 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com Loop Control Frequency Compensation L VReg C8 C7 C ESR R4 C4 R6 C5 R9 VSENSE Error AMP R5 COMP Vref = 0.8 V Type 3 Compensation Figure 16. Type 3 Compensation Type III Compensation fc = fsw × 0.1 (the cut off frequency, when the gain is 1 is called the unity gain frequency). The fc is typically 1/5 to 1/10 of the switching frequency, double pole frequency response due to the LC output filter The modulator break frequencies as a function of the output LC filter is derived from Equation 9 and Equation 10. The LC output filter gives a “Double Pole” which has a –180 degree phase shift 1 fLC = 1/2 2p (LCO ) (9) The ESR of the output capacitor C gives a “ZERO” that has a 90 degree phase shift 1 fESR = (2p CO ´ ESR) (R4 + R5) Vreg = Vref ´ R5 Vreg (R4 + R5) = 0.8V R5 (10) (11) (12) The VIN/Vr modulator gain is about 10 for 8V<VIN<50V. Vr is fixed at 1V for VIN<8V and 5V for VIN>48V Note that the VIN/Vr gain (Amod) is not precise and has a tolerance of about 20%. VIN Vramp = 10 æ VIN ö Gain(dB) = 20 ´ log ç ÷ è Vramp ø (13) Gain = 20 × Log 10 = 20 dB fp1 = (C5 + C8) 2 p ´ R6 ´ (C5 ´ C8) (14) 1 fp2 = 2p ´ R9 ´ C7 (15) Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 19 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com 1 2p ´ R6 ´ C5 1 fz2 = 2p ´ (R4 + R9 ) ´ C7 fz1 = (16) (17) Bode Plot of Converter Gain Open Loop Error Amp Gain f P1 f P2 Gain - dB f Z1 f Z2 20 log R6 (R4+R9)/(R4*R9) 20 log (R6/R4) 20 log (10) Modulator Gain Compensation Gain Closed Loop Gain f LC f ESR f - Frequency - Hz 20 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION The following guidelines are recommended for PCB layout of the TPS54362/TPS54362A device. Input Voltage, VI 8V to 28V Output Voltage, VO 3.3V ± 2% Maximum Output Current, IO-max 2.5A Transient Response 0.25A to 2.25A load step ΔVO = 5% Reset Threshold 92% of Output Voltage Overvoltage Threshold 106% of Output Voltage Undervoltage Threshold 95% of Output Voltage SELECTING THE SWITCHING FREQUENCY The user selects the switching frequency based on the minimum on-time of the internal power switch, the maximum input voltage and the minimum output voltage and the frequency shift limitations. Equation 18 must be used to find the maximum frequency for the regulator. The value of the resistor to set on the RT terminal to set this frequency can be extrapolated from Figure 17. æ VO - min ö ç ÷ VI- max ø è fsw - max = (Hz) t on- min (18) ton-min = 150ns from the DC Electrical Characteristics fsw-max = 770kHz Since the oscillator can vary 10%, decrease the frequency by 10%. Further, to keep the switching frequency outside the AM band, fsw can be selected as 400kHz. D1 J1 1 C11 + 3 R11 GND 102k 4 5 R10 GND 88.7k GND GND V_REG GND R8 R7 260k 30.1k 6 7 R12 2k 8 C2 4.7nF 9 10 BOOT NC VIN SYNC VIN LPM PH EN VREG RT COMP RSLEW VSENSE RST RST_TH CDLY OV_TH AGND SS 20 2 C3 0.1uF GND 19 V_REG 18 L1 17 22uH 1 16 V_REG GND 2 D2 R9 C12 C5 15 430pF 2.15k 14 13 V_REG C8 R6 C7 82pF 324K 360pF + 0.1uF R4 J2 C4 2 VOUT= 3.3V 220uF 1 187k IOUT= 2.5A GND R1 12 73.6k 11 C6 21 GND NC 1 1 2 220uF 2 GND V_REG 1 PAD GND TPS54362PWP 2 VIN = 8 to 28V 0.1uF U1 C1 R5 4.7nF R2 C10 3.48k 15pF 59k GND GND GND GND C9 R3 56pF 22.6k GND GND Figure 17. Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 21 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com Output Inductor Selection (LO) The minimum inductor value is calculated using Equation 20. The KIND is the coefficient that represents the amount of inductor ripple current relative to the maximum output current, using equation 19 the ripple is calculated. The inductor ripple current is filtered by the output capacitor and so the typical range of this ripple current is in the range of KIND = 0.2 to 0.3, depending on the ESR and the ripple current rating of the output capacitor. The minimum inductor value calculated is 14.5μH, choose inductor ≈ 22μH. IRipple = KIND × IO (19) IRipple = 0.2 × 2.5 = 0.5A (peak-to-peak) Calculate inductor L: (VI-max - VO ) × VO LO-min = ƒSW × IRipple × VI-max (Henries) (20) Where, fSW is the regulator’s switching frequency. IRipple = Allowable ripple current in the inductor, typically 20% of max IO The RMS and peak current flowing in Inductor is: (IRipple )2 (IO ) 2 + IL,RMS = (Am ps) 12 Inductor peak current: IRipple IL,pk = IO + 2 (21) (Amps) (22) Output Capacitor (CO) The selection of the output capacitor will determine several parameters in the operation of the converter, the modulator pole, voltage droop on the out capacitor and the output ripple. During a load step from no load to full load or changes in the input voltage, the output capacitor must hold up the output voltage above a certain level for a specified time and NOT issue a reset, until the main regulator control loop responds to the change. The minimum output capacitance required to allow sufficient droop on the output voltage with issuing a reset is determined by Equation 24. The capacitance value determines the modulator pole and the roll off frequency due to the LC output filter double pole - Equation 9. The output ripple voltage is a product of the output capacitor ESR and ripple current – Equation 26. Using Equation 23, the minimum capacitance needed to maintain desired output voltage during high to low load transition and prevent over shoot is 157μF. L ´ CO = ((I O-max 2 (VO-max ) )2 - (IO-min )2 - 2 ) (Farads) (VO-min ) (23) IO - max, is max output current IO - min is min output current The difference between the output current max to min is the worst case load step in the system. VO - max is max tolerance of regulated output voltage VO - min is the min tolerance of regulated output voltage Minimum Capacitance needed for transient load response, using Equation 24, yields 53μF. 2 ´ DIO CO > (Farads) fsw ´ DVO 22 Submit Documentation Feedback (24) Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com Minimum Capacitance needed for output voltage ripple specification, using Equation 25, yields 1.18μF. 1 1 CO > x (Farads) 8 ´ fsw æ VO-Ripple ö ç ÷ ç IRipple ÷ è ø (25) The most critical condition based on the calculations above indicates that the output capacitance has to be a minimum of 157μF to keep the output voltage in regulation during load transients. Additional capacitance de-ratings for temperature, aging and dc bias has to be factored, and so a value of 220μF with ESR calculated using Equation 26 of less than 100mΩ should be used on the output stage. Maximum ESR of the out capacitor based on output ripple voltage specification. VO-Ripple RESR < (Ohms) IRipple (26) Output capacitor root mean square (RMS) ripple current. This is to prevent excess heating or failure due to high ripple currents. This parameter is sometimes specified by the manufacturers. ( VO x VI_max - VO IO_RMS = ) (Apms) 12 x VI_max x LO x fsw (27) FLYBACK SCHOTTKY DIODE The TPS54362/TPS54362A requires an external Schottky diode connected between the PH and power ground termination. The absolute voltage at PH pin should not go beyond the values mentioned in Absolute Maximum Ratings table on page 2 of this document. The schottky diode conducts the output current during the off state of the internal power switch. This schottky diode must have a reverse breakdown higher then the maximum input voltage of the application. A schottky diode is selected for its lower forward voltage. The schottky diode is selected based on the appropriate power rating, which factors in the DC conduction losses and the AC losses due to the high switching frequencies; this is determined by Equation 28. Pdiode ( ) æ VI_max - VO x IO x V fd = ç ç VI- max è ö ÷+ ÷ ø æ V- V ç I fd ç ç è ( 2 ) x fsw x CJ ö÷ ÷ (Watts) 2 ÷ ø (28) Where: Vfd = forward conducting voltage of Schottky diode Cj = junction capacitance of the Schottky diode The recommended part numbers are PDS360 and SBR8U60P5. INPUT CAPACITOR, CI The requires an input ceramic de-coupling capacitor type X5R or X7R and bulk capacitance to minimize input ripple voltage. The dc voltage rating of this input capacitance must be greater than the maximum input voltage. The capacitor must have an input ripple current rating higher than the maximum input ripple current of the converter for the application; this is determined by Equation 29. The input capacitors for power regulators are chosen to have reasonable capacitance to volume ratio and fairly stable over temperature. The value of the input capacitance also determines the input ripple voltage of the regulator, shown by Equation 30. II_RMS IO x ( VI_min - VO VO x VI_min VI_min ) (Amps) (29) I x 0.25 DVI = O-max (Volts) CI x fsw (30) Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 23 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com OUTPUT VOLTAGE AND FEEDBACK RESISTOR SELECTION In the design example, 187kΩ was selected for R4, using Equation 1, R4 is calculated as 59kΩ. To minimize the effect of leakage current on the VSENSE terminal, the current flowing through the feedback network should be greater than 5μA in order to maintain output accuracy. Higher resistor values help improve the converter efficiency at low output currents, but may introduce noise immunity problems. OVERVOLTAGE RESISTOR SELECTION Using Equation 8, the value of R3 is determined to set the overvoltage threshold at 1.06 × 3.3V. The total resistor network from VReg output to ground is approximately 100kΩ (this is R1 + R2 +R3). Then R3 is calculated to be 22.87kΩ. Use the nearest standard value, which is 22.6kΩ. A noise decoupling capacitor may be required on this terminal to ensure proper operation; the value chosen for this design is 56pF. RESET THRESHOLD RESISTOR SELECTION Then using Equation 7 the value of R2 + R3 is calculated, and then knowing R3 from the OV_TH setting, R2 is determined. The value of R2 + R3 yielded 26.35kΩ, which means R2 is approximately 3.48kΩ. This will set the reset threshold at 0.92 × 3.3V. A noise decoupling capacitor may be required on this terminal to ensure proper operation; the value chosen for this design is 15pF. R1 is determined to be 73.6kΩ. LOW POWER MODE THRESHOLD To obtain an approximation of the output load current at which the converter is operating in discontinuous mode, use Equation 31. The values used in the equation for minimum and maximum input voltage will affect the duty cycle and the overall discontinuous mode load current. With a maximum input voltage of 28V, the output load current for DCM is 165.8mA, and for minimum input voltage of 8V the DCM mode load current is 111.7mA. These are nominal values and other factors are not taken into consideration like external component variations with temperature and aging. (1 - D ) ´ VO IL _DISCONT = IL_LPM = (Amperes) (with ± 30% hysteresis) 2 ´ ¦ SW ´ L (31) UNDERVOLTAGE THRESHOLD FOR LOW POWER MODE AND LOAD TRANSIENT OPERATION This threshold is set above the reset threshold to ensure the regulator operates within the specified tolerances during output load transient of low load to high load and during discontinuous conduction mode. Using Equation 6 the typical voltage threshold is determined. In this design, the value for this threshold is 0.95 × 3.3V. SOFTSTART CAPACITOR The soft start capacitor determines the minimum time to reach the desired output voltage during a power up cycle. This is useful when a load requires a controlled voltage slew rate, and helps to limit the current draw from the input voltage supply line. Equation 4 has to be satisfied in addition to the other conditions stated in the soft start section of this document(not applicable for TPS54362A). In this design, a 4.7nF capacitor is required to meet these criteria. If the buck converter starts up with output shorted to ground, TPS54362A and minimum 150nF Css are required. BOOTSTRAP CAPACITOR SELECTION A 0.1μF ceramic capacitor must be connected between the PH and BOOT terminals for the converter to operate and regulate the desired output voltage. It is recommended to use a capacitor with X5R or better grade dielectric material, and the voltage rating on this capacitor of at least 25V to allow for derating. 24 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com COMPENSATION Guidelines for Compensation Components 1 Make the two zeroes close to the double pole (LC), e.g fz1 ≈ fz2 ≈ 2 x p LCO 1. Make first zero below the filter double pole (approx 50% to 75% of fLC) 2. Make second zero at filter double pole (fLC) Make the two poles above the cross-over frequency fc, 1. Make first pole at the ESR frequency (fESR) 2. Make the second pole at 0.5 the switching frequency (0.5 × fsw) Select R4 = 187kW (R4 ´ 0.8 ) R5 = (VO - 0.8) (32) fc ´ Vramp ´ R4 R6 = (fLC ´ VI) (33) Calculate C5 based on placing a zero at 50% to 75% of the output filter double pole frequency. 1 C5 = p ´ R6 ´ fLC (34) Calculate C8 by placing the first pole at the ESR zero frequency. C5 C8 = (2 p ´ R6 ´ C5 ´ fESR - 1) (35) Set the second pole at 0.5 the switching frequency and also set the second zero at the output filter double pole frequency. R4 R9 = æ æ fsw ö ö çç ç ÷ - 1÷÷ è è 2 ´ fLC ø ø (36) 1 C7 = p ´ R9 ´ fsw (37) Calculate the Loop Compensation DC modulator gain (Amod) = 8 /Vr Vr = 0.8 Amod (dB) = 20 log (10) = 20 dB Output filter due to LCO poles and CO ESR zeros from Equation 9 and Equation 10. fLC = 2.3 kHz for LCO = 22µH, CO = 220µF fESR = 7.23 kHz for CO = 220µF, ESR = 100mΩ Choose R4 = 187kΩ Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 25 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com The poles and zeros for a type III network are calculated using equations Equation 32 to Equation 37. R5 = 59.8k (use standard value 59k) R6 = 326.9k (use standard value 324k) C5 = 425.5pF (use standard value 430pF) C8 = 79.9pF (use standard value 43pF) R9 = 2.16k (use standard value 2.15K) C7 = 367.7pF (use standard value 360pF) The poles and zeros based on these compensation values can be calculated using Equation 14 to Equation 17. Power Dissipation The power dissipation losses are applicable for continuous conduction mode operation (CCM) æV ö PCON = IO2 × RDS(on) ´ ç O ÷ (Conduction losses) è VI ø PSW = 1/2 ´ VI ´ IO ´ (tr + t f ) ´ fSW (38) (Switching losses) (39) -9 PGate = Vdrive ´ Qg ´ fsw (Gate drive losses) where Qg = 1 ´ 10 (nC) (40) PIC = VI ´ Iq-normal (Supply losses) (41) PTotal = PCON + PSW + PGate + PIC (Watts) (42) Where: VO = Output voltage VI = Input voltage IO = Output current tr = FET switching rise time (tr max = 40ns) tf = FET switching fall time Vdrive = FET gate drive voltage (typically Vdrive = 6V and Vdrive max = 8V) fsw = Switching frequency For given operating ambient temperature TA TJ = TAmb + Rth ´ PTotal (43) For a given max junction temperature TJ-Max = 150°C TAmb-Max = TJ-Max - Rth ´ PTotal (44) Where: PTotal = Total power dissipation (Watts) TAmb = Ambient Temperature in °C TJ = Junction Temperature in °C TAmb-Max = Maximum Ambient Temperature in °C TJ-Max = Maximum junction temperature in °C Rth = Thermal resistance of package in (°C/W) Other factors NOT included in the information above which affect the overall efficiency and power losses are Inductor ac and dc losses. Trace resistance and losses associated with the copper trace routing connection Flyback catch diode The output current rating for the regulator may have to be derated for ambient temperatures above 85°C. The de-rate value will depend on calculated worst case power dissipation and the thermal management implementation in the application. 26 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com Power Dissipation (W) versus Ambient Temperature (C) 4.00 Power Dissipation (W) 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperture (C) Figure 18. Power Dissipation De-Rating LAYOUT The following guidelines are recommended for PCB layout of the TPS54362/TPS54362A device. INDUCTOR Use a low EMI inductor with a ferrite type shielded core. Other types of inductors may be used; however, they must be low EMI characteristics and located away from the low power traces and components in the circuit. INPUT FILTER CAPACITORS Input ceramic filter capacitors should be located in the close proximity of the VIN terminal. Surface mount capacitors are recommended to minimize lead length and reduce noise coupling. FEEDBACK Route the feedback trace such that there is minimum interaction with any noise sources associated with the switching components. Recommended practice is to ensure the inductor is placed away from the feedback trace to prevent EMI noise source. TRACES AND GROUND PLANE All power (high current) traces should be thick and short as possible. The inductor and output capacitors should be as close to each other as possible. This will reduce EMI radiated by the power traces due to high switching currents. In a two sided PCB, it is recommended to have ground planes on both sides of the PCB to help reduce noise and ground loop errors. The ground connection for the input and output capacitors and IC ground should be connected to this ground plane. In a multilayer PCB, the ground plane is used to separate the power plane (high switching currents and components are placed) from the signal plane (where the feedback trace and components are) for improved performance. Also, arrange the components such that the switching current loops curl in the same direction. Place the high current components such that during conduction the current path is in the same direction. This will prevent magnetic field reversal caused by the traces between the two half cycles, helping to reduce radiated EMI. Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 27 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com Output Capacitor Topside Supply Area Input Capacitor Ground Plane Catch Diode NC BOOT NC VIN SYNC LPM Output Inductor VIN PH EN VReg RT COMP Rslew VSENSE RST RST_TH Cdly OV_TH GND Compensation Network Supervisor Network Resistor Divider Signal via to Ground Plane SS Topside Ground Area Thermal Via Signal Via Figure 19. PCB Layout Example 28 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 TPS54362-Q1, TPS54362A-Q1 SLVS845D – MARCH 2009 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY Changes from Revision C (March 2010) to Revision D • Page Added TPS54362A-Q1 device .............................................................................................................................................. 1 Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s) :TPS54362-Q1 TPS54362A-Q1 Submit Documentation Feedback 29 PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS54362AQPWPRQ1 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS54362QPWPRQ1 NRND HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS54362AQPWPRQ1 HTSSOP PWP 20 2000 330.0 16.4 TPS54362QPWPRQ1 HTSSOP PWP 20 2000 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54362AQPWPRQ1 HTSSOP PWP 20 2000 346.0 346.0 33.0 TPS54362QPWPRQ1 HTSSOP PWP 20 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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