OPA 2132 OPA 132 OPA 132 OPA132 OPA2132 OPA4132 OPA 4132 OPA 2132 OPA 4132 SBOS054A – JANUARY 1995 – REVISED JUNE 2004 High-Speed FET-INPUT OPERATIONAL AMPLIFIERS FEATURES OPA132 ● FET INPUT: IB = 50pA max ● WIDE BANDWIDTH: 8MHz Offset Trim 1 8 Offset Trim ● HIGH SLEW RATE: 20V/µs ● LOW NOISE: 8nV/√Hz (1kHz) –In 2 7 V+ +In 3 6 Output ● LOW DISTORTION: 0.00008% V– 4 5 NC 8 V+ 7 Out B 6 –In B 5 +In B ● HIGH OPEN-LOOP GAIN: 130dB (600Ω load) 8-Pin DIP, SO-8 ● WIDE SUPPLY RANGE: ±2.5 to ±18V ● LOW OFFSET VOLTAGE: 500µV max ● SINGLE, DUAL, AND QUAD VERSIONS OPA2132 DESCRIPTION Out A The OPA132 series of FET-input op amps provides highspeed and excellent dc performance. The combination of high slew rate and wide bandwidth provide fast settling time. Single, dual, and quad versions have identical specifications for maximum design flexibility. High performance grades are available in the single and dual versions. All are ideal for general-purpose, audio, data acquisition and communications applications, especially where high source impedance is encountered. OPA132 op amps are easy to use and free from phase inversion and overload problems often found in common FET-input op amps. Input cascode circuitry provides excellent common-mode rejection and maintains low input bias current over its wide input voltage range. OPA132 series op amps are stable in unity gain and provide excellent dynamic behavior over a wide range of load conditions, including high load capacitance. Dual and quad versions feature completely independent circuitry for lowest crosstalk and freedom from interaction, even when overdriven or overloaded. Single and dual versions are available in 8-pin DIP and SO-8 surface-mount packages. Quad is available in 14-pin DIP and SO-14 surface-mount packages. All are specified for –40°C to +85°C operation. –In A 1 A 2 +In A 3 V– 4 B 8-Pin DIP, SO-8 OPA4132 Out A 1 –In A 2 A 14 Out D 13 –In D D +In A 3 12 +In D V+ 4 11 V– +In B 5 10 +In C B C –In B 6 9 –In C Out B 7 8 Out C 14-Pin DIP SO-14 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1995-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Supply Voltage, V+ to V– .................................................................... 36V Input Voltage ..................................................... (V–) –0.7V to (V+) +0.7V Output Short-Circuit(1) .............................................................. Continuous Operating Temperature .................................................. –40°C to +125°C Storage Temperature ..................................................... –55°C to +125°C Junction Temperature ...................................................................... 150°C Lead Temperature (soldering, 10s) ................................................. 300°C NOTE: (1) Short-circuit to ground, one amplifier per package. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. 2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. OPA132, 2132, 4132 www.ti.com SBOS054A SPECIFICATIONS At TA = +25°C, VS = ±15V, unless otherwise noted. OPA132PA, UA OPA2132PA, UA OPA4132PA, UA OPA132P, U OPA2132P, U PARAMETER OFFSET VOLTAGE Input Offset Voltage vs Temperature(1) vs Power Supply Channel Separation (dual and quad) CONDITION MIN Operating Temperature Range VS = ±2.5V to ±18V RL = 2kΩ INPUT BIAS CURRENT Input Bias Current(2) vs Temperature Input Offset Current(2) VCM = 0V ±0.25 ±2 5 0.2 ±0.5 ±10 15 MIN VCM = –12.5V to +12.5V INPUT IMPEDANCE Differential Common-Mode VCM = –12.5V to +12.5V (V–)+2.5 96 110 110 110 G = –1, 10V Step, CL = 100pF G = –1, 10V Step, CL = 100pF G = ±1 1kHz, G = 1, VO = 3.5Vrms RL = 2kΩ RL = 600Ω POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current (per amplifier) (V+)–2.5 ✻ 86 RL = 10kΩ ±2.5 IO = 0 TEMPERATURE RANGE Operating Range Storage Thermal Resistance, θJA 8-Pin DIP SO-8 Surface-Mount 14-Pin DIP SO-14 Surface-Mount ±0.5 ✻ ✻ ✻ ±2 ✻ 30 mV µV/°C µV/V µV/V ✻ ✻ ✻ ✻ pA ✻ pA ✻ 94 nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA/√Hz ✻ V dB ✻ 120 120 dB dB dB 8 ±20 0.7 1 0.5 ✻ ✻ ✻ ✻ ✻ MHz V/µs µs µs µs 0.00008 0.00009 ✻ ✻ % % ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V V V V V mA 120 126 130 104 104 104 ✻ ✻ ✻ ✻ ✻ ✻ (V+)–0.9 (V–)+0.3 (V+)–1.2 (V–)+0.9 (V+)–2.0 (V–)+1.9 ±40 See Typical Curve RL = 600Ω UNITS Ω || pF Ω || pF (V+)–1.2 (V–)+0.5 (V+)–1.5 (V–)+1.2 (V+)–2.5 (V–)+2.2 RL = 2kΩ MAX ✻ ✻ 1013 || 2 1013 || 6 RL = 10kΩ, VO = –14.5V to +13.8V RL = 2kΩ, VO = –13.8V to +13.5V RL = 600Ω, VO = –12.8V to +12.5V OUTPUT Voltage Output, Positive Negative Positive Negative Positive Negative Short-Circuit Current Capacitive Load Drive (Stable Operation) ±13 100 TYP ✻ ✻ ✻ ✻ ✻ 23 10 8 8 3 INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time: 0.1% 0.01% Overload Recovery Time Total Harmonic Distortion + Noise MAX +5 ±50 See Typical Curve ±2 ±50 VCM = 0V NOISE Input Voltage Noise Noise Density, f = 10Hz f = 100Hz f = 1kHz f = 10kHz Current Noise Density, f = 1kHz OPEN-LOOP GAIN Open-Loop Voltage Gain TYP ±15 ±4 –40 –40 100 150 80 110 ✻ ±18 ±4.8 ✻ +85 +125 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V mA ✻ ✻ °C °C °C/W °C/W °C/W °C/W ✻ Specifications same as OPA132P, OPA132U. NOTES: (1) Guaranteed by wafer test. (2) High-speed test at TJ = 25°C. OPA132, 2132, 4132 SBOS054A www.ti.com 3 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±15V, RL = 2kΩ, unless otherwise noted. POWER SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY OPEN-LOOP GAIN/PHASE vs FREQUENCY 160 0 120 140 100 –PSR 100 φ 80 –90 60 40 –135 PSR, CMR (dB) –45 Phase Shift (°) Voltage Gain (dB) 120 80 60 40 +PSR G 20 CMR 20 0 –180 –20 0 0.1 1 10 100 1k 10k 100k 1M 10 10M 100 1k Frequency (Hz) 10k 100k 1M Frequency (Hz) INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY 160 1k Channel Separation (dB) Current Noise (fA/√Hz) Voltage Noise (nV/√Hz) RL = ∞ 100 Voltage Noise 10 140 120 100 Current Noise 1 80 1 10 100 1k 10k 100k 100 1M 10k 100k Frequency (Hz) INPUT BIAS CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs INPUT COMMON-MODE VOLTAGE 10 High Speed Test Warmed Up 9 Input Bias Current (pA) 10k Input Bias Current (pA) 1k Frequency (Hz) 100k 1k Quad 100 Dual 10 1 Single High Speed Test 8 7 6 5 4 3 2 1 0 0.1 –75 –50 –25 0 25 50 75 100 –15 125 –10 –5 0 5 10 15 Common-Mode Voltage (V) Ambient Temperature (°C) 4 RL = 2kΩ Dual and quad devices. G = 1, all channels. Quad measured channel A to D or B to C—other combinations yield improved rejection. OPA132, 2132, 4132 www.ti.com SBOS054A TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VS = ±15V, RL = 2kΩ, unless otherwise noted. Open-Loop Gain 110 PSR 100 CMR 60 4.2 50 4.1 –75 –50 –25 0 25 50 75 100 4.0 30 ±IQ 20 3.9 125 10 –75 –50 –25 0 25 50 75 Ambient Temperature (°C) Ambient Temperature (°C) OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION 12 100 125 12 Typical production distribution of packaged units. Single, dual and quad units included. Typical production distribution of packaged units. Single, dual and quad units included. 10 Percent of Amplifiers (%) 10 8 6 4 2 0 8 6 4 2 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.0 1400 1200 1000 800 600 400 0 200 –200 –400 –600 –800 –1000 –1200 –1400 0 Offset Voltage Drift (µV/°C) Offset Voltage (µV) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY MAXIMUM OUTPUT VOLTAGE vs FREQUENCY 0.01 30 RL 2kΩ 600Ω 0.001 G = +10 0.0001 G = +1 20 10 VS = ±5V VO = 3.5Vrms 0.00001 VS = ±2.5V 0 10 100 1k 10k 100k Frequency (Hz) 10k 100k 1M 10M Frequency (Hz) OPA132, 2132, 4132 SBOS054A Maximum output voltage without slew-rate induced distortion VS = ±15V Output Voltage (Vp-p) THD+Noise (%) 40 ±ISC 3.8 90 Percent of Amplifiers (%) 4.3 0.5 AOL, CMR, PSR (dB) 120 Quiescent Current Per Amp (mA) 130 Short-Circuit Current (mA) QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE AOL, CMR, PSR vs TEMPERATURE www.ti.com 5 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VS = ±15V, RL = 2kΩ, unless otherwise noted. LARGE-SIGNAL STEP RESPONSE G = 1, CL = 100pF 5V/div 50mV/div SMALL-SIGNAL STEP RESPONSE G = 1, CL = 100pF 200ns/div 1µs/div SETTLING TIME vs CLOSED-LOOP GAIN SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 100 60 0.01% 10 Overshoot (%) Settling Time (µs) 50 FPO 0.1% 1 G = +1 40 G = –1 30 20 G = ±10 10 0.1 ±1 ±10 ±100 0 100pF ±1000 1nF Closed-Loop Gain (V/V) 10nF Load Capacitance OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 15 VIN = 15V Output Voltage Swing (V) 14 –55°C 13 12 25°C 25°C 125°C 85°C 11 10 –10 85°C 125°C –11 –12 25°C –13 –55°C –14 VIN = –15V –15 0 10 20 30 40 50 60 Output Current (mA) 6 OPA132, 2132, 4132 www.ti.com SBOS054A APPLICATIONS INFORMATION OPA132 series op amps are unity-gain stable and suitable for a wide range of general-purpose applications. Power supply pins should be bypassed with 10nF ceramic capacitors or larger. OPA132 op amps are free from unexpected output phasereversal common with FET op amps. Many FET-input op amps exhibit phase-reversal of the output when the input common-mode voltage range is exceeded. This can occur in voltage-follower circuits, causing serious problems in control loop applications. OPA132 series op amps are free from this undesirable behavior. All circuitry is completely independent in dual and quad versions, assuring normal behavior when one amplifier in a package is overdriven or short-circuited. OPERATING VOLTAGE OPA132 series op amps operate with power supplies from ±2.5V to ±18V with excellent performance. Although specifications are production tested with ±15V supplies, most behavior remains unchanged throughout the full operating voltage range. Parameters which vary significantly with operating voltage are shown in the typical performance curves. OFFSET VOLTAGE TRIM Offset voltage of OPA132 series amplifiers is laser trimmed and usually requires no user adjustment. The OPA132 (single op amp version) provides offset voltage trim connections on pins 1 and 8. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure 1. This adjustment should be used only to null the offset of the op amp, not to adjust system offset or offset produced by the signal source. Nulling offset could degrade the offset voltage drift behavior of the op amp. While it is not possible to predict the exact change in drift, the effect is usually small. V+ Trim Range: ±4mV typ 10nF 100kΩ 7 8 3 10nF OPA132 4 6 OPA132 single op amp only. Use offset adjust pins only to null offset voltage of op amp—see text. V– FIGURE 1. OPA132 Offset Voltage Trim Circuit. INPUT BIAS CURRENT The FET-inputs of the OPA132 series provide very low input bias current and cause negligible errors in most applications. For applications where low input bias current is crucial, junction temperature rise should be minimized. The input bias current of FET-input op amps increases with temperature as shown in the typical performance curve “Input Bias Current vs Temperature.” The OPA132 series may be operated at reduced power supply voltage to minimize power dissipation and temperature rise. Using ±3V supplies reduces power dissipation to one-fifth that at ±15V. The dual and quad versions have higher total power dissipation than the single, leading to higher junction temperature. Thus, a warmed-up quad will have higher input bias current than a warmed-up single. Furthermore, an SOIC will generally have higher junction temperature than a DIP at the same ambient temperature because of a larger θJA. Refer to the specifications table. Circuit board layout can also help minimize junction temperature rise. Temperature rise can be minimized by soldering the devices to the circuit board rather than using a socket. Wide copper traces will also help dissipate the heat by acting as an additional heat sink. Input stage cascode circuitry assures that the input bias current remains virtually unchanged throughout the full input common-mode range of the OPA132 series. See the typical performance curve “Input Bias Current vs CommonMode Voltage.” OPA132, 2132, 4132 SBOS054A 1 2 www.ti.com 7 PACKAGE OPTION ADDENDUM www.ti.com 1-Jul-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS OPA132P OBSOLETE PDIP P 8 OPA132P1 OBSOLETE PDIP P 8 OPA132PA OBSOLETE PDIP P 8 OPA132PA2 OBSOLETE PDIP P 8 PACKAGE QTY OPA132U ACTIVE SOIC D 8 100 OPA132U/2K5 ACTIVE SOIC D 8 2500 OPA132U1 OBSOLETE PDIP P 8 OPA132UA ACTIVE SOIC D 8 100 OPA132UA/2K5 ACTIVE SOIC D 8 2500 OPA132UA2 OBSOLETE PDIP P 8 OPA2132P ACTIVE PDIP P 8 OPA2132PA ACTIVE PDIP P 8 50 50 OPA2132U ACTIVE SOIC D 8 100 OPA2132U/2K5 ACTIVE SOIC D 8 2500 OPA2132UA ACTIVE SOIC D 8 100 OPA2132UA/2K5 ACTIVE SOIC D 8 2500 OPA4132PA OBSOLETE PDIP N 14 OPA4132UA ACTIVE SOIC D 14 58 OPA4132UA/2K5 ACTIVE SOIC D 14 2500 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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