SN54LVT16646, SN74LVT16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS149C – JULY 1994 – REVISED JULY 1995 D D D D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation Members of the Texas Instruments Widebus Family Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors Support Live Insertion Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings SN54LVT16646 . . . WD PACKAGE SN74LVT16646 . . . DGG OR DL PACKAGE (TOP VIEW) 1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE description The ’LVT16646 are 16-bit bus transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ′LVT16646. Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. The direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVT16646, SN74LVT16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS149C – JULY 1994 – REVISED JULY 1995 description (continued) When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT16646 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54LVT16646 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74LVT16646 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS DATA I/Os OE DIR CLKAB CLKBA SAB SBA A1 THRU A8 X X ↑ X X X Input B1 THRU B8 Unspecified† OPERATION OR FUNCTION X X X ↑ X X Unspecified† Input Store A, B unspecified† Store B, A unspecified† H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus † The data output functions may be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVT16646, SN74LVT16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS OE L DIR L CLKAB CLKBA X X SAB X BUS B BUS A BUS A BUS B SCBS149C – JULY 1994 – REVISED JULY 1995 SBA L OE L DIR H DIR X X H X X X CLKAB CLKBA ↑ X ↑ X ↑ ↑ SAB L SBA X BUS B BUS A BUS A OE CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A CLKAB X SAB SBA X X X X X X STORAGE FROM A, B, OR A AND B OE L L DIR L H CLKAB X H or L CLKBA H or L X SAB X H SBA H X TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVT16646, SN74LVT16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS149C – JULY 1994 – REVISED JULY 1995 logic symbol† 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 1A1 56 1 55 54 2 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 3 G7 29 28 30 31 27 26 G10 10 EN8 [BA] 10 EN9 [AB] C11 G12 C13 G14 ≥1 5 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 7 1 2A3 2A4 2A5 2A6 2A7 2A8 ≥1 7 51 49 9 48 10 47 12 45 13 44 14 43 15 16 ≥1 8 1 14 12 11D 42 ≥1 1B3 1B4 1B5 1B6 1B7 1B8 2B1 9 41 17 40 19 38 20 37 21 36 23 34 24 33 POST OFFICE BOX 655303 1B2 12 1 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 4 1B1 2 8 13D 14 2A2 52 5 1 6D 6 4D 5 • DALLAS, TEXAS 75265 2B2 2B3 2B4 2B5 2B6 2B7 2B8 SN54LVT16646, SN74LVT16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS149C – JULY 1994 – REVISED JULY 1995 logic diagram (positive logic) 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 56 1 55 54 2 3 One of Eight Channels 1D C1 1A1 5 52 1B1 1D C1 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB To Seven Other Channels 29 28 30 31 27 26 One of Eight Channels 1D C1 2A1 15 42 2B1 1D C1 To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVT16646, SN74LVT16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS149C – JULY 1994 – REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . – 0.5 V to 7 V Current into any output in the low state, IO: SN54LVT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVT16646 . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVT16646 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) SN54LVT16646 SN74LVT16646 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH IOL High-level output current – 24 – 32 mA Low-level output current 48 64 mA ∆t /∆v Input transition rise or fall rate 10 ns / V 85 °C High-level input voltage 2 Outputs enabled TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 10 – 55 125 – 40 V V SN54LVT16646, SN74LVT16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS149C – JULY 1994 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54LVT16646 TYP† MAX TEST CONDITIONS VCC = 2.7 V, VCC = MIN to MAX‡, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = – 8 mA IOH = – 24 mA VCC = 3 V VCC = 2 2.7 7V VOL VCC = 3 V VCC = 3.6 V, VCC = 0 or MAX‡, II VCC = 3.6 V Ioff VCC = 0, II(hold) I(h ld) VCC = 3 V IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, MIN –1.2 VCC – 0.2 2.4 VCC = 3.6 3 6 V, V VI = VCC or GND –1.2 VCC – 0.2 2.4 IOH = – 32 mA IOL = 100 µA 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 V 0.55 0.55 Control inputs A or B ports§ VI or VO = 0 to 4.5 V VI = 0.8 V A or B ports VI = 2 V VO = 3 V Ci VI = 3 V or 0 VO = 3 V or 0 20 20 5 5 – 10 – 10 75 75 –75 3.5 µA µA µA 1 µA –1 –1 µA 0.12 0.12 1 Outputs disabled VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND ±1 10 –75 Outputs low ∆ICC¶ ±1 10 ± 100 VO = 0.5 V IO = 0, 0 V 2 0.2 IOL = 64 mA VI = VCC or GND UNIT V 2 Outputs high ICC SN74LVT16646 TYP† MAX MIN 5 5 0.12 0.12 0.2 0.2 mA mA 3.5 pF Cio 12 12 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § Unused pins at VCC or GND ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVT16646, SN74LVT16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS149C – JULY 1994 – REVISED JULY 1995 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVT16646 VCC = 3.3 V ± 0.3 V fclock tw MIN MAX 0 150 Clock frequency Pulse duration, CLK high or low tsu Setup time,, A or B before CLKAB↑ or CLKBA↑ th Hold time, A or B after CLKAB↑ or CLKBA↑ SN74LVT16646 VCC = 2.7 V MIN MAX 0 150 VCC = 3.3 V ± 0.3 V MIN MAX 0 150 VCC = 2.7 V MIN MAX 0 150 3.3 3.3 3.3 3.3 Data high 1.3 1.4 1.3 1.4 Data low 2.4 3 2.4 3 Data high 0.5 0 0.5 0 Data low 0.6 0.5 0.5 0.5 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) SN54LVT16646 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ SN74LVT16646 VCC = 2.7 V MAX MIN MAX 150 CLKBA or CLKAB A or B A or B B or A SBA or SAB‡ A or B OE A or B OE A or B DIR A or B VCC = 3.3 V ± 0.3 V MIN TYP† MAX VCC = 2.7 V MIN MHz 1.8 6 6.9 1.8 3.8 5.7 6.7 2.1 5.9 6.6 2.1 3.9 5.7 6.5 1.3 4.9 5.6 1.3 3 4.7 5.4 1 4.8 5.8 1 3.1 4.7 5.6 1.4 6.4 7.4 1.4 4 6.2 7.2 1.4 6.4 7.4 1.4 4.3 6.2 7.2 1 5.7 7.4 1 3 5.4 6.4 1 6.5 7.5 1 3.1 5.6 6.5 2.3 6.7 7.1 2.3 4.6 6.5 6.9 2.2 6 6.5 2.2 4.5 5.8 5.9 1 5.9 7.7 1 3.3 5.7 6.7 1.2 5.9 7.3 1.2 3.5 5.8 6.7 1.7 7.3 8.5 1.7 4.7 7.2 DIR A or B tPLZ 1.5 7.8 7.4 1.5 4.9 6.6 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ These parameters are measured with the internal output state of the storage register opposite to that of the bus input. 8 MAX 150 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 8.3 7.2 ns ns ns ns ns ns ns SN54LVT16646, SN74LVT16646 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS149C – JULY 1994 – REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V th 2.7 V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Input 1.5 V 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 6 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 2.7 V Output Control 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated