54AC11175, 74AC11175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCAS090 – DECEMBER 1989 – REVISED APRIL 1993
•
•
•
•
•
•
54AC11175 . . . J PACKAGE
74AC11175 . . . DW or N PACKAGE
(TOP VIEW)
Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
1Q
2Q
2Q
GND
GND
GND
GND
3Q
3Q
4Q
t
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1Q
CLR
1D
2D
VCC
VCC
3D
4D
CLK
4Q
54AC11014 . . . FK PACKAGE
description
(TOP VIEW)
1D
2D
VCC
VCC
3D
These positive-edge-triggered flipflops implement
D-type flip-flop logic with a direct clear input.
Information at the D inputs that meets the setup
time requirements is transferred to the outputs on
the positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock input is at
either the high or low level, the D input signal has
no effect at the output.
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4D
CLK
4Q
4Q
3Q
GND
GND
CND
GND
3Q
CLR
1Q
1Q
2Q
2Q
The 54AC11175 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The 74AC11175 is characterized for
operation from – 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
OUTPUTS
INPUTS
CLR
CLK
D
Q
Q
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
54AC11175, 74AC11175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCAS090 – DECEMBER 1989 – REVISED APRIL 1993
logic symbol†
19
CLR
12
CLK
1D
2D
18
17
logic diagram (positive logic)
CLR
R
C1
20
1D
1
2
3
8
3D
14
9
10
4D
19
13
11
1Q
1Q
CLK 12
1D
18
20
1Q
C1
2Q
2Q
3Q
3Q
1D
2D
17
R
1
1D
2
1Q
2Q
C1
4Q
R
3
1D
8
C1
R
9
2Q
4Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the DW, J and N packages.
3D
14
13
4D
1D
10
3Q
3Q
4Q
C1
R
11
4Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
}Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
54AC11175, 74AC11175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCAS090 – DECEMBER 1989 – REVISED APRIL 1993
recommended operating conditions
54AC11175
VCC
NOM
MAX
3
5
5.5
Supply voltage
VIH
VCC = 3 V
VCC = 4.5 V
High-level input voltage
VCC = 5.5 V
VCC = 3 V
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
VI
VO
3
5
5.5
3.15
3.85
UNIT
V
V
3.85
0.9
0.9
VCC = 4.5 V
VCC = 5.5 V
1.35
1.35
1.65
1.65
VCC = 3 V
VCC = 4.5 V
–4
–4
– 24
– 24
VCC = 5.5 V
– 24
– 24
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
12
12
24
24
24
24
0
Operating free-air temperature
MAX
3.15
0
Input transition rise or fall rate
NOM
2.1
Output voltage
TA
MIN
2.1
Input voltage
Dt /Dv
74AC11175
MIN
VCC
VCC
0
0
VCC
VCC
V
mA
mA
V
V
0
10
0
10
ns/ V
– 55
125
– 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = – 50 mA
VOH
IOH = – 4 mA
IOH = – 24 mA
IOH = – 50 mA{
TA = 25°C
MIN
TYP
54AC11175
74AC11175
MIN
MIN
UNIT
MAX
MAX
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
5.5 V
IOH = – 75 mA{
IOL = 12 mA
IOL = 24 mA
V
3.85
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
IOL = 50 mA
5.5 V
IOL = 75 mA{
5.5 V
II
VI = VCC or GND
5.5 V
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
IO = 0
MAX
3.85
5.5V
IOL = 50 mA
VOL
VCC
1.65
1.65
± 0.1
±1
±1
8
160
80
5.5 V
5V
V
4
mA
mA
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–3
54AC11175, 74AC11175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCAS090 – DECEMBER 1989 – REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
TA = 25°C
54AC11175
74AC11175
MIN
MAX
MIN
MAX
MIN
MAX
0
90
0
90
0
90
CLR low
5.5
5.5
5.5
CLK high or low
5.5
5.5
5.5
Data
8
8
8
CLR inactive
8
8
8
0.5
0.5
0.5
UNIT
MHz
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
TA = 25°C
54AC11175
74AC11175
MIN
MAX
MIN
MAX
MIN
MAX
0
125
0
125
0
125
CLR low
4
4
4
CLK high or low
4
4
4
Data
5.5
5.5
5.5
CLR inactive
5.5
5.5
5.5
0.5
0.5
0.5
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
54AC11175
74AC11175
MIN
MAX
MIN
2.6
9.9
2.6
9.3
8.7
2.6
9.9
2.6
9.3
10
11.6
2.5
13
2.5
12.4
10
11.6
2.5
13
2.5
12.4
2.4
6.8
8.7
2.4
9.4
2.4
9.1
2.4
6.8
8.7
2.4
9.4
2.4
9.1
Any Q
1.7
9.4
11.7
1.7
13
1.7
12.5
Any Q
1.7
9.4
11.7
1.7
13
1.7
12.5
MIN
90
120
Any Q
2.6
7
8.7
Any Q
2.6
7
Any Q
2.5
Any Q
2.5
Any Q
Any Q
fmax
tPLH
CLR
tPHL
CLR
tPLH
CLK
tPHL
CLK
TA = 25°C
TYP
MAX
TO
(OUTPUT)
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
90
MAX
90
UNIT
MHz
ns
ns
ns
ns
54AC11175, 74AC11175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCAS090 – DECEMBER 1989 – REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
fmax
tPLH
CLR
tPHL
CLR
tPLH
CLK
tPHL
CLK
MIN
TA = 25°C
TYP
MAX
54AC11175
74AC11175
MIN
MIN
MAX
125
MAX
125
150
Any Q
2.2
4.5
6.3
2.2
7.1
125
2.2
6.8
Any Q
2.2
4.5
6.3
2.2
7.1
2.2
6.8
Any Q
2.4
6.7
8.5
2.4
9.7
2.4
9.3
Any Q
2.4
6.7
8.5
2.4
9.7
2.4
9.3
Any Q
2.2
4.5
6.3
2.2
7.2
2.2
6.9
Any Q
2.2
4.5
6.3
2.2
7.2
2.2
6.9
Any Q
1.9
6.4
8.5
1.9
9.7
1.9
9.3
Any Q
1.9
6.4
8.5
1.9
9.7
1.9
9.3
UNIT
MHz
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 1 MHz
TYP
UNIT
48
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
tw
CL = 50 pF
(see Note A)
VCC
500 Ω
Input
50%
50%
0V
VOLTAGE WAVEFORMS
LOAD CIRCUIT
VCC
Input
(see Note B)
Timing Input
(see Note B)
VCC
50%
0V
th
tsu
Data Input
50%
50%
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VCC
50%
tPLH
tPHL
50%
0V
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
54AC11175, 74AC11175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCAS090 – DECEMBER 1989 – REVISED APRIL 1993
2–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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