SIPEX SP509CF

®
SP509
Rugged 40Mbps, 8 Channel Multi-Protocol Transceiver
with Programmable DCE/DTE and Termination Resistors
FEATURES
■ Ultra Fast 40Mbps Differential Transmission Rates Available
■ Improved ESD Tolerance for Analog I/Os with 15kV HBM.
■ Internal Transceiver Termination Resistors for V.11 and V.35
■ Interface Modes:
✓ RS-232 (V.28)
✓ X.21 (V.11)
✓ RS-449/V.36
(V.10 & V.11)
Now Available in Lead Free Packaging
✓ EIA-530 (V.10 & V.11)
✓ EIA-530A (V.10 & V.11)
✓ V.35
Refer to page 7 for pinout
■ Protocols are Software Selectable with 3-Bit Word
■ Eight (8) Drivers and Eight (8) Receivers
■ V.35 and V.11 Receiver Termination Network Disable Option
■ Internal Line or Digital Loopback for Diagnostic Testing
■ Adheres to NET1/NET2 and TBR-2 Compliancy Requirements
■ Easy Flow-Through Pinout
■ +5V Only Operation
■ Individual Driver and Receiver Enable/Disable Controls
■ Operates in either DTE or DCE Mode
APPLICATIONS
■ Router
■ Frame Relay
■ CSU
■ DSU
■ PBX
■ Secure Communication Terminals
DESCRIPTION
The SP509 is a monolithic device that supports eight (8) popular serial interface standards for
Wide Area Network (WAN) connectivity. The SP509 is fabricated using a low power BiCMOS
process technology, and incorporates a Sipex regulated charge pump allowing +5V only
operation. Sipex's patented charge pump provides a regulated output of +5.8V, which will
provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8)
receivers can be configured via software for any of the above interface modes at any time. The
SP509 requires no additional external components for compliant operation for all of the eight
(8) modes of operation other than four capacitors used for the internal charge pump. All
necessary termination is integrated within the SP509 and is switchable when V.35 drivers and
V.35 receivers, or when V.11 receivers are used. The SP509 provides the controls and
transceiver availability for operating as either a DTE or DCE.
Additional features with the SP509 include internal loopback that can be initiated in any of the
operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are
internally connected to driver inputs creating an internal signal path bypassing the serial
communications controller for diagnostic testing. The SP509 also includes a latch enable pin
with the driver and receiver address decoder. The internal V.11 or V.35 receiver termination
can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8)
drivers and receivers in the SP509 include separate enable pins for added convenience. The
SP509 is ideal for WAN serial ports in networking equipment such as routers, concentrators,
network muxes, DSU/CSU's, networking test equipment, and other access devices.
Applicable U.S. Patents-5,306,954; and others patents pending
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
1
© Copyright 2004 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
STORAGE CONSIDERATIONS
Due to the relatively large package size of the 100-pin quad flatpack, storage in a low humidity environment is preferred. Large
high density plastic packages are moisture sensitive and should
be stored in Dry Vapor Barrier Bags. Prior to usage, the parts
should remain bagged and stored below 40°C and 60%RH. If
the parts are removed from the bag, they should be used within
48 hours or stored in an environment at or below 20%RH. If the
above conditions cannot be followed, the parts should be
baked for four hours at 125°C in order to remove moisture prior
to soldering. Sipex ships the 100-pin LQFP in Dry Vapor
Barrier Bags with a humidity indicator card and desiccant pack.
The humidity indicator should be below 30%RH.
These are stress ratings only and functional operation of the
device at these ratings or any other above those indicated in the
operation sections of the specifications below is not implied.
Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
VCC ................................................................................................ +7V
Input Voltages:
Logic ................................................ -0.3V to (VCC+0.5V)
Drivers ............................................. -0.3V to (VCC+0.5V)
Receivers ........................................................... ±15.5V
Output Voltages:
Logic ................................................ -0.3V to (VCC+0.5V)
Drivers ................................................................... ±12V
Receivers ........................................ -0.3V to (VCC+0.5V)
Storage Temperature ................................................ -65°C to +150°C
Power Dissipation ................................................................. 1520mW
(derate 19.0mW/°C above +70°C)
Package Derating:
øJA
.................................................................................................................
52.7 °C/W
øJC .................................................................................................................... 6.5 °C/W
ELECTRICAL SPECIFICATIONS
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
MIN.
TYP.
MAX.
UNITS
CONDITIONS
0.8
Volts
Volts
0.4
Volts
Volts
IOUT= –3.2mA
IOUT= 1.0mA
±15
±15
±100
Volts
Volts
mA
Ω
per Figure 1
per Figure 2
per Figure 4, VOUT=0V
per Figure 5
VCC = +5V for AC parameters
1.5
30
µs
V/µs
per Figure 6; +3V to -3V
per Figure 3
5
5
µs
µs
kbps
7
+2.0
3.0
kΩ
Volts
Volts
Volts
LOGIC INPUTS
VIL
VIH
2.0
LOGIC OUTPUTS
VOL
VOH
2.4
V.28 DRIVER
DC Parameters
Outputs
Open Circuit Voltage
Loaded Voltage
Short-Circuit Current
Power-Off Impedance
AC Parameters
Outputs
Transition Time
Instantaneous Slew Rate
Propagation Delay
tPHL
tPLH
Max.Transmission Rate
±5.0
300
0.5
0.5
120
1
1
230
V.28 RECEIVER
DC Parameters
Inputs
Input Impedance
Open-Circuit Bias
HIGH Threshold
LOW Threshold
AC Parameters
Propagation Delay
tPHL
tPLH
Date: 8/19/04
3
0.8
1.7
1.2
per Figure 7
per Figure 8
VCC = +5V for AC parameters
50
50
100
100
500
500
ns
ns
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
2
© Copyright 2004 Sipex Corporation
ELECTRICAL SPECIFICATIONS
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
MIN.
TYP.
MAX.
UNITS
CONDITIONS
V.28 RECEIVER (continued)
AC Parameters (cont.)
Max.Transmission Rate
120
235
kbps
V.10 DRIVER
DC Parameters
Outputs
Open Circuit Voltage
Test-Terminated Voltage
Short-Circuit Current
Power-Off Current
AC Parameters
Outputs
Transition Time
Propagation Delay
tPHL
tPLH
Max.Transmission Rate
±4.0
0.9VOC
30
30
120
±150
±100
Volts
Volts
mA
µA
200
ns
500
500
ns
ns
kbps
+3.25
mA
kΩ
Volts
±6.0
100
100
per Figure 9
per Figure 10
per Figure 11
per Figure 12
VCC = +5V for AC parameters
per Figure 13; 10% to 90%
V.10 RECEIVER
DC Parameters
Inputs
Input Current
Input Impedance
Sensitivity
AC Parameters
Propagation Delay
tPHL
tPLH
Max.Transmission Rate
–3.25
4
±0.3
per Figures 14 and 15
VCC = +5V for AC parameters
50
50
ns
ns
kbps
±6.0
0.67VOC
±0.4
+3.0
±150
±100
Volts
Volts
Volts
Volts
Volts
mA
µA
10
ns
50
50
5
ns
ns
ns
120
V.11 DRIVER
DC Parameters
Outputs
Open Circuit Voltage
Test Terminated Voltage
Balance
Offset
Short-Circuit Current
Power-Off Current
AC Parameters
Outputs
Transition Time
Propagation Delay
tPHL
tPLH
Differential Skew
(|tPHL - tPLH|)
Max.Transmission Rate
Channel to Channel Skew
±2.0
0.5VOC
30
30
2
40
per Figure 16
per Figure 17
per Figure 17
per Figure 17
per Figure 18
per Figure 19
VCC = +5V for AC parameters
per Figures 21 and 36; 10% to 90%
Using CL = 50pF;
per Figures 33 and 36
per Figures 33 and 36
per Figures 33 and 36
Mbps
ns
2
V.11 RECEIVER
DC Parameters
Inputs
Common Mode Range
Sensitivity
Date: 8/19/04
–7
+7
±0.2
Volts
Volts
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
3
© Copyright 2004 Sipex Corporation
ELECTRICAL SPECIFICATIONS
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
MIN.
TYP.
MAX.
UNITS
±3.25
mA
±60.75
mA
kΩ
CONDITIONS
V.11 RECEIVER (continued)
DC Parameters (cont.)
Input Current
Current w/100Ω Termination
Input Impedance
AC Parameters
Propagation Delay
tPHL
tPLH
Skew (|tPHL - tPLH|)
Max.Transmission Rate
Channel to Channel Skew
–3.25
4
30
30
2
per Figure 20 and 22;
power on or off
per Figure 23 and 24
VCC = +5V for AC parameters
Using CL = 50pF;
per Figures 33 and 38
per Figures 33 and 38
per Figure 33
50
50
5
ns
ns
ns
Mbps
ns
±0.66
±0.6
+0.2VST
150
165
Volts
Volts
Volts
Ω
Ω
7
20
ns
per Figure 29; 10% to 90%
30
30
2
50
50
5
ns
ns
ns
per Figures 33 and 36; CL = 20pF
per Figures 33 and 36; CL = 20pF
per Figures 33 and 36; CL = 20pF
40
2
V.35 DRIVER
DC Parameters
Outputs
Test Terminated Voltage
±0.44
Offset
Output Overshoot
-0.2VST
Source Impedance
50
Short-Circuit Impedance
135
AC Parameters
Outputs
Transition Time
Propagation Delay
tPHL
tPLH
Differential Skew
(|tPHL - tPLH|)
Max.Transmission Rate
40
Channel to Channel Skew
per Figure 25
per Figure 25
per Figure 25; VST = Steady state value
per Figure 27; ZS = V2/V1 x 50
per Figure 28
VCC = +5V for AC parameters
Mbps
ns
2
V.35 RECEIVER
DC Parameters
Inputs
Sensitivity
Source Impedance
Short-Circuit Impedance
AC Parameters
Propagation Delay
tPHL
tPLH
Skew (|tPHL - tPLH|)
Max.Transmission Rate
Channel to Channel Skew
±50
90
135
30
30
2
+100
110
165
mV
Ω
Ω
50
50
5
ns
ns
ns
Mbps
ns
per Figures 33 and 38; CL = 20pF
per Figures 33 and 38; CL = 20pF
per Figure 33; CL = 20pF
µA
µA
per Figure 32; Drivers disabled
TX & RX disabled, 0.4V - VO - 2.4V
40
2
per Figure 30; ZS = V2/V1 x 50Ω
per Figure 31
VCC = +5V for AC parameters
TRANSCEIVER LEAKAGE CURRENT
Driver Output 3-State Current
Rcvr Output 3-State Current
500
1
10
POWER REQUIREMENTS
VCC
ICC (Shutdown Mode)
(V.28/RS-232)
(V.11/RS-422)
(EIA-530 & RS-449)
(V.35)
(EIA-530A)
Date: 8/19/04
4.75
5.00
1
95
230
270
170
200
5.25
Volts
µA
mA
mA
mA
mA
mA
All ICC values are with VCC = +5V
fIN = 120kbps; Drivers active & loaded
fIN = 10Mbps; Drivers active & loaded
fIN = 10Mbps; Drivers active & loaded
V.35 @ fIN = 10Mbps, V.28 @ 20kbps
fIN = 10Mbps; Drivers active & loaded
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
4
© Copyright 2004 Sipex Corporation
OTHER AC CHARACTERISTICS
TA = +25°C and VCC = +5.0V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW
0.11
5.0
µs
tPZH; Tri-state to Output HIGH
0.11
2.0
µs
tPLZ; Output LOW to Tri-state
0.05
2.0
µs
tPHZ; Output HIGH to Tri-state
0.05
2.0
µs
RS-423/V.10
tPZL; Tri-state to Output LOW
0.07
2.0
µs
tPZH; Tri-state to Output HIGH
0.05
2.0
µs
tPLZ; Output LOW to Tri-state
0.55
2.0
µs
tPHZ; Output HIGH to Tri-state
0.12
2.0
µs
RS-422/V.11
tPZL; Tri-state to Output LOW
0.04
10.0
µs
tPZH; Tri-state to Output HIGH
0.05
2.0
µs
tPLZ; Output LOW to Tri-state
0.03
2.0
µs
tPHZ; Output HIGH to Tri-state
0.11
2.0
µs
V.35
tPZL; Tri-state to Output LOW
0.85
10.0
µs
tPZH; Tri-state to Output HIGH
0.36
2.0
µs
tPLZ; Output LOW to Tri-state
0.06
2.0
µs
tPHZ; Output HIGH to Tri-state
0.05
2.0
µs
CONDITIONS
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 37; S1
closed
CL = 100pF, Fig. 34 & 37; S2
closed
CL = 15pF, Fig. 34 & 37; S1
closed
CL = 15pF, Fig. 34 & 37; S2
closed
CL = 100pF, Fig. 34 & 37; S1
closed
CL = 100pF, Fig. 34 & 37; S2
closed
CL = 15pF, Fig. 34 & 37; S1
closed
CL = 15pF, Fig. 34 & 37; S2
closed
RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW
0.05
2.0
µs
CL = 100pF, Fig. 35 & 40; S1
closed
tPZH; Tri-state to Output HIGH
0.05
2.0
µs
CL = 100pF, Fig. 35 & 40; S2
closed
tPLZ; Output LOW to Tri-state
0.65
2.0
µs
CL = 100pF, Fig. 35 & 40; S1
closed
tPHZ; Output HIGH to Tri-state
0.65
2.0
µs
CL = 100pF, Fig. 35 & 40; S2
closed
RS-423/V.10
tPZL; Tri-state to Output LOW
0.04
2.0
µs
CL = 100pF, Fig. 35 & 40; S1
closed
tPZH; Tri-state to Output HIGH
0.03
2.0
µs
CL = 100pF, Fig. 35 & 40; S2
closed
tPLZ; Output LOW to Tri-state
0.03
2.0
µs
CL = 100pF, Fig. 35 & 40; S1
closed
tPHZ; Output HIGH to Tri-state
0.03
2.0
µs
CL = 100pF, Fig. 35 & 40; S2
closed
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
5
© Copyright 2004 Sipex Corporation
OTHER AC CHARACTERISTICS (Continued)
TA = +25°C and VCC = +5.0V unless otherwise noted.
PARAMETER
RS-422/V.11
tPZL; Tri-state to Output LOW
MIN.
TYP.
MAX.
UNITS
0.04
2.0
µs
tPZH; Tri-state to Output HIGH
0.03
2.0
µs
tPLZ; Output LOW to Tri-state
0.03
2.0
µs
tPHZ; Output HIGH to Tri-state
0.03
2.0
µs
V.35
tPZL; Tri-state to Output LOW
0.04
2.0
µs
tPZH; Tri-state to Output HIGH
0.03
2.0
µs
tPLZ; Output LOW to Tri-state
0.03
2.0
µs
tPHZ; Output HIGH to Tri-state
0.03
2.0
µs
CONDITIONS
CL = 100pF, Fig. 35 & 39; S1
closed
CL = 100pF, Fig. 35 & 39; S2
closed
CL = 15pF, Fig. 35 & 39; S1
closed
CL = 15pF, Fig. 35 & 39; S2
closed
CL = 100pF, Fig. 35 & 39; S1
closed
CL = 100pF, Fig. 35 & 39; S2
closed
CL = 15pF, Fig. 35 & 39; S1
closed
CL = 15pF, Fig. 35 & 39; S2
closed
TRANSCEIVER TO TRANSCEIVER SKEW
RS-232 Driver
100
100
RS-232 Receiver
20
20
RS-422 Driver
2
2
RS-422 Receiver
2
3
RS-423 Driver
5
5
RS-423 Receiver
5
5
(per Figures 32, 33, 36, 38)
ns
[ (tphl )Tx1 – (tphl )Txn ]
ns
[ (tplh )Tx1 – (tplh )Txn]
ns
[ (tphl )Rx1 – (tphl )Rxn ]
ns
[ (tphl )Rx1 – (tphl )Rxn ]
ns
[ (tphl )Tx1 – (tphl )Txn ]
ns
[ (tplh )Tx1 – (tplh )Txn ]
ns
[ (tphl )Rx1 – (tphl )Rxn ]
ns
[ (tphl )Rx1 – (tphl )Rxn ]
ns
[ (tphl )Tx2 – (tphl )Txn ]
ns
[ (tplh )Tx2 – (tplh )Txn ]
ns
[ (tphl )Rx2 – (tphl )Rxn ]
ns
[ (tphl )Rx2 – (tphl )Rxn ]
V.35 Driver
ns
ns
ns
ns
V.35 Receiver
Date: 8/19/04
2
2
2
2
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
6
[ (tphl )Tx1 – (tphl )Txn ]
[ (tplh )Tx1 – (tplh )Txn ]
[ (tphl )Rx1 – (tphl )Rxn ]
[ (tphl )Rx1 – (tphl )Rxn]
© Copyright 2004 Sipex Corporation
76 N/C
77 VCC
78 TR(b)
79 RRC(b)
80 VCC
81 RRC(a)
82 GND
83 RS(a)
84 VCC
85 RS(b)
86 GND
87 ST(a)
88 VCC
89 V35TGND3
90 ST(b)
91 GND
92 TT(a)
93 VCC
94 V35TGND2
95 TT(b)
96 GND
97 SD(a)
98 VCC
99 V35TGND1
100 SD(b)
PINOUT 100 PIN LQFP
VCC 1
75 TR(a)
GND 2
74 GND
SDEN 3
73 VDD
TTEN 4
72 C1+
STEN 5
71 VCC
70 C2+
RSEN 6
TREN 7
69 C1-
®
68 GND
RRCEN 8
RLEN 9
67 C2-
LLEN 10
66 VSS
RDEN 11
65 RL(a)
RTEN 12
64 VCC
TXCEN 13
63 LL(a)
CSEN 14
62 TM(a)
DMEN 15
61 IC(a)
SP509
RRTEN 16
ICEN 17
TMEN 18
D0 19
60 RRT(a)
59 RRT(b)
58 V10GND
57 DM(a)
D1 20
56 DM(b)
D2 21
55 CS(a)
TERM_OFF 22
54 CS(b)
53 TXC(a)
D_LATCH 23
52 GND
N/C 24
51 TXC(b)
RT(a) 50
RT(b) 49
RD(a) 48
RD(b) 47
V35RGND 46
VCC 45
TM 43
GND 44
RI 42
DCD_DTE 41
DSR 40
CTS 39
TXC 38
RXC 37
LL 35
RXD 36
RL 34
DCD_DCE 33
DTR 32
ST 30
RTS 31
TXCE 29
TXD 28
VCC 26
Date: 8/19/04
LOOPBACK 27
GND 25
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
7
© Copyright 2004 Sipex Corporation
PIN DESCRIPTION
Pin Number
Pin Name
Pin Number
Pin Name
1
VCC
Description
5V Power Supply Input
51
TxC(b)
Description
2
GND
Signal Ground
52
GND
3
SDEN
TxD Driver Enable Input
53
TxC(a)
4
TTEN
TxCE Driver Enable Input
54
CS(b)
CTS Non-Inverting Input
5
STEN
ST Driver Enable Input
55
CS(a)
CTS Inverting Input
6
RSEN
RTS Driver Enable Input
56
DM(b)
DSR Non-Inverting Input
7
TREN
DTR Driver Enable Input
57
DM(a)
8
RRCEN
DCD Driver Enable Input
58
GNDV10
TxC Non-Inverting Input
Signal Ground
TxC Inverting Input
DSR Inverting Input
V.10 Rx Reference Node
9
RLEN
RL Driver Enable Input
59
RRT(b)
DCDDTE Non-Inverting Input
10
LLEN#
LL Driver Enable Input
60
RRT(a)
DCDDTE Inverting Input
11
RDEN#
RxD Receiver Enable Input
61
IC
RI Receiver Input
12
RTEN#
RxC Receiver Enable Input
62
TM(a)
TM Receiver Input
13
TxCEN#
TxC Receiver Enable Input
63
LL(a)
LL Driver Output
14
CSEN#
CTS Receiver Enable Input
64
VCC
Power Supply Input
15
DMEN#
DSR Receiver Enable Input
65
RL(a)
RL Driver Output
16
RRTEN#
DCDDTE Receiver Enable Input
66
VSS1
-2xVCC Charge Pump Output
17
ICEN#
RI Receiver Enable Input
67
C2N
Charge Pump Capacitor
18
TMEN
TM Receiver Enable Input
68
GND
Signal Ground
19
D0
Mode Select Input
69
C1N
Charge Pump Capacitor
20
D1
Mode Select Input
70
C2P
Charge Pump Capacitor
21
D2
Mode Select Input
71
VCC
Power Supply Input
C1P
Charge Pump Capacitor
22
TERM_OFF Termination Disable Input
72
23
D_LATCH#
Decoder Latch Input
73
VDD
2xVCC Charge Pump Output
24
NC
No Connect
74
GND
Signal Ground
25
GND
Signal Ground
75
TR(a)
DTR Inverting Output
26
VCC
5V Power Supply Input
76
NC
77
VCC
Power Supply Input
TxD Driver TTL Input
78
TR(b)
DTR Non-Inverting Output
TxCE Driver TTL Input
79
RRC(b)
DCD Non-Inverting Output
ST Driver TTL Input
80
VCC
RTS Driver TTL Input
81
RRC(a)
27
LOOPBACK# Loopback Mode Enable Input
28
TxD
29
TxCE
30
ST
31
RTS
32
DTR
33
DCD_DCE
34
35
36
37
No Connect
Power Supply Input
DCD Inverting Output
DTR Driver TTL Input
82
GND
Signal Ground
DCDDCE Driver TTL Input
83
RS(a)
RTS Inverting Output
RL
RL Driver TTL Input
84
VCC
Power Supply Input
LL
LL Driver TTL Input
85
RS(b)
RTS Non-Inverting Output
RxD
RxD Receiver TTL Output
86
GND
Signal Ground
RxC
RxC Receiver TTLOutput
87
ST(a)
ST Inverting Output
VCC
Power Supply Input
38
TxC
TxC Receiver TTL Output
88
39
CTS
CTS Receiver TTL Output
89
40
DSR
DSR Receiver TTL Output
90
ST(b)
ST Non-Inverting Output
41
DCD_DTE
DCDDTE Receiver TTL Output
91
GND
Signal Ground
V35TGND3 ST Termination Referance
42
RI
RI Receiver TTL Output
92
TT(a)
TxCE Inverting Output
43
TM
TM Receiver TTL Output
93
VCC
5V Power Supply Input
44
GND
Signal Ground
94
Power Supply Input
95
TT(b)
96
GND
Signal Ground
SD(a)
TxD Inverting Output
VCC
5V Power Supply Input
45
46
VCC
V35RGND
Reciever Termination Refrence
47
RD(b)
RXD Non-Inverting Input
97
48
RD(a)
RXD Inverting Input
98
49
RT(b)
RxC Non-Inverting Input
99
50
RT(a)
RxC Inverting Input
100
Date: 8/19/04
V35TGND2 ST Termination Referance
V35TGND1 ST Termination Referance
SD(b)
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
8
TxCE Non-Inverting Output
TxD Non-Inverting Output
© Copyright 2004 Sipex Corporation
SP509 Driver Table
Driver Output
Pin
V.35 Mode
EIA-530
Mode
RS-232
Mode
(V.28)
EIA-530A
Mode
RS-449
Mode
(V.36)
X.21 Mode
(V.11)
Shutdown
MODE (D0, D1, D2)
001
010
011
100
101
110
111
Suggested
Signal
T1OUT(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxD(a)
T1OUT(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxD(b)
T2OUT(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxCE(a)
T2OUT(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxCE(b)
T3OUT(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxC_DCE(a)
T3OUT(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxC_DCE(b)
T4OUT(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
RTS(a)
T4OUT(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
RTS(b)
T5OUT(a)
V.28
V.11
V.28
V.10
V.11
V.11
High-Z
DTR(a)
T5OUT(b)
High-Z
V.11
High-Z
High-Z
V.11
V.11
High-Z
DTR(b)
T6OUT(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
DCD_DCE(a)
T6OUT(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
DCD_DCE(b)
T7OUT(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
RL
T8OUT(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
LL
X.21 Mode
(V.11)
Shutdown
Suggested
Signal
Table 1. Driver Mode Selection
SP509 Receiver Table
Receiver Input
Pin
V.35 Mode
EIA-530
Mode
RS-232
Mode
(V.28)
EIA-530A
Mode
RS-449
Mode
(V.36)
MODE (D0, D1, D2)
001
010
011
100
101
110
111
R1IN(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
RxD(a)
R1IN(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
RxD(b)
R2IN(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
RxC(a)
R2IN(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
RxC(b)
R3IN(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxC_DTE(a)
R3IN(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxC_DTE(b)
R4IN(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
CTS(a)
R4IN(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
CTS(b)
R5IN(a)
V.28
V.11
V.28
V.10
V.11
V.11
High-Z
DSR(a)
R5IN(b)
High-Z
V.11
High-Z
High-Z
V.11
V.11
High-Z
DSR(b)
R6IN(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
DCD_DTE(a)
R6IN(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
DCD_DTE(b)
R7IN(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
RI
R8IN(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
TM
Table 2. Receiver Mode Selection
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
9
© Copyright 2004 Sipex Corporation
TEST CIRCUITS
A
A
VOC
VT
3kΩ
C
C
Figure 1. V.28 Driver Output Open Circuit Voltage
Figure 2. V.28 Driver Output Loaded Voltage
A
A
VT
7kΩ
Isc
Oscilloscope
C
C
Scope used for slew rate
measurement.
Figure 3. V.28 Driver Output Slew Rate
Figure 4. V.28 Driver Output Short-Circuit Current
VCC = 0V
A
A
Ix
±2V
3kΩ
C
Oscilloscope
C
Figure 6. V.28 Driver Output Rise/Fall Times
Figure 5. V.28 Driver Output Power-Off Impedance
Date: 8/19/04
2500pF
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
10
© Copyright 2004 Sipex Corporation
A
A
Iia
±15V
voc
C
C
Figure 7. V.28 Receiver Input Impedance
Figure 8. V.28 Receiver Input Open Circuit Bias
A
A
3.9kΩ
VOC
Vt
450Ω
C
C
Figure 9. V.10 Driver Output Open-Circuit Voltage
Figure 10. V.10 Driver Output Test Terminated Voltage
VCC = 0V
A
A
Ix
±0.25V
Isc
C
C
Figure 11. V.10 Driver Output Short-Circuit Current
Date: 8/19/04
Figure 12. V.10 Driver Output Power-Off Current
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
11
© Copyright 2004 Sipex Corporation
A
A
Iia
±10V
Oscilloscope
450Ω
C
C
Figure 13. V.10 Driver Output Transition Time
Figure 14. V.10 Receiver Input Current
A
V.10 RECEIVER
VOCA
+3.25mA
3.9kΩ
VOC
VOCB
-10V
-3V
B
+3V
+10V
Maximum Input Current
vesus Voltage
C
-3.25mA
Figure 15. V.10 Receiver Input IV Graph
Figure 16. V.11 Driver Output Open-Circuit Voltage
A
A
Isa
50Ω
VT
50Ω
Isb
B
B
VOS
C
C
Figure 17. V.11 Driver Output Test Terminated Voltage
Date: 8/19/04
Figure 18. V.11 Driver Output Short-Circuit Current
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
12
© Copyright 2004 Sipex Corporation
VCC = 0V
A
Iia
A
±10V
Ixa
±0.25V
B
B
C
C
VCC = 0V
A
A
±10V
±0.25V
Iib
Ixb
B
B
C
C
Figure 19. V.11 Driver Output Power-Off Current
Figure 20. V.11 Receiver Input Current
A
V.11 RECEIVER
+3.25mA
50Ω
Oscilloscope
50Ω
-10V
B
50Ω
-3V
VE
+3V
+10V
Maximum Input Current
vesus Voltage
C
-3.25mA
Figure 22. V.11 Receiver Input IV Graph
Figure 21. V.11 Driver Output Rise/Fall Time
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
13
© Copyright 2004 Sipex Corporation
V.11 RECEIVER
A
w/ Optional Cable Termination
(100Ω to 150Ω)
i [mA] = V [V] / 0.1
Iia
±6V
i [mA] = V [V] - 3) / 4.0
100Ω to
150Ω
-6V
-3V
+3V
B
+6V
i [mA] = V [V] - 3) / 4.0
C
Maximum Input Current
versus Voltage
i [mA] = V [V] / 0.1
Figure 24. V.11 Receiver Input Graph w/ Termination
A
A
±6V
50Ω
100Ω to
150Ω
VT
50Ω
Iib
B
VOS
B
C
C
Figure 23. V.11 Receiver Input Current w/ Termination
Figure 25. V.35 Driver Output Test Terminated Voltage
V1
A
A
50Ω
50Ω
VT
24kHz, 550mVp-p
Sine Wave
V2
50Ω
VOS
B
B
C
C
Figure 26. V.35 Driver Output Offset Voltage
Date: 8/19/04
Figure 27. V.35 Driver Output Source Impedance
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
14
© Copyright 2004 Sipex Corporation
A
A
50Ω
Oscilloscope
50Ω
ISC
B
B
50Ω
±2V
C
C
Figure 29. V.35 Driver Output Rise/Fall Time
Figure 28. V.35 Driver Output Short-Circuit Impedance
V1
A
A
50Ω
24kHz, 550mVp-p
Sine Wave
V2
Isc
B
B
±2V
C
C
Figure 30. V.35 Receiver Input Source Impedance
Figure 31. V.35 Receiver Input Short-Circuit Impedance
Any one of the three conditions for disabling the driver.
VCC = 0V
1
1
1
D2
D1
D0
CL1
A
VCC
IZSC
±12V
TIN
B
B
A
A
ROUT
CL2
15pF
Logic “1”
B
fIN (50% Duty Cycle, 2.5VP-P)
Figure 33. Driver/Receiver Timing Test Circuit
Figure 32. Driver Output Leakage Current Test
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
15
© Copyright 2004 Sipex Corporation
S1
500Ω
Output
Under
Test
1KΩ
Test Point
Receiver
Output
VCC
VCC
S1
CRL
1KΩ
CL
S2
S2
Figure 35. Receiver Timing Test Load Circuit
Figure 34. Driver Timing Test Load Circuit
f > 10MHz; tR < 10ns; tF < 10ns
DRIVER
INPUT
DRIVER
OUTPUT
+3V
1.5V
1.5V
0V
A
tPLH
VO 1/2VO
1/2VO
B
tDPLH
DIFFERENTIAL
OUTPUT
VB – VA
tPHL
VO+
0V
VO–
tDPHL
tR
tF
tSKEW = | tDPLH - tDPHL |
Figure 36. Driver Propagation Delays
Mx or Tx_Enable
+3V
1.5V
0V
1.5V
tZL
tLZ
5V
2.3V
A, B
VOL
VOH
A, B
2.3V
0V
Output normally LOW
0.5V
Output normally HIGH
0.5V
tZH
tHZ
Figure 37. Driver Enable and Disable Times
f > 10MHz; tR < 10ns; tF < 10ns
V0D2+
0V
A–B
0V
INPUT
V0D2–
OUTPUT
VOH
(VOH - VOL)/2
(VOH - VOL)/2
RECEIVER OUT
VOL
tPLH
tPHL
tSKEW = | tPHL - tPLH |
Figure 38. Receiver Propagation Delays
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
16
© Copyright 2004 Sipex Corporation
f = 1MHz; tR < 10ns; tF < 10ns
DECx +3V
1.5V
0V
RCVRENABLE
1.5V
tZL
tLZ
5V
1.5V
RECEIVER OUT
VIL
Output normally LOW
0.5V
Output normally HIGH
0.5V
VIH
RECEIVER OUT
1.5V
0V
tZH
tHZ
Figure 39. Receiver Enable and Disable Times
+3V
f = 60kHz; tR < 10ns; tF < 10ns
1.5V
1.5V
Tx_Enable
0V
0V
TOUT
VOL
+3V
tLZ
tZL
VOL - 0.5V
VOL - 0.5V
Output LOW
f = 60kHz; tR < 10ns; tF < 10ns
1.5V
1.5V
Tx_Enable
0V
VOH
tZH
Output HIGH
tHZ
VOH - 0.5V
TOUT
0V
Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
17
© Copyright 2004 Sipex Corporation
Figure 41. Typical V.28 Driver Output Waveform
Figure 42. Typical V.10 Driver Output Waveform
Figure 43. Typical V.11 Driver Output Waveform
Figure 44. Typical V.35 Driver Output Waveform
Figure 45. Typical V.11 Driver Output Waveform at 20MHz
Figure 46. Typical V.35 Driver Output Waveform at 20 MHz
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
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© Copyright 2004 Sipex Corporation
+5V (decoupling capacitor not shown)
1µF
1µF
VCC
C1+
1µF
C1-
C2+
C2-
VSS
VDD
Regulated Charge Pump
1µF
V35RGND
TxD
RD(a)
SD(a)
V35TGND1
RxD
RDEN
SD(b)
RD(b)
SDEN
RT(a)
TxCE
TT(a)
V35TGND2
RxC
RTEN
TT(b)
RT(b)
TTEN
TxC(a)
ST
ST(a)
TxC
TxCEN
V35TGND3
ST(b)
TxC(b)
STEN
CS(a)
RTS
RS(a)
CTS
CSEN
RS(b)
CS(b)
RSEN
DM(a)
DTR
TR(a)
DSR
DMEN
TR(b)
DM(b)
TREN
RRT(a)
DCD_DCE
RRC(a)
DCD_DTE
RRTEN
RRC(b)
RRT(b)
RRCEN
IC
RL
RI
ICEN
RL(a)
RLEN
TM
LL
TM
TMEN
LL(a)
LLEN
D0
D1
SP509
V.10-GND
D2
D-LATCH
TERM-OFF
LOOPBACK
GND
RECEIVER TERMINATION NETWORK
V.35 MODE
V.11 MODE
V.35 DRIVER TERMINATION NETWORK
51ohms
51ohms
V.35 MODE
124ohms
RX ENABLE
124ohms
TX ENABLE
51ohms
51ohms
Figure 47. Functio nal Diagram
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
19
© Copyright 2004 Sipex Corporation
FEATURES
There are four basic types of driver circuits –
ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423),
ITU-T-V.11 (RS-422), and CCITT-V.35.
The SP509 contains highly integrated serial
transceivers that offer programmability between
interface modes through software control. The
SP509 offers the hardware interface modes for
RS-232 (V.28), RS-449/V.36 (V.11 and V.10),
EIA-530 (V.11 and V.10), EIA-530A (V.11 and
V.10), V.35 (V.35 and V.28) and X.21(V.11). The
interface mode selection is done via three control
pins, which can be latched via microprocessor
control.
The V.28 (RS-232) drivers output single-ended
signals with a minimum of +5V (with 3kΩ &
2500pF loading), and can operate over 120kbps.
Since the SP509 uses a charge pump to generate
the RS-232 output rails, the driver outputs will
never exceed +10V. The V.28 driver architecture
is similar to Sipex's standard line of RS-232
transceivers.
The SP509 has eight drivers, eight receivers, and
Sipex's patented on-board charge pump (5,306,954)
that is ideally suited for wide area network
connectivity and other multi-protocol applications.
Other features include digital and line loopback
modes, individual enable/disable control lines for
each driver and receiver, fail-safe when inputs are
either open or shorted, individual termination
resistor ground paths, separate driver and receiver
ground outputs, enhanced ESD protection on driver
outputs and receiver inputs.
The RS-423 (V.10) drivers are also single-ended
signals which produce open circuit VOL and VOH
measurements of +4.0V to +6.0V. When terminated
with a 450Ω load to ground, the driver output will
not deviate more than 10% of the open circuit
value. This is in compliance of the ITU V.10
specification. The V.10 (RS-423) drivers are used
in RS-449/V.36, EIA-530, and EIA-530A modes
as Category II signals from each of their
corresponding specifications. The V.10 drivers
are guaranteed to transmit over 120kbps, but can
operate at over 1Mbps if necessary.
THEORY OF OPERATION
The SP509 device is made up of 1) the drivers, 2)
the receivers, 3) a charge pump, 4) DTE/DCE
switching algorithm, and 5) control logic.
The third type of drivers are V.11 (RS-422)
differential drivers. Due to the nature of differential
signaling, the drivers are more immune to noise as
opposed to single-ended transmission methods.
The advantage is evident over high speeds and
long transmission lines. The strength of the driver
outputs can produce differential signals that can
maintain +2V differential output levels with a load
of 100Ω. The signal levels and drive capability of
these drivers allow the drivers to also support
RS-485 requirements of +1.5V differential output
levels with a 54Ω load. The strength allows the
SP509 differential driver to drive over long cable
lengths with minimal signal degradation. The V.11
drivers are used in RS-449, EIA-530, EIA-530A
and V.36 modes as Category I signals which are
used for clock and data. Sipex's new driver design
over its predecessors allow the SP509 to operate
over 40Mbps for differential transmission.
Drivers
The SP509 has eight enhanced independent drivers.
Control for the mode selection is done via a threebit control word into D0, D1, and D2. The drivers
are prearranged such that for each mode of
operation, the relative position and functionality
of the drivers are set up to accommodate the
selected interface mode. As the mode of the drivers
is changed, the electrical characteristics will change
to support the required signal levels. The mode of
each driver in the different interface modes that
can be selected is shown in Table 1.
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
20
© Copyright 2004 Sipex Corporation
protocols of the receivers. Table 1 shows
the mode of each receiver in the different
interface modes that can be selected. There are
two basic types of receiver circuits—ITU-T-V .28
(RS-232) and ITU-T-V.11, (RS-422).
The fourth type of drivers are V.35 differential
drivers. There are only three available on the
SP509 for data and clock (TxD, TxCE, and TxC
in DCE mode). These drivers are current sources
that drive loop current through a differential pair
resulting in a 550mV differential voltage at the
receiver. These drivers also incorporate fixed
termination networks for each driver in order to
set the VOH and VOL depending on load conditions.
This termination network is basically a “Y”
configuration consisting of two 51Ω resistors
connected in series and a 124Ω resistor connected
between the two 50Ω resistors and a V35TGND
output. Each of the three drivers and its associated
termination will have its own V35TGND output
for grounding convenience. Filtering can be done
on these pins to reduce common mode noise
transmitted over the transmission line by
connecting a capacitor to ground.
The RS-232 (V.28) receiver is single-ended and
accepts RS-232 signals from the RS-232 driver.
The RS-232 receiver has an operating input
voltage range of +15V and can receive signals
downs to +3V. The input sensitivity complies
with RS-232 and V .28 at +3V. The input
impedance is 3kΩ to 7kΩ in accordance to RS232 and V .28. The receiver output produces a
TTL/CMOS signal with a +2.4V minimum for
a logic “1” and a +0.4V maximum for a logic “0”.
The RS-232 (V.28) protocol uses these receivers
for all data, clock and control signals. They are
also used in V.35 mode for control line signals:
CTS, DSR, LL, and RL. The RS-232 receivers
can operate over 120kbps.
The drivers also have separate enable pins
which simplifies half-duplex configurations for
some applications, especially programmable
DTE/DCE. The enable pins will either enable or
disable the output of the drivers according to the
appropriate active logic illustrated on Figure 47.
The enable pins have internal pull-up and pulldown devices, depending on the active polarity
of the receiver, that enable the driver upon poweron if the enable lines are left floating. During
disabled conditions, the driver outputs will be at
a high impedance 3-state.
The second type of receiver is a differential type
that can be configured internally to support
ITU-T-V.10 and CCITT-V.35 depending on its
input conditions. This receiver has a typical
input impedance of 10kΩ and a differential
threshold of less than +200mV, which complies
with the ITU-T-V.11 (RS-422) specifications.
V.11 receivers are used in RS-449/V.36,
EIA-530, EIA-530A and X.21 as Category I
signals for receiving clock, data, and some control
line signals not covered by Category II V.10
circuits. The differential V.11 transceiver has
improved architecture that allows over 40Mbps
transmission rates.
The driver inputs are both TTL or CMOS
compatible. All driver inputs have an internal
pull-up resistor so that the output will be at a
defined state at logic LOW (“0”). Unused driver
inputs can be left floating. The internal pull-up
resistor value is approximately 500kΩ.
Receivers dedicated for data and clock (RxD,
RxC, TxC) incorporate internal termination for
V.11. The termination resistor is typically 120Ω
connected between the A and B inputs. The
termination is essential for minimizing crosstalk
and signal reflection over the transmission line .
The minimum value is guaranteed to exceed
100Ω, thus complying with the V.11 and RS-422
specifications. This resistor is invoked when the
receiver is operating as a V.11 receiver, in modes
EIA-530, EIA-530A, RS-449/V.36, and X.21.
Receivers
The SP509 has eight enhanced independent
receivers. Control for the mode selection is done
via a three-bit control word that is the same as the
driver control word. Therefore, the modes for
the drivers and receivers are identical in the
application.
Like the drivers, the receivers are prearranged
for the specific requirements of the synchronous
serial interface. As the operating mode of the
receivers is changed, the electrical characteristics
will change to support the required serial interface
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
21
© Copyright 2004 Sipex Corporation
The same receivers also incorporate a termination
network internally for V.35 applications. For
V.35, the receiver input termination is a “Y”
termination consisting of two 51Ω resistors
connected in series and a 124Ω resistor connected
between the two 50Ω resistors and V35RGND
output. The V35RGND is usually grounded. The
receiver itself is identical to the V.11 receiver.
CHARGE PUMP
The charge pump is a Sipex-patented design
(5,306,954) and uses a unique approach compared
to older less-efficient designs. The charge pump
still requires four external capacitors, but uses
four-phase voltage shifting technique to attain
symmetrical power supplies. The charge pump
VDD and VSS outputs are regulated to +5.8V and
-5.8V, respectively. There is a free-running
oscillator that controls the four phases of the
voltage shifting. A description of each phase
follows.
The differential receivers can be configured to
be ITU-T-V.10 single-ended receivers by
internally connecting the non-inverting input to
ground. This is internally done by default from
the decoder. The non-inverting input is rerouted
to V10GND and can be grounded separately.
The ITU-T-V.10 receivers can operate over
1Mbps and are used in RS-449/V.36, E1A-530,
E1A-530A and X.21 modes as Category II signals
as indicated by their corresponding specifications.
All receivers include an enable/disable line for
disabling the receiver output allowing convenient
half-duplex configurations. The enable pins will
either enable or disable the output of the receivers
according to the appropriate active logic
illustrated on Figure 47. The receiver’s enable
lines include an internal pull-up or pull-down
device, depending on the active polarity of the
receiver, that enables the receiver upon power up
if the enable lines are left floating. During disabled
conditions, the receiver outputs will be at a high
impedance state. If the receiver is disabled any
associated termination is also disconnected from
the inputs.
Phase 1
__VSS charge storage ——During this phase of
the clock cycle, the positive side of capacitors C1
and C2 are initially charged to VCC. C+ is then
switched to ground and the charge in C1- is
transferred to C2-. Since C2+ is connected to VCC,
the voltage potential across capacitor C2 is now
2XVCC.
Phase 2
—VSS transfer —Phase two of the clock connects
the negative terminal of C2 to the VSS storage
capacitor and the positive terminal of C2 to
ground, and transfers the negative generated
voltage to C3. This generated voltage is regulated
to –5.8V. Simultaneously, the positive side of
the capacitor C1 is switched to VCC and the
negative side is connected to ground.
Phase 3
—VDD charge storage —The third phase of the
clock is identical to the first phase—the charge
transferred in C1 produces –VCC in the negative
terminal of C1 which is applied to the negative
side of the capacitor C2 . Since C2+ is at VCC, the
voltage potential across C2 is 2XVCC.
All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs are
open, terminated but open, or shorted together.
For single-ended V.28 and V.10 receivers, there
are internal 5kΩ pull-down resistors on the inputs
which produces a logic high (“1”) at the receiver
outputs. The differential receivers have a
proprietary circuit that detect open or shorted
inputs and if so, will produce a logic HIGH (“1”)
at the receiver output.
Date: 8/19/04
Phase 4
—VDD transfer —The fourth phase of the clock
connects the negative terminal of C2 to ground,
and transfers the generated 5.8V across C2 to C4,
the VDD storage capacitor. This voltage is
regulated to +5.8V. At the regulated voltage, the
internal oscillator is disabled and simultaneously
with this, the positive side of capacitor C1 is
switched to VCC and the negative side is connected
to ground, and the cycle begins again. The charge
pump cycle will continue as long as the
operational conditions for the internal oscillator
are present.
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
22
© Copyright 2004 Sipex Corporation
Since both V+ and V- are separately generated
from VCC; in a no-load condition V+ and V- will
be symmetrical. Older charge pump approaches
that generate V- from V+ will show a decrease in
the magnitude of V- compared to V+ due to the
inherent inefficiencies in the design.
There are internal pull-up devices on D0, D1,
and D2, which allow the device to be in
SHUTDOWN mode (“111”) upon power up.
However , if the device is powered -up with the
D_LATCH at a logic HIGH, the decoder state of
the SP509 will be undefined.
The clock rate for the charge pump typically
operates at 250kHz. The external capacitors can
be as low as 1µF with a 16V breakdown voltage
rating.
ESD TOLERANCE
The SP509 device incorporates ruggedized ESD
cells on all driver output and receiver input
pins. The ESD structure is improved over our
previous family for more rugged applications
and environments sensitive to electrostatic
discharges and associated transients.
TERM_OFF FUNCTION
The SP509 contains a TERM_OFF pin that
disables all three receiver input termination
networks regardless of mode. This allows the
device to be used in monitor mode applications
typically found in networking test equipment.
The TERM_OFF pin internally contains a
pull-down device with an impedance of over
500kΩ, which will default in a “ON” condition
during power-up if V.35 receivers are used. The
individual receiver enable line and
the SHUTDOWN mode from the decoder
will disable the termination regardless of
TERM_OFF.
CTR1/CTR2 EUROPEAN COMPLIANCY
As with all of Sipex’s previous multi-protocol
serial transceiver IC’s the drivers and receivers
have been designed to meet all the requirements
to NET1/NET2 and TBR2 in order to meet
CTR1/CTR2 compliancy. The SP509 is also
tested in-house at Sipex and adheres to all the
NET1/2 physical layer testing and the ITU Series
V specifications before shipment. Please note
that although the SP509 , as with its predecessors,
adhere to CTR1/CTR2 compliancy testing,
any complex or unusual configuration should
be double-checked to ensure CTR1/CTR2
compliance. Consult the factory for details.
LOOPBACK FUNCTION
The SP509 contains a LOOPBACK pin that
invokes a loopback path. This loopback path is
illustrated in Figure 52. LOOPBACK has an
internal pull-up resistor that defaults to normal
mode during power up or if the pin is left floating.
During loopback, the driver output and receiver
input characteristics will still adhere to its
appropriate specifications.
DECODER AND D_LATCH FUNCTION
The SP509 contains a D_LATCH pin that latches
the data into the D0, D1, and D2 decoder inputs.
If tied to a logic LOW (“0”), the latch is
transparent, allowing the data at the decoder
inputs to propagate through and program
the SP509 accordingly. If tied to a logic
HIGH(“1”), the latch locks out the data and
prevents the mode from changing until this pin
is brought to a logic LOW.
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
23
© Copyright 2004 Sipex Corporation
SD(a)
TxD
SD(b)
RD(a)
RxD
RD(b)
TT(a)
TxCE
TT(b)
RT(a)
RxC
RT(b)
ST(a)
ST
ST(b)
TxC(a)
TxC
TxC(b)
RS(a)
RTS
RS(b)
CS(a)
CTS
CS(b)
TR(a)
DTR
TR(b)
DM(a)
DSR
DM(b)
RRC(a)
DCD_DCE
RRC(b)
RRT(a)
DCD_DTE
RRT(b)
RL
RL(a)
RI
IC
LL
LL(a)
TM
TM(a)
Figure 48. SP509 Loopback Path
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
24
© Copyright 2004 Sipex Corporation
1µF
1µF
Vcc
+
10µF
73
72
VDD
C1+
1µF
69
70
67
1µF
C1- C2+ C2-
VCC
VSS
66
CIRCUIT #
Serial Port Connector Pins
#103
#113
#113
97 SD(a)
TxD
100 S(b)
29
92 TT(a)
TxCE
95 TT(b)
30
87 ST(a)
ST
#105
#108
#109
28
83 RS(a)
RTS
85 RS(b)
32
75 TR(a)
DTR
78 TR(b)
33
24
11
TxCE_TXC_A
TXCE_TXC_B
4
19
RTS_CTS_A
RTS_CTS_B
20
23
DTR_DSR_A
DTR_DSR_B
21
RL_RI
18
LL_TM
81 RRC(a)
79 RRC(b)
34
RL
65 RL(a)
35
#141
TxD_RXD_A
TxD_RXD_B
90 ST(b)
31
DCD_DCE
#140
2
14
LL
63 LL(a)
SP509
#105
#115
#114
#106)
#107
#109
#125
#142
Vcc
DCE/DTE
3
RXD_TXD_A
47 RD(b)
16
RXD_TXD_B
50 RT(a)
17
9
RXC_TXCE_A
RXC_TXCE_B
15
12
TXC_RXC_A
TXC_RXC_B
5
13
CTS_RTS_A
CTS_RTS_B
6
DSR_DTR_A
48 RD(a)
36
RxD
37
RxC
49 RT(b)
53 TxC(a)
38
TxC
51 TxC(b)
55 CS(a)
39
CTS
54 CS(b)
40
57 DM(a)
DSR
56 DM(b)
41
60 RRT(a)
DCD_DTE
59 RRT(b)
42
RI
61 IC
43
TM
62 TM
Logic Section
3 SDEN
4 TTEN
5 STEN
6 RSEN
7 TREN
8 RRCEN
9 RLEN
10 LLEN
11 RDEN
12 RTEN
13 TxCEN
14 CSEN
15 DMEN
16 RRTEN
17 ICEN
18 TMEN
22
DSR_DTR_B
8
DCD_DCD_A
10
DCD-DCD-B
22
RI_RL
25
LL_TM
D0 19
D1 20
D2 21
LOOPBACK 27
Vcc
LATCH 23
TERM_OFF 22
V35TGND1 99
V35TGND2 94
35TGND3 89
* - Driver applies for DCE only on pins 15 and 12.
Receiver applies for DTE only on pins 15 and 12.
Driver applies for DCE only on pins 8 and 10.
Receiver applies for DTE only on pins 8 and 10.
V35RGND 46
V10_GND 58
Input Line
Output Line
Bi-directional Bus.
Figure 49. Configuring SP509 to Operate as either DCE or DTE
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
25
© Copyright 2004 Sipex Corporation
PACKAGE: 100 Pin LQFP
D
D1
0.2 RAD MAX.
c
0.08 RAD MIN.
PIN 1
11°-13°
0°MIN
E1
CL
E
0°–7°
11°-13°
L
L1
CL
A2
A
A1
b
DIMENSIONS
Minimum/Maximum
(mm)
SYMBOL
Seating
Plane
e
100–PIN LQFP
JEDEC MS-026
(BED) Variation
MIN
NOM
COMMON DIMENSIONS
SYMBL MIN
MAX
1.60
A
A1
0.05
A2
1.35
1.40
1.45
b
0.17
0.22
0.27
16.00 BSC
D1
14.00 BSC
e
0.50 BSC
E
16.00 BSC
E1
14.00 BSC
N
100
0.09
L
0.45
L1
0.15
D
c
NOM
MAX
0.60
0.75
0.20
1.00 REF
100 PIN LQFP
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
26
© Copyright 2004 Sipex Corporation
Pin assignments and signal functions are subject to national or regional variation and
proprietary / non-standard implementations
Date: 6/14/04
V.28
TM
25
V.10
TM
25
V.10
TM
18
V.28
142
NN
V.28
BA
2
V.28
DA
24
V.11
V.11
V.11
V.11
BA(A)
BA(B)
DA(A)
DA(B)
2
12
24
11
V.11
V.11
V.11
V.11
SD(A)
SD(B)
TT(A)
TT(B)
4
22
17
35
V.35
V.35
V.35
V.35
103
103
113
113
P
S
U
W
V.11
V.11
V.11
V.11
T(A)
T(B)
X(A)
X(B)
2
9
7**
14**
V.28
CA
4
V.11
V.11
V.11
V.11
RS(A)
RS(B)
TR(A)
TR(B)
7
25
12
30
C
V.11
V.11
C(A)
C(B)
3
10
20
4
19
20
23
105
CD
CA(A)
CA(B)
CD(A)
CD(B)
V.28
V.28
V.11
V.11
V.11
V.11
V.28
108
H
V.28
RL
21
V.10
RL
21
V.10
RL
14
V.28
140
N
V.28
LL
18
V.10
LL
18
V.10
LL
10
V.28
141
L
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
27
** X.21 use either B() or
X(), not both
© Copyright 2004 Sipex Corporation
27
Spare drivers and receivers may be used for optional signals (Signal
Quality, Rate Detect, Standby) or may be disabled using individual
enable pins for each driver and receiver
X.21
V.35
RS-449
EIA-530
RS-232 or V.24
Signal Mnemo DB-25 Signal Mnemo DB-25 Signal Mnemo DB-37 Signal Mnemo M34 Signal Mnemo DB-15
Pin(F)
nic
Pin(F) Type
nic
nic
Pin(F) Type
nic
Pin(F) Type
Pin(F) Type
nic
Type
4
R(A)
V.11
R
104
V.35
6
V.11 RD(A)
3
V.11 BB(A)
3
BB
V.28
11
R(B)
V.11
T
104
V.35
24
V.11 RD(B)
16
V.11 BB(B)
7**
B(A)
V.11
V
115
V.35
8
V.11 RT(A)
17
V.11 DD(A)
17
DD
V.28
14**
B(B)
V.11
X
115
V.35
26
V.11 RT(B)
9
V.11 DD(B)
6
S(A)
V.11
Y
114
V.35
5
ST(A)
V.11
15
V.11 DB(A)
15
DB
V.28
13
S(B)
V.11
AA
114
V.35
23
ST(B)
V.11
12
V.11 DB(B)
5
I(A)
V.11
D
106
V.28
9
V.11 CS(A)
5
V.11 CB(A)
5
CB
V.28
12
I(B)
V.11
27
V.11 CS(B)
13
V.11 CB(B)
E
107
V.28
11
V.11 DM(A)
6
V.11 CC(A)
6
CC
V.28
29
V.11 DM(B)
22
V.11 CC(B)
F
109
V.28
13
V.11 RR(A)
8
V.11 CF(A)
8
CF
V.28
31
V.11 RR(B)
10
V.11 CF(B)
J
125
V.28
22
CE
V.28
© Copyright 2004 Sipex Corporation
Recommended Signals and Port Pin Assignments
Date: 8/19/04
SP508 Multiprotocol Configured as DCE
Interface to PortConnector
Interface to System Logic
Pin
Pin
Pin Mnemonic Number
Circuit
Number Pin Mnemonic
97
SD(A)
Driver_1
TxD
28
100
SD(B)
SDEN
3
92
TT(A)
Driver_2
TxCE
29
95
TT(B)
TTEN
4
87
ST(A)
ST
30
Driver_3
90
ST(B)
STEN
5
83
RS(A)
RTS
31
Driver_4
85
RS(B)
RSEN
6
75
TR(A)
DTR
32
Driver_5
78
TR(B)
TREN
7
81
RRC(A)
DCD_DCE
33
Driver_6
79
RRC(B)
RRCEN
8
65
RL(A)
RL
34
Driver_7
RLEN
9
63
LL(A)
LL
35
Driver_8
LLEN#
10
48
RD(A)
RxD
36
Receiver_1
47
RD(B)
RDEN#
11
50
RT(A)
RxC
37
Receiver_2
49
RT(B)
RTEN#
12
53
TxC(A)
TxC
38
Receiver_3
51
TxC(B)
TxCEN#
13
55
CS(A)
CTS
39
Receiver_4
54
CS(B)
CSEN#
14
57
DM(A)
DSR
40
Receiver_5
56
DM(B)
DMEN#
15
60
RRT(A)
DCD_DTE
41
Receiver_6
59
RRT(B)
RRTEN#
16
61
IC
RI
42
Receiver_7
ICEN#
17
62
TM(A)
TM
43
Receiver_8
TMEN
18
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
DCE CONFIGURATION
Driver_7
Pin Mnemonic
SD(A)
SD(B)
TT(A)
TT(B)
ST(A)
ST(B)
RS(A)
RS(B)
TR(A)
TR(B)
RRC(A)
RRC(B)
RL(A)
Driver_8
LL(A)
63
Receiver_1
Receiver_7
RD(A)
RD(B)
RT(A)
RT(B)
TxC(A)
TxC(B)
CS(A)
CS(B)
DM(A)
DM(B)
RRT(A)
RRT(B)
IC
Receiver_8
TM(A)
Circuit
Driver_1
Driver_2
Driver_3
Driver_4
Driver_5
Driver_6
Receiver_2
Receiver_3
Receiver_4
Receiver_5
Receiver_6
Date: 6/14/04
Signal Mnemo
nic
Type
V.11 SD(A)
V.11 SD(B)
TT(A)
V.11
TT(B)
V.11
DB-37
Pin(M)
4
22
17
35
V.28
105
C
108
H
14
V.28
140
N
10
V.28
141
L
6
24
8
26
5
23
9
27
11
29
13
31
V.35
V.35
V.35
V.35
V.35
V.35
V.28
104
104
115
115
114
114
106
R
T
V
X
Y
AA
D
V.28
107
E
V.28
109
F
V.28
125
J
V.28
142
NN
CA(A)
CA(B)
CD(A)
CD(B)
4
19
20
23
V.11
V.11
V.11
V.11
RS(A)
RS(B)
TR(A)
TR(B)
7
25
12
30
21
V.10
RL
21
V.10
RL
18
V.10
LL
18
V.10
LL
BB
3
V.28
DD
17
V.28
DB
15
BB(A)
BB(B)
DD(A)
DD(B)
DB(A)
DB(B)
CB(A)
CB(B)
CC(A)
CC(B)
CF(A)
CF(B)
RI
3
16
17
9
15
12
5
13
6
22 ‡
8
10
22 ‡
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
RD(A)
RD(B)
RT(A)
RT(B)
ST(A)
ST(B)
CS(A)
CS(B)
DM(A)
DM(B)
RR(A)
RR(B)
TM
25
V.10
CA
4
V.28
CD
20
V.28
RL
V.28
LL
48
47
50
49
53
51
55
54
57
56
60
59
61
V.28
62
V.28
CB
5
V.28
CC
6
V.28
CF
8
V.28
CE
22
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11/10
V.11/Z
V.11
V.11
V.10
V.28
TM
25
V.10
X.21
Signal Mnemo DB-15
Pin(M)
nic
Type
2
T(A)
V.11
9
T(B)
V.11
7**
X(A)
V.11
14**
X(B)
V.11
V.28
V.11
V.11
V.11/10
V.11/Z
V.28
Spare drivers and receivers may be used for optional signals (Signal
Quality, Rate Detect, Standby) or may be disabled using individual
enable pins for each driver and receiver
DB-25
Pin(M)
2
14
24
11
TM
18
AppleTalk™
V.35
Signal Mnemo M34
Pin(M)
nic
Type
P
103
V.35
S
103
V.35
U
113
V.35
W
113
V.35
RS-449
EIA-530
RS-232 or V.24
Signal Mnemo DB-25 Signal Mnemo
nic
Pin(M) Type
nic
Type
BA(A)
V.11
2
BA
V.28
BA(B)
V.11
V.11 DA(A)
24
DA
V.28
V.11 DA(B)
Pin assignments and signal functions are subject to national or regional variation and proprietary
/ non-standard implementations
V.11
V.11
C(A)
C(B)
Signal
Type
V.11
V.11
Mnemo
nic
TxD TxD +
DIN-8
Pin(F)
3
6
V.10
HSKo
1
V.11
V.11
RxDRxD+
5
8
V.10*
V.10
GND
HSKi
GPi
2
7
3
10
V.11
V.11
R(A)
R(B)
4
11
V.11
V.11
V.11
V.11
V.11
V.11
S(A)
S(B)
I(A)
I(B)
B(A)
B(B)
6
13
5
12
7**
14**
** X.21 use either B() or
X(), not both
‡ EIA-530 uses V.11 (differential) for DSR (CC) and DTR (CD) signals; EIA-530-A uses singleended V.10 for DSR and DTR and adds RI signal on pin 22
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
28
© Copyright 2004 Sipex Corporation
28
Pin Mnemonic
TxD
SDEN
TxCE
TTEN
ST
STEN
RTS
RSEN
DTR
TREN
DCD_DCE
RRCEN
RL
RLEN
LL
LLEN#
RxD
RDEN#
RxC
RTEN#
TxC
TxCEN#
CTS
CSEN#
DSR
DMEN#
DCD_DTE
RRTEN#
RI
ICEN#
TM
TMEN
Pin
Number
97
100
92
95
87
90
83
85
75
78
81
79
65
© Copyright 2004 Sipex Corporation
Pin
Number
28
3
29
4
30
5
31
6
32
7
33
8
34
9
35
10
36
11
37
12
38
13
39
14
40
15
41
16
42
17
43
18
Recommended Signals and Port Pin Assignments
Date: 8/19/04
SP508 Multiprotocol Configured as DTE
Interface to PortConnector
Interface to System Logic
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
DTE CONFIGURATION
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP509CF ............................................... 0°C to +70°C ............................................................ 100 Lead LQFP
Available in lead free packaging. To order add “-L” suffix to part number.
Example: SP509CF/TR = standard; SP509CF-L/TR = lead free
REVISION HISTORY
DATE
3/31/04
6/14/04
8/19/04
REVISION
A
B
C
DESCRIPTION
Implemented tracking revision.
Added tables to pages 27 and 28.
Corrected pin description table and figure 49. Updated DCE/DTE
tables.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 8/19/04
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
29
© Copyright 2004 Sipex Corporation