SP6681 PRELIMINARY INFORMATION ® High Efficiency Boost Charge Pump Regulator FEATURES APPLICATIONS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Ideal for Li Ion or 3V to 5V Conversion Low Profile, Inductorless Regulator Up To 96% Power Efficiency +2.7V to +5.5V Input Voltage Range 5.0V, 50mA Output, 4% Accuracy Low EMI Design Low Quiescent Current: 175µA Low Shutdown Current: 4µA Optional External Clock: 32.768kHz Thermal Shutdown Protection Programmable Frequencies: 8.192kHz, 32.768kHz, or 262.14kHz ■ Internal Oscillator: 16kHz or 130kHz, when CLK Pin Is Held High ■ Ultra small 10-Pin MSOP Package GSM SIM Card Power Supplies 3V to 5V Boost Applications Li Ion to 5.0V Boost Applications White LED Driver Smart Card Readers DESCRIPTION The SP6681 is a charge pump ideal for converting a +3.6V Li-Ion battery input to a +5.0V regulated output. An input voltage range of +2.7V to +5.5V is converted to a regulated output of 5.0V. The SP6681 device will operate at three different switching frequencies corresponding to three different output resistances and load current ranges. An external 32.768kHz nominal clock signal is used to produce three synchronized pump frequencies through the use an internal phase lock loop to drive the charge pump. Two control inputs can adjust the internal pump frequency on the fly to 8.192kHz (fINPUT / 4), 32.768kHz (fINPUT x 1), or 262.14kHz (fINPUT x 8). The charge pump configuration dynamically changes to optimize power efficiency. At low input voltages the charge pump doubles the input while at higher inputs the output is 1.5 times the input. The SP6681 can deliver high power efficiencies up to 96% with low quiescent currents from 175µA to 800µA. The SP6681 is offered in a 10-Pin µSOIC package. 2.2µF 2.2µF CF1N CF1P 2 VIN CF2P 9 CF2N 10 7 3 1 VOUT +5.0V output SP6681 +3.6V Lithium-Ion Battery 4 5 6 GND C/4 Cx8 CLK Rev:A Date: 11/20/03 8 4.7µF 2.2µF *All Capacitors Are Ceramic SP6681 High Efficiency Boost Charge Pump Regulator 1 © Copyright 2002 Sipex Corporation PRELIMINARY INFORMATION ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VIN.........................................................-0.3V to +6.0V VOUT......................................................-0.3V to +6.0V IOUT....................................................................100mA Storage Temperature........................-65˚C to +150˚C Power Dissipation Per Package 10-pin mSOIC (derate 8.84mW/OC above +70OC)..................720mW Junction Temperature........................................125˚C SPECIFICATIONS VIN = +2.75 to +5.5V, fCLK = 32.768kHz, CIN = 4.7µF (ceramic), CF1 = CF2 = COUT = 2.2µF, (ESR = 0.03 Ω) and TAMB = -40°C to +85°C unless otherwise noted. PARAMETER Supply Voltage, VIN Quiescent Current, IQ fPUMP = fCLK/4 fCLK=fPUMP fPUMP = fCLK/8 TYP. 3.6 175 230 580 In-Rush Current into VIN, INRUSH Off Current, IOFF Input Clock Freq., fCLK 2.7V V IN 5.5V, NOTE 1 500 Pump Frequency, fPUMP fCLK Input Threshold Voltage VIL VIH Input Current IIN(low) IIN(high) Mode Transition Voltage, CONDITIONS MIN. 2.75 clock not present Operational (supplied externally) 8 32.768 MAX. 5.5 250 300 1500 UNITS V µA mA 15 µA kHz C/4pin input Cx8pin input no input X X Present Low Low Present High Low Present X High High Low Low High Low High High High Low Digital inputs = fCLK, fCLK/4, fCLK x 8 0 32.768 8.192 262.140 16 130 0 kHz 0.4 V 0.1 1.0 10 10 µA 3.70 3.70 3.85 3.85 V 1.3 Digital inputs = fCLK, fCLK/4, fCLK x 8 X1.5 to X2, VIN falling fpump = fCLK/4, ILOAD = 1mA fpump, fCLK, ILOAD = 5mA 3.55 3.55 Hysteresis for Mode Transition Voltage VIN rising to VIN falling 50 mVpp Transient Response: Max. Transient Amplitude; t=5µs ILOAD fPUMP 100µA to 2mA 8.192kHz 2mA to 20mA 32.768kHz 20mA to 50mA 262.14kHz 1.5 1.5 1.5 % Rev:A Date: 11/20/03 SP6681 High Efficiency Boost Charge Pump Regulator 2 © Copyright 2002 Sipex Corporation SPECIFICATIONS (CONT) PRELIMINARY INFORMATION VIN = +2.75 to +5.5V, fCLK = 32.768kHz, CIN = 4.7µF (ceramic), CF1 = CF2 = COUT = 2.2µF, (ESR = 0.03 Ω) and TAMB = -40°C to +85°C unless otherwise noted. PARAMETER Output Resistance, ROUT Average Output Voltage: Ave VOUT Power Efficiency PEFF CONDITIONS Mode: X2, VIN=3.85V ILOAD=2mA fPUMP=8.192kHz 10mA 32.768kHz 50mA 262.14kHz fPUMP=8.192kHz; ILOAD=2mA VIN Mode 3.0V X2 3.55V X2 3.85V X1.5 3.5V X1.5 fPUMP=32.768kHz; ILOAD=10mA VIN Mode 3.0V X2 3.55V X2 3.85V X1.5 3.5V X1.5 fPUMP=262.14kHz; ILOAD=50mA VIN Mode 3.0V X2 3.55V X2 3.85V X1.5 3.5V X1.5 fPUMP=8.192kHz; ILOAD=2mA Mode VIN 3.0V X2 3.55V X2 3.85V X1.5 3.5V X1.5 fPUMP=32.768kHz; ILOAD=10mA VIN Mode 3.0V X2 3.55V X2 3.85V X1.5 3.5V X1.5 fPUMP=262.14kHz; ILOAD=50mA VIN Mode 3.0V X2 3.55V X2 3.85V X1.5 3.5V X1.5 MIN. TYP. MAX. UNITS 60 20 12.5 4.8 4.8 4.8 4.8 5.0 5.0 5.0 5.0 5.2 5.2 5.2 5.2 V 4.8 4.8 4.8 4.8 5.0 5.0 5.0 5.0 5.2 5.2 5.2 5.2 V 4.8 4.8 4.8 4.8 5.0 5.0 5.0 5.0 5.2 5.2 5.2 5.2 V 93 80 92 54 % 96 80 92 57 % 92 81 91 60 % NOTE 1: FCLK applied 10ms after VIN is present. Rev:A Date: 11/20/03 SP6681 High Efficiency Boost Charge Pump Regulator 3 © Copyright 2002 Sipex Corporation PRELIMINARY INFORMATION PINOUT VOUT 1 CF1P 2 VIN 10 CF2P 9 CF1N 3 8 GND C/4 4 7 CF2N Cx8 5 6 CLK SP6681 PIN ASSIGNMENTS to drive the frequency of the charge pump. Logic low inputs on the C/4 and Cx8 pins sets the internal charge pump frequency according to Table 1. Shutdown mode for the device is set when there is no clock signal present on this input pin, or when it is pulled to ground. Pin 1— VOUT — 5.0V regulated charge pump. Pin 2 — CF1P — Positive terminal to the charge pump flying capacitor, CF1. Pin 3 — VIN — Input pin for the +2.7V to +5.5V supply voltage. Pin 7 — CF2N — Negative terminal to the charge pump flying capacitor, CF2. Pin 4 — C/4 — This is a control line for the internal charge pump frequency. When this control line is forced to a logic high, the internal charge pump frequency is set to 1/4 of the CLK frequency, provided that Cx8 is low. Pin 8 — GND — Ground reference. Pin 9 — CF2P — Positive terminal to the charge pump flying capacitor, CF2. Pin 5 — Cx8 — This is a control line for the internal charge pump frequency. When this control line is forced to a logic high, the internal charge pump frequency is set to x8 of the CLK frequency. Pin 10 — CF1N — Negative terminal to the charge pump flying capacitor, CF2. Pin 6 — CLK — 32.768kHz Clock. Connect this input pin to an external 32.768kHz clock Rev:A Date: 11/20/03 SP6681 High Efficiency Boost Charge Pump Regulator 4 © Copyright 2002 Sipex Corporation PRELIMINARY INFORMATION DESCRIPTION THEORY OF OPERATION The SP6681 device is a regulated CMOS charge pump voltage converter that can be used to convert a +2.7V to +5.5V input voltage to a nominal +5.0V output. These devices are ideal for cellular phone designs involving batterypowered and/or board level voltage conversion applications. There are seven major circuit blocks for the SP6681 device. Refer to Figure 1. An external clock signal with a frequency of 32.768kHz nominal is required for device operation. A designer can set the SP6681 device to operate at 3 different charge pump frequencies: 8.192kHz (fINPUT / 4), 32.768kHz (fINPUT x 1), and 262.14kHz (fINPUT x 8). The three frequencies correspond to three nominal load current ranges: 2mA, 20mA, and 50mA, respectively. The SP6681 device optimizes for high power efficiency with a low quiescent current of 175µA at 8.198kHz, 230µA at 32.768kHz, and 800µA at 262.14kHz. When there is no external clock signal input, the device is in a low-power shutdown mode drawing 4.4µA (typical) current. 2) The Clock Manager accepts the digital input voltage levels (including the input clock) and translates them to VCC and 0V. It also determines if a clock is present in which case the device is powered up. If the CLK input is left floating or pulled near ground, the device shuts down and VIN is shorted to VOUT. The worst case digital low is 0.4V and the worst case digital high is 1.3V. This block contains a synthesizer that generates the internal pump clock which runs at the frequency controlled with the C/4 and Cx8 logic pins. 1) The Voltage Reference contains a band gap and other circuits that provide the proper current biases and voltage references used in the other blocks. 3) The Charge Pump Switch Configuration Control determines the pump configuration depending upon VIN as described earlier and programs the Clock Phase Control. For an input supply voltage from +2.7V to +3.7V, an X2 doubling architecture is enabled. This mode requires one flying capacitor and one output capacitor. For an input supply voltage greater than +3.7V up to +5.5V, an X1.5 multiplier architecture is enabled. This mode requires two flying capacitors and one output capacitor. The SP6681 device is ideal for designs using +3.6V lithium ion batteries such as cell phones, PDAs, medical instruments, and other portable equipment. For designs involving power sources above +2.7V up to +5.5V, the internal charge pump switch architecture dynamically selects an operational mode that optimizes efficiency. The SP6681 device regulates the maximum output voltage to +5.0V. VIN 3 Voltage Reference CLK C/4 Cx8 6 4 5 Clock Manager Charge Pump Switch Configuration Control Clock Phase Reference CF1P SP6681 Drivers CF1N CF1 CF2P Charge Pump CF2N Switches CF2 VOUT VOUT Control 8 COUT GND Figure 1. Internal Block Diagram of the SP6681 Rev:A Date: 11/20/03 SP6681 High Efficiency Boost Charge Pump Regulator 5 © Copyright 2002 Sipex Corporation PRELIMINARY INFORMATION 4) The Clock Phase Control accepts the clock and mode control generated by the Clock Manager and the Charge Pump Switch Configuration Control. This block then provides several clock phases going to the Drivers block. If VIN is above 3.70V, the device is reconfigured and multiplies the input by a factor of 1.5. This mode reduces the current drawn from the supply and hence increases the power efficiency. As the output reaches 5.0V, the charge transfer to the load capacitor is truncated. 5) The VOUT Control regulates the Clock Phase Control to ensure VOUT is regulated to 5.0V. APPLICATION INFORMATION 6) The Drivers block drives the clock phase information to the gates of the large pump transistors. Refer to Figure 3 for a typical SIM card application circuit with the SP6681. Oscillator Control 7) The Charge Pump Switch block contains the large transistors that transfer charge to the fly and load capacitors. The external clock frequency required to drive the internal charge pump oscillator is 32.768kHz (nominal) at the CLK pin. When there is no clock signal present at the CLK pin, the SP6681 device is in a low-power shutdown mode. In normal operation of the device VIN is connected between +2.7 and 5.5V. Refer to Figure 2 for a typical application circuit. When no clock is present (CLK is floating or near ground) the device is in shutdown and the output is connected to the input. This shutdown feature will work either in start up or after the device is pumping. Once a clock is present, the band gap is activated, but only if VIN > 2.3V. Otherwise the device remains in shutdown mode. Once the reference voltage is stable, the device begins the pumping operation. C/4 and Cx8 are two control lines for the internal charge pump oscillator. When the C/4 control line is forced to a logic high and the Cx8 control line is at a low, the internal charge pump oscillator is set to 8.192kHz. When both the C/4 and Cx8 control lines are at a logic low, the internal charge pump oscillator is set to the input clock signal, 32.768kHz. When the C/4 control line is forced to a logic high, the internal charge pump oscillator is set to 262.14kHz. If VIN < 3.70V, the device is configured as a doubler. However, as the output reaches 5.0V, the doubler action is truncated. CF1 = 2.2µF 5.0V VOUT COUT = 2.2µF 1 CF1P 2.7V to 5.5V VIN CF2P CF1N 9 2 SP6681 GND 3 8 C/4 4 Cx8 5 Frequency Control Inputs CIN = 4.7µF 10 7 6 CF2 = 2.2µF CF2N CLK Input Clock Figure 2. Typical Application for the SP6681 Rev:A Date: 11/20/03 SP6681 High Efficiency Boost Charge Pump Regulator 6 © Copyright 2002 Sipex Corporation 2.2µF PRELIMINARY INFORMATION 2.2µF CF1N CF1P 2 VIN CF2P 9 CF2N 10 7 3 1 SP6681 4 +3.6V Lithium-Ion Battery 5 6 VOUT 5.0V output 8 4.7µF GND 2.2µF C/4 Cx8 CLK Figure 3. Typical SIM Card Application Circuit for the SP6681 Capacitor Selection Any standard CMOS logic output is suitable for driving the C/4 or Cx8 control lines as long as logic low is less than 0.4V and logic high is greater than 1.3V. CLK pin C/4 pin Cx8 pin fPUMP not present X X 0 32.768kHz low low 32.768kHz 32.768kHz low high 262.14kHz 32.768kHz high low 8.192kHz 32.768kHz high high 262.14kHz In order to maintain the lowest output resistance, input ripple voltage and output ripple voltage, multi-layer ceramic capacitors with inherently low ESR are recommended. Refer to Table 2 for some suggested low ESR capacitors. Tables of output resistance and ripple voltages for a variety of input, output and pump capacitors are included here to use as a guide in capacitor selection. Measured conditions are with CLK = 32kHz, 5mA output load and all capacitors are 2.2uF except when stated otherwise. A DC power supply with added 0.25ohm output ESR was used to simulate a Lithium Ion Battery as shown in figure 4. Table 1. Control Line Logic for the Internal Charge Pump Oscillator Efficiency Board Layout PC board layout is an important design consideration to mitigate switching current effects. High frequency operation makes PC layout important for minimizing ground bounc and noise. Components should be place as close to the IC as possible with connections made through short, low impedance traces. To maximize output ripple voltage, use a ground plane and solder the IC's GND pin directly to the ground plane. Power efficiency with the SP6681 charge pump regulator is improved over standard charge pumps doubler circuits by the inclusion of an 1.5X output mode, as described in the Theory of Operation section. The net result is an increase in efficiency at battery inputs greater than 3.7 to 3.8V where the SP6681 switches to the 1.5X mode. + Power Supply HP3631A 1000µF 0.25ohm 0.75” Leads VIN (p-p) SP6681 EvBd 2.2µF Caps VOUT (p-p) - Figure 4. Capacitor Selection Test Circuit Rev:A Date: 11/20/03 SP6681 High Efficiency Boost Charge Pump Regulator 7 © Copyright 2002 Sipex Corporation PRELIMINARY INFORMATION MANUFACTURER / TELEPHONE # PART NUMBER CAPACITANCE / VOLTAGE MAX ESR @ 100kHz CAPACITOR SIZE / TYPE TDK / 847-803-6100 C2012X5R1A225K 2.2µF / 10V 0.030Ω 0805 / X5R TDK / 847-803-6100 C3216X5R1C475K 4.7µF / 10V 0.020Ω 1206 / X5R AVX / 843-448-9411 1206ZC225K 2.2µF / 10V 0.030Ω 1206 / X7R Taiyo Yuden / 847-925-0888 LMK212BJ225MG 2.2µF / 10V 0.030Ω 0805 / X5R Taiyo Yuden / 847-925-0888 LMK316BJ475ML 4.7µF / 10V 0.020Ω 1206 / X7R Table 2. Suggested Low ESR Cermic Surface Mount Capacitors. The SP6681 circuit shown in figure 5 acts as a 3.3V in to 5V out for biasing the two 5V Logic Level N-channel MOSFETs used in a stepdown DC/DC converter. The high current switching path is from the +3.3V bus through the N-channel MOSFETs and inductor L1 to the output capacitors. To fully enhance LogicLevel N-channel MOSFETs, +5V is needed from the SP6681 output to the SP6120 VCC pin, which supplies the low-side MOSFET MN1 with a 0V to 5V gate pulse through the GL pin. For the top-side MOSFET MN2 (which has a floating gate driver biased at the BST pin), the boost pin BST is charge pumped up from the 0 to 3.3V switching at the switch node pin SWN, with an additional 5V from SP6681 output, through the DBST diode to a total of 8.3V when the SWN is at 3.3V, or a total of 5V from gate to source to fully enhance the MOSFET MN2. For a more detailed schematic of a step-down DC/ DC converter, see the SP6120 datasheet. 3.3V VIN DBST +5VOUT VCC 2.2µF SP6120 CIN CBST BST GH MN2 2.2µF VFB 1 4.7µF VOUT SP6681 CF2P 10 2 CF1P 3 VIN 4 CD4 CF2N 5 Cx8 CLK CF1N 9 PGND 1.9V 1A to 7A SWN GL MN1 2.2µF VOUT L1 RF GND 8 COUT 7 RI 6 130kHz Internal Clock Figure 5. SP6681 Circuit as a 3.3V to 5.0V Boost for 5V N-Channel MOSFETs in Buck DC/DC Converter Circuit. Rev:A Date: 11/20/03 SP6681 High Efficiency Boost Charge Pump Regulator 8 © Copyright 2002 Sipex Corporation PRELIMINARY INFORMATION PACKAGE: 10-PIN MSOP (ALL DIMENSIONS IN MILLIMETERS) D e1 Ø1 E/2 R1 R E1 E Gauge Plane L2 Ø1 Seating Plane Ø L L1 1 2 e Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2) Dimensions in (mm) 10-PIN MSOP JEDEC MO-187 (BA) Variation MIN NOM MAX A - - 1.1 A1 0 - 0.15 A2 0.75 b 0.17 - 0.27 c 0.08 - 0.23 D 0.85 0.95 (b) WITH PLATING 3.00 BSC E 4.90 BSC E1 3.00 BSC e 0.50 BSC e1 c 2.00 BSC L 0.4 0.60 0.80 L1 - 0.95 - L2 - 0.25 - N - 10 - R 0.07 - - R1 0.07 - - Ø 0º Ø1 0º BASE METAL D A2 A 8º - b 15º A1 1 Rev:A Date: 11/20/03 SP6681 High Efficiency Boost Charge Pump Regulator 9 © Copyright 2002 Sipex Corporation PRELIMINARY INFORMATION ORDERING INFORMATION Model Temperature Range Package Type SP6681EU .............................................. -40˚C to +85˚C ........................................ 10-pin ΜSOP SP6681EU/TR ........................................ -40˚C to +85˚C ............... (tape and reel) 10-pin ΜSOP Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. Rev:A Date: 11/20/03 SP6681 High Efficiency Boost Charge Pump Regulator 10 © Copyright 2002 Sipex Corporation