SL74LS161 Synchronous 4 Bit Counters; Binary, Direct Reset This synchronous, presettable counter features an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change conicident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positivegoing) edge of the clock input wave form. This counter is fully programmable; that is the outputs may be preset to either level. As presetting is synchronous setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishiing this function are two counter-enable inputs and a ripple carry output. Both countenable inputs (ENABLE P and ENABLE T) must be high to count, and ENABLE T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high level portion of the QA output. The high-level overflow ripple carry pulse can be enable successive cascaded stages. Transitions at the ENPor ENT are allowed regardless of the level of the clock input. • Internal Look-Ahead for Fast Counting • Carry Output for n-Bit Cascading • Synchronous Counting • Synchronously Programmable • Load Control Line • Diode-Clamped Inputs ORDERING INFORMATION SL74LS161N Plastic SL74LS161D SOIC TA = 0° to 70° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND SLS System Logic Semiconductor SL74LS161 FUNCTION TABLE Inputs Outputs Reset Load Enable P Enable T Clock Q0 Q1 Q2 Q3 Function L X X X X L L L L Reset to “0” H L X X P0 P1 P2 P3 Preset Data H H X L No change No count H H L X No change No count H H H H Count up Count H X X X No change No count X=don’t care P0,P1,P2,P3 = logic level of Data inputs Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3 MAXIMUM RATINGS * Symbol Parameter Value Unit VCC Supply Voltage 7.0 V VIN Input Voltage 7.0 V VOUT Output Voltage 5.5 V Tstg Storage Temperature Range -65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 5.25 V VCC Supply Voltage 4.75 VIH High Level Input Voltage 2.0 VIL Low Level Input Voltage 0.8 V IOH High Level Output Current -0.4 mA IOL Low Level Output Current 8.0 mA fclock Clock frequency 0 25 MHz tw(clock) Width of clock pulse 25 ns tw(reset) Width of reset pulse 20 ns tsu Setup time Data inputs P0, P1, P2, P3 20 Enable P or T 20 Load 20 th Hold time at any input 3 TA Ambient Temperature Range 0 SLS V ns ns +70 °C System Logic Semiconductor SL74LS161 DC ELECTRICAL CHARACTERISTICS over full operating conditions Guaranteed Limit Symbol Parameter Test Conditions Min Max Unit -1.5 V VIK Input Clamp Voltage VCC = min, IIN = -18 mA VOH High Level Output Voltage VCC = min, IOH = -0.4 mA VOL Low Level Output Voltage VCC = min, IOL = 4 mA 0.4 VCC = min, IOL = 8 mA 0.5 VCC = max Data or enable P 20 VIN =2.7 V Load, clock or enable T 40 Reset 20 VCC = max Data or enable P 0.1 VIN =7.0 V Load, clock or enable T 0.2 Reset 0.1 VCC = max Data or enable P -0.4 VIN =0.4 V Load, clock or enable T Reset -0.8 IIH IIL High Level Input Current Low Level Input Current IO Output Short Circuit Current VCC = max, VO = 0 V (Note 1) ICC Supply Current All outputs high All outputs low 2.7 -20 V V µA mA mA -100 mA VCC = max (Note 2) 31 mA VCC = max (Note 3) 32 Note 1: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 2: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open. Note 3: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open. SLS System Logic Semiconductor SL74LS161 AC ELECTRICAL CHARACTERISTICS (TA=25°C, VCC = 5.0 V, CL = 15 pF, RL = 2 kΩ, t r =15 ns, tf = 6.0 ns) Symbol Parameter Min Max Unit tPLH Propagation Delay, Clock to Ripple carry 35 ns tPHL Propagation Delay, Clock to Ripple carry 35 ns tPLH Propagation Delay, Clock (load input high) to Any Q 24 ns tPHL Propagation Delay, Clock (load input high) to Any Q 27 ns tPLH Propagation Delay, Clock (load input low) to Any Q 24 ns tPHL Propagation Delay, Clock (load input low) to Any Q 27 ns tPLH Propagation Delay, Enable T to Ripple carry 14 ns tPHL Propagation Delay, Enable T to Ripple carry 14 ns tPHL Propagation Delay, Reset to Any Q 28 ns Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform Figure 4. Switching Waveform SLS System Logic Semiconductor SL74LS161 NOTES A. CL includes probe and jig capacitance. B. All diodes are 1N916 or 1N3064. Figure 5. Test Circuit Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to binary twelve. 3. Count to thirteen, fourteen, fifteen, zero, one, and two. 4. Inhibit. Figure 7. Timing Diagram SLS System Logic Semiconductor