SN8P1602B 8-Bit Micro-Controller SN8P1602B USER’S MANUAL General Release Specification SONiX 8-Bit Micro-Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part. SONiX TECHNOLOGY CO., LTD Version 1.1 SN8P1602B 8-Bit Micro-Controller AMENDENT HISTORY Version Date Description VER 1.0 Sep. 2003 V1.0 First Issue VER 1.1 Sep. 2003 1. Remove approval sheet 2. Remove PCB layout notice section. 3. Modify the description of code option notice. 4. Add the description of PEDGE register. 5. Modify the description of INTRQ register. 6. Change operating voltage range from “2.2V ~ 5.5V” to “2.4V ~ 5.5V” at Fosc=3.579545 MHz, ambient temperature = 25°C. SONiX TECHNOLOGY CO., LTD Version 1.1 SN8P1602B 8-Bit Micro-Controller Table of Content AMENDENT HISTORY ............................................................................................................................... 2 1 PRODUCT OVERVIEW................................................................................................................. 8 GENERAL DESCRIPTION........................................................................................................................... 8 UPGRADE FROM SN8P1602/SN8P1603/SN8P1602A............................................................................... 8 FEATURES .................................................................................................................................................... 9 SELECTION TABLE..................................................................................................................................... 9 SYSTEM BLOCK DIAGRAM.................................................................................................................... 10 PIN ASSIGNMENT ..................................................................................................................................... 11 PIN DESCRIPTIONS .................................................................................................................................. 12 PIN CIRCUIT DIAGRAMS ........................................................................................................................ 12 2 CODE OPTION TABLE ............................................................................................................... 13 SN8P1602B .................................................................................................................................................. 13 3 ADDRESS SPACES ....................................................................................................................... 14 PROGRAM MEMORY (ROM)................................................................................................................... 14 OVERVIEW .............................................................................................................................................. 14 USER RESET VECTOR ADDRESS (0000H) ........................................................................................... 15 INTERRUPT VECTOR ADDRESS (0008H) ............................................................................................ 15 CHECKSUM CALCULATION ................................................................................................................. 17 GENERAL PURPOSE PROGRAM MEMORY AREA.............................................................................. 18 LOOK-UP TABLE DESCRIPTION.......................................................................................................... 18 JUMP TABLE DESCRIPTION................................................................................................................. 20 DATA MEMORY (RAM) ........................................................................................................................... 22 OVERVIEW .............................................................................................................................................. 22 WORKING REGISTERS............................................................................................................................. 23 Y, Z REGISTERS ...................................................................................................................................... 23 SONiX TECHNOLOGY CO., LTD Page 3 Version 1.1 SN8P1602B 8-Bit Micro-Controller R REGISTERS........................................................................................................................................... 24 PROGRAM FLAG ....................................................................................................................................... 25 RESET/WAKEUP FLAG .......................................................................................................................... 25 CARRY FLAG ........................................................................................................................................... 25 DECIMAL CARRY FLAG......................................................................................................................... 25 ZERO FLAG ............................................................................................................................................. 25 ACCUMULATOR ....................................................................................................................................... 26 STACK OPERATIONS ............................................................................................................................... 27 OVERVIEW .............................................................................................................................................. 27 STACK REGISTERS ................................................................................................................................. 28 STACK OPERATION EXAMPLE............................................................................................................. 29 PROGRAM COUNTER............................................................................................................................... 29 ONE ADDRESS SKIPPING ..................................................................................................................... 30 MULTI-ADDRESS JUMPING ................................................................................................................. 31 4 ADDRESSING MODE................................................................................................................... 32 OVERVIEW................................................................................................................................................. 32 IMMEDIATE ADDRESSING MODE....................................................................................................... 32 DIRECTLY ADDRESSING MODE .......................................................................................................... 32 INDIRECTLY ADDRESSING MODE ...................................................................................................... 32 5 SYSTEM REGISTER .................................................................................................................... 33 OVERVIEW................................................................................................................................................. 33 SYSTEM REGISTER ARRANGEMENT (BANK 0)................................................................................. 33 BYTES of SYSTEM REGISTER ................................................................................................................ 33 BITS of SYSTEM REGISTER.................................................................................................................... 34 6 POWER ON RESET ...................................................................................................................... 35 OVERVIEW................................................................................................................................................. 35 EXTERNAL RESET DESCRIPTION......................................................................................................... 36 LOW VOLTAGE DETECTOR (LVD) DESCRIPTION ............................................................................ 37 SONiX TECHNOLOGY CO., LTD Page 4 Version 1.1 SN8P1602B 8-Bit Micro-Controller 7 OSCILLATORS ............................................................................................................................. 38 OVERVIEW................................................................................................................................................. 38 CLOCK BLOCK DIAGRAM .................................................................................................................... 38 OSCM REGISTER DESCRIPTION.......................................................................................................... 39 EXTERNAL HIGH-SPEED OSCILLATOR .............................................................................................. 40 OSCILLATOR MODE CODE OPTION ................................................................................................... 40 OSCILLATOR DEVIDE BY 2 CODE OPTION ....................................................................................... 40 OSCILLATOR SAFE GUARD CODE OPTION....................................................................................... 40 SYSTEM OSCILLATOR CIRCUITS ......................................................................................................... 41 External RC Oscillator Frequency Measurement .................................................................................... 42 INTERNAL LOW-SPEED OSCILLATOR ................................................................................................ 43 SYSTEM MODE DESCRIPTION............................................................................................................... 44 OVERVIEW .............................................................................................................................................. 44 NORMAL MODE...................................................................................................................................... 44 SLOW MODE ........................................................................................................................................... 44 GREEN MODE......................................................................................................................................... 44 POWER DOWN MODE ........................................................................................................................... 44 SYSTEM MODE CONTROL...................................................................................................................... 45 SYSTEM MODE SWITCHING ................................................................................................................. 46 WAKEUP TIME .......................................................................................................................................... 47 OVERVIEW .............................................................................................................................................. 47 HARDWARE WAKEUP............................................................................................................................ 47 EXTERNAL WAKEUP TRIGGER CONTROL ......................................................................................... 48 8 TIMERS .......................................................................................................................................... 49 WATCHDOG TIMER (WDT)..................................................................................................................... 49 TIMER0 (TC0) ............................................................................................................................................. 50 OVERVIEW .............................................................................................................................................. 50 TC0M MODE REGISTER ........................................................................................................................ 51 TC0C COUNTING REGISTER ................................................................................................................ 52 TC0 TIMER OPERATION SEQUENCE .................................................................................................. 53 SONiX TECHNOLOGY CO., LTD Page 5 Version 1.1 SN8P1602B 8-Bit Micro-Controller 9 INTERRUPT................................................................................................................................... 54 OVERVIEW................................................................................................................................................. 54 INTEN INTERRUPT ENABLE REGISTER .............................................................................................. 55 INTRQ INTERRUPT REQUEST REGISTER............................................................................................ 55 INTERRUPT OPERATION DESCRIPTION.............................................................................................. 56 GIE GLOBAL INTERRUPT OPERATION............................................................................................... 56 INT0 (P0.0) INTERRUPT OPERATION .................................................................................................. 57 TC0 INTERRUPT OPERATION .............................................................................................................. 58 MULTI-INTERRUPT OPERATION ......................................................................................................... 59 10 I/O PORT ............................................................................................................................ 60 OVERVIEW................................................................................................................................................. 60 I/O PORT FUNCTION TABLE................................................................................................................... 61 I/O PORT MODE......................................................................................................................................... 61 I/O PULL UP REGISTER............................................................................................................................ 62 I/O PORT DATA REGISTER ..................................................................................................................... 62 11 CODING ISSUE ................................................................................................................. 63 TEMPLATE CODE ..................................................................................................................................... 63 PROGRAM CHECK LIST .......................................................................................................................... 67 12 13 INSTRUCTION SET TABLE........................................................................................... 68 ELECTRICAL CHARACTERISTIC .............................................................................. 69 ABSOLUTE MAXIMUM RATING............................................................................................................ 69 SONiX TECHNOLOGY CO., LTD Page 6 Version 1.1 SN8P1602B 8-Bit Micro-Controller STANDARD ELECTRICAL CHARACTERISTIC.................................................................................... 69 CHARACTERISTIC GRAPHS ................................................................................................................... 70 14 PACKAGE INFORMATION ........................................................................................... 73 P-DIP 18 PIN................................................................................................................................................ 73 SOP 18 PIN................................................................................................................................................... 74 SSOP 20 PIN ................................................................................................................................................ 75 SONiX TECHNOLOGY CO., LTD Page 7 Version 1.1 SN8P1602B 8-Bit Micro-Controller 1 PRODUCT OVERVIEW GENERAL DESCRIPTION The SN8P1602B is an 8-bit micro-controller utilized CMOS technology and featured with low power consumption and high performance by its unique electronic structure. SN8P1602B is designed with the excellent IC structure including the program memory up to 1K-word OTP ROM, data memory of 48-bytes RAM, one 8-bit timer (TC0), a watchdog timer, two interrupt sources (TC0, INT0), and 4-level stack buffers. Besides, user can choose desired oscillator configuration for the controller. There are four external oscillator configurations to select for generating system clock, including High/Low speed crystal, ceramic resonator or cost-saving RC. SN8P1602B also includes an internal RC oscillator for slow mode controlled by programming. UPGRADE FROM SN8P1602/SN8P1603/SN8P1602A Item Standby Current at 3V SN8P1602B <1uA SN8P1602A 3 ~ 4uA SN8P1602 3 ~ 4uA SN8P1603 70uA Pull-up resistor Yes Yes - - Power On Reset / Brown Out Reset Excellent Excellent - Good High Clock High Clock Internal RC Internal RC High Clock High Clock Watchdog Clock Source Fixed at Internal RC and Internal RC Clock Always Enable Yes Yes - - Green Mode Yes Yes - - Falling Falling Watchdog Clock Source P0.0 Interrupt Edge Falling/Rising/Both Falling/Rising/Both Port 1 Wakeup Level Change Level Change Low Level Low Level TC0 Event Counter Yes Yes - - External Reset Recommend Value 20K / 0.1uF 20K / 0.33uF 20K / 0.1uF 20K / 0.1uF Power On Delay at 4Mhz ~ 200ms ~ 200ms ~ 70ms ~ 70ms Low Power code option Yes Yes - - LVD 1.8V Always ON 1.8V Always ON 2.4V ON/OFF 2.4V Always ON SONiX TECHNOLOGY CO., LTD Page 8 Version 1.1 SN8P1602B 8-Bit Micro-Controller FEATURES ♦ Memory configuration OTP ROM size: 1K * 16-bit. RAM size: 48 * 8-bit. ♦ Two interrupt sources One internal interrupt: TC0. One external interrupt: INT0. ♦ I/O pin configuration Input only: P0 Bi-directional: P1, P2, Wakeup: P0, P1 Pull-up resistors: P0, P1, P2 External interrupt: P0 ♦ Four levels stack buffer. ♦ Dual clock system offers four operating modes External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and low clock active Slow mode: Low clock only Sleep mode: Both high and low clock stop Green mode: Periodical wakeup by timer. Package ♦ ♦ On chip watchdog timer. One 8-bit timer counters. ♦ 57 powerful instructions Four clocks per instruction cycle All of instructions are one word length. Most of instructions are one cycle only. Maximum instruction cycle is two. All ROM area JMP instruction. All ROM area lookup table function (MOVC) ♦ P-DIP18, SOP18, SSOP20. SELECTION TABLE CHIP SN8P1602B ROM RAM Stack 1K*16 48 4 Timer I/O TC0 TC1 V - 14 Green PWM Wakeup Package Mode Buzzer Pin no. V - 6 DIP18/SOP18 /SSOP20 SONiX TECHNOLOGY CO., LTD Page 9 Version 1.1 SN8P1602B 8-Bit Micro-Controller SYSTEM BLOCK DIAGRAM SN8P1602B PC H-OSC IR Internal RC POR ROM FLAGS TIMING GENERATOR ALU Watch Dog RAM ACC SYSTEM REGISTER INTERRUPT CONTROL TIMER & COUNTER PORT 0 PORT 1 SONiX TECHNOLOGY CO., LTD PORT 2 Page 10 Version 1.1 SN8P1602B 8-Bit Micro-Controller PIN ASSIGNMENT OTP Type: SN8P1602BP (P-DIP 18 pins) SN8P1602BS (SOP 18 pins) P1.2 P1.3 INT0/P0.0 RST/VPP VSS P2.0 P2.1 P2.2 P2.3 1 U 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 SN8P1602BP SN8P1602BS P1.1 P1.0 XIN XOUT/P1.4 VDD P2.7 P2.6 P2.5 P2.4 P1.2 P1.3 INT0/P0.0 RST/VPP VSS VSS P2.0 P2.1 P2.2 P2.3 1 U 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 SN8P1602BX P1.1 P1.0 XIN XOUT/P1.4 VDD VDD P2.7 P2.6 P2.5 P2.4 SN8P1602BX (SSOP 20 pins) SONiX TECHNOLOGY CO., LTD Page 11 Version 1.1 SN8P1602B 8-Bit Micro-Controller PIN DESCRIPTIONS SN8P1602B PAD NAME VDD, VSS RST/VPP XIN XOUT/P1.4 P0.0 / INT0 P1.0 ~ P1.4 P2.0 ~ P2.7 TYPE DESCRIPTION P Power supply input pins. Place the 0.1µF bypass capacitor between the VDD and VSS pin. RST: System reset input pin. Schmitt trigger structure, low active, normal stay to I, P “high”. VPP: OTP programming pin. I External oscillator input pin. RC mode input pin. I/O External oscillator output pin. In RC mode is P1.4 I/O. I Port 0.0 and shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up resistors. I/O Port 1.0~Port 1.4 bi-direction pins / Built-in pull-up resistors. I/O Port 2.0~Port 2.7 bi-direction pins / Built-in pull-up resistors. PIN CIRCUIT DIAGRAMS SN8P1602B Port1~Port2 structure Port0 structure PUR PUR PnM, PUR PUR Pin PnM Pin Int. bus Latch PnM Note: All of the latch output circuits are push-pull structures. SONiX TECHNOLOGY CO., LTD Page 12 Version 1.1 SN8P1602B 8-Bit Micro-Controller 2 CODE OPTION TABLE SN8P1602B Code Option High_Clk High_Clk / 2 Content RC 32K X’tal 12M X’tal 4M X’tal Enable Disable Enable OSG Watch_Dog Low Power Noise Filter Security INT_16K_RC Disable Enable Disable Enable Disable Enable Disable Enable Disable Always_ON By_CPUM Function Description Low cost RC for external high clock oscillator Low frequency, power saving crystal (e.g. 32.768K) for external high clock oscillator High speed crystal /resonator (e.g. 12M) for external high clock oscillator Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator External high clock divided by two, Fosc = high clock / 2 Fosc = high clock Enable Oscillator Safe Guard function to enhance noise immunity performance. Disable Oscillator Safe Guard function Enable Watch Dog function Disable Watch Dog function Enable Low Power function to save Operating current Disable Low Power function Enable Noise Filter function to enhance noise immunity performance Disable Noise Filter function Enable ROM code Security function Disable ROM code Security function Force Watch Dog Timer clock source come from INT 16K RC. Also INT 16K RC never stop both in power down and green mode that means Watch Dog Timer will always enable both in power down and green mode. Enable or Disable internal 16K(at 3V) RC clock by CPUM register Table 2-1 SN8P1602B Code Option Table This table is for design guidance, not tested or guaranteed. Some values presented are outside specified operating range. This is for information only and devices are guaranteed to operate properly only within the specified range. Code Option Lowest Operation Voltage Enable Disable 4 MHz 16 MHz - Noise Filter/Low Power/OSG 2.2V 2.8V Noise Filter Low Power/OSG 2.2V 3.5V Low Power Noise Filter/OSG 2.2V 3.8V OSG Noise Filter/Low Power 2.2V 2.9V Table 2-2 SN8P1602B Minimum Working Voltage vs. Code Option and clock frequency Notice: Under high noisy environment, enable “Noise Filter”, “OSG” and disable “Low Power” is strongly recommended. The side effect is to increase the minimum working voltage if enables “Noise Filter”/“OSG”/ “Low Power” code option. (Please refer to Characteristic Graphs) Enable “Low Power” option will reduce operating current during the normal operating mode. If users select “32K X’tal” in “High_Clk” option, assembler will force “OSG” to be enabled. If users select “RC” in “High_Clk” option, assembler will force “High_Clk / 2” to be enabled. SONiX TECHNOLOGY CO., LTD Page 13 Version 1.1 SN8P1602B 8-Bit Micro-Controller 3 ADDRESS SPACES PROGRAM MEMORY (ROM) OVERVIEW The SN8P1602B provides the program memory up to 1024 * 16-bit to be addressed and is able to fetch instructions through 10-bit wide PC (Program Counter). It can look up ROM data by using ROM code registers (R, Y, Z). 1-word reset vector addresses 1-word interrupt vector addresses 1K words general purpose area 5-word reserved area All of the program memory is partitioned into three coding areas. The first area is located from 00H to 03H(The Reset vector area), the second area is a reserved area 04H ~07H, the 3rd area is for the interrupt vector and the user code area from 0008H to 03FEH/0FFEH. The address 08H is the interrupt enter address point. 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H . . 000FH 0010H 0011H . . 03FEH 03FFH SONiX TECHNOLOGY CO., LTD ROM Reset vector General purpose area User reset vector Jump to user start address Jump to user start address Jump to user start address Reserved Interrupt vector User interrupt vector User program General purpose area End of user program Reserved Page 14 Version 1.1 SN8P1602B 8-Bit Micro-Controller USER RESET VECTOR ADDRESS (0000H) A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. The following example shows the way to define the reset vector in the program memory. Programming Tip: Defining Reset Vector CHIP SN8P1602B ORG JMP . 0 START ORG 10H START: ; 0000H ; Jump to user program address. ; 0004H ~ 0007H are reserved ; 0010H, The head of user program. ; User program . . . . ENDP ; End of program INTERRUPT VECTOR ADDRESS (0008H) A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory. Programming Tip: Defining Interrupt Vector (Example 1) CHIP SN8P1602B .DATA .CODE PFLAGBUF ORG JMP . 0 START ; 0000H ; Jump to user program address. ; 0004H ~ 0007H are reserved ORG B0XCH B0MOV B0MOV . . B0MOV B0MOV B0XCH RETI 8 A, ACCBUF A, PFLAG PFLAGBUF, A ; Interrupt service routine ; B0XCH doesn’t change C, Z flag A, PFLAGBUF PFLAG, A A, ACCBUF START: . . JMP ; Save PFLAG register in a buffer ; Restore PFLAG register from buffer ; B0XCH doesn’t change C, Z flag ; End of interrupt service routine ; The head of user program. ; User program START ENDP SONiX TECHNOLOGY CO., LTD ; End of user program ; End of program Page 15 Version 1.1 SN8P1602B 8-Bit Micro-Controller Programming Tip: Defining Interrupt Vector (Example 2) CHIP SN8P1602B .DATA .CODE PFLAGBUF ORG JMP . 0 START ORG JMP 08 MY_IRQ ORG 10H START: . . . JMP ; 0008H, Jump to interrupt service routine address ; 0010H, The head of user program. ; User program START MY_IRQ: B0XCH B0MOV B0MOV . . B0MOV B0MOV B0XCH RETI ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved A, ACCBUF A, PFLAG PFLAGBUF, A A, PFLAGBUF PFLAG, A A, ACCBUF ENDP ; End of user program ;The head of interrupt service routine ; B0XCH doesn’t change C, Z flag ; Save PFLAG register in a buffer ; Restore PFLAG register from buffer ; B0XCH doesn’t change C, Z flag ; End of interrupt service routine ; End of program Remark: It is easy to understand the rules of SONIX program from demo programs given above. These points are as following: 1. The address 0000H is a “JMP” instruction to make the program starts from the beginning. 2. The 0004H~0007H are reserved. Users is NOT allow to use 0004H~0007H addresses. The default value might change from time to time during various production progress. We strongly suggest users DO NOT take this value into the Check Sum. For detailed information, please check the following Checksum Calculation section SONiX TECHNOLOGY CO., LTD Page 16 Version 1.1 SN8P1602B 8-Bit Micro-Controller CHECKSUM CALCULATION The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses (0004H~0007H and last address) when calculate the Checksum value. Example: The demo program shows user’s code MOV B0MOV MOV B0MOV CLR CLR how to avoid 0004H~0007H when calculated Checksum from 00H to the end of A,#END_USER_CODE$L END_ADDR1,A ;save low end address to end_addr1 A,#END_USER_CODE$M END_ADDR2,A ;save middle end address to end_addr2 Y ;set Y to 00H Z ;set Z to 00H @@: CALL MOVC B0BSET ADD MOV ADC JMP YZ_CHECK FC DATA1,A A,R DATA2,A END_CHECK INCMS JMP JMP Z @B Y_ADD_1 MOV CMPRS JMP MOV CMPRS JMP JMP A,END_ADDR1 A,Z AAA A,END_ADDR2 A,Y AAA CHECKSUM_END MOV CMPRS RET MOV CMPRS RET INCMS INCMS INCMS INCMS RET A,#04H A,Z ;call function of check yz value ; ;clear C flag ;add A to Data1 ;add R to Data2 ;check if the YZ address = the end of code AAA: ;Z=Z+1 ;if Z!= 00H calculate to next address ;if Z=00H increase Y END_CHECK: YZ_CHECK: A,#00H A,Y Z Z Z Z ;check if Z = low end address ;if Not jump to checksum calculate ;if Yes, check if Y = middle end address ;if Not jump to checksum calculate ;if Yes checksum calculated is done. ;check if YZ=0004H ;check if Z=04H ;if Not return to checksum calculate ;if Yes, check if Y=00H ;if Not return to checksum calculate ;if Yes, increase 4 to Z ;set YZ=0008H then return Y_ADD_1: INCMS NOP JMP Y ;increase Y @B ;jump to checksum calculate CHECKSUM_END: ………. ………. END_USER_CODE: SONiX TECHNOLOGY CO., LTD ;Label of program end Page 17 Version 1.1 SN8P1602B 8-Bit Micro-Controller GENERAL PURPOSE PROGRAM MEMORY AREA The ROM location 0009H~03FEH are used as general-purpose memory. The area is to store both instruction’s op-code and look-up table data. The SN8P1602B includes jump table function by using program counter (PC) and look-up table function by using ROM code registers (R, Y, Z). The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table function and look-up table function, the program counter can’t leap over the boundary by program counter automatically. Users need to modify the PCH value to “PCH+1” when the PCL overflows (from 0FFH to 000H). LOOK-UP TABLE DESCRIPTION In the ROM’s data lookup function, Y register is pointed to the bit 8~bit 15 and Z register to the bit 0~bit 7 data of ROM address. After MOVC instruction is executed, the low-byte data will be stored in ACC and high-byte data stored in R register. Example: To look up the ROM data located “TABLE1”. @@: TABLE1: B0MOV B0MOV MOVC Y, #TABLE1$M Z, #TABLE1$L INCMS JMP INCMS NOP Z @F Y MOVC . DW DW DW . 0035H 5105H 2012H ; To set lookup table1’s middle address ; To set lookup table1’s low address. ; To lookup data, R = 00H, ACC = 35H ; ; Increment the index address for next address ; Z+1 ; Not overflow ; Z overflow (FFH 00), Y=Y+1 ; ; ; To lookup data, R = 51H, ACC = 05H. ; ; To define a word (16 bits) data. ;“ ;“ CAUSION: The Y register will not increase automatically when Z register crosses boundary from 0xFF to 0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflows, Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users can omit “B0MOV X, #TABLE1$H”. SONiX ICE supports larger program memory addressing capability. Please be sure that X register is “0” to avoid unpredicted error in loop-up table operation. Example: INC_YZ Macro INC_YZ MACRO INCMS JMP INCMS NOP Z @F ; Z+1 ; Not overflow Y ; Y+1 ; Not overflow @@: ENDM SONiX TECHNOLOGY CO., LTD Page 18 Version 1.1 SN8P1602B 8-Bit Micro-Controller The other example of loop-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen. Example: Increase Y and Z register by B0ADD/ADD instruction B0MOV B0MOV Y, #TABLE1$M Z, #TABLE1$L ; To set lookup table’s middle address. ; To set lookup table’s low address. B0MOV B0ADD A, BUF Z, A ; Z = Z + BUF. B0BTS1 JMP INCMS NOP FC GETDATA Y ; Check the carry flag. ; FC = 0 ; FC = 1. Y+1. . 0035H 5105H 2012H ; ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 . . ; ; To define a word (16 bits) data. ;“ ;“ GETDATA: MOVC TABLE1: . DW DW DW SONiX TECHNOLOGY CO., LTD Page 19 Version 1.1 SN8P1602B 8-Bit Micro-Controller JUMP TABLE DESCRIPTION The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the value of the accumulator (A). When carry flag occurs after executing of “ADD PCL, A”, it will not affect PCH register. Users have to check if the jump table crosses over the ROM page boundary or the listing file generated by SONIX assembly software. We suggest users to place the jump table at the beginning of the program memory page (xx00H) to avoid errors to occur when editing the program. Example : ORG 0X0100 ; The jump table is from the head of the ROM boundary B0ADD JMP JMP JMP JMP PCL, A A0POINT A1POINT A2POINT A3POINT ; PCL = PCL + ACC, the PCH can’t be changed. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will enter the wrong address 0x0000 and the system will be in a unexpected operation mode. It is important to check whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM boundary (e.g. 0100H). Example (Incorrect): If the “jump table” crosses over ROM boundary, the program will cause the errors to occur. ROM Address . . . 0X00FD 0X00FE 0X00FF 0X0100 0X0101 . . . . . B0ADD JMP JMP JMP JMP . . PCL, A A0POINT A1POINT A2POINT A3POINT ; PCL = PCL + ACC, the PCH can’t be changed. ; ACC = 0 ; ACC = 1 ; ACC = 2 jump table cross boundary here ; ACC = 3 SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size. @JMP_A MACRO IF JMP ORG ENDIF ADD ENDM VAL (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) ($ | 0XFF) ($ | 0XFF) PCL, A Note: “VAL” is the number of the jump table listing number. SONiX TECHNOLOGY CO., LTD Page 20 Version 1.1 SN8P1602B 8-Bit Micro-Controller Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”. B0MOV @JMP_A JMP JMP JMP JMP JMP A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT ; “BUF0” is from 0 to 4. ; The number of the jump table listing is five. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT If the jump table position is from 00FDH to 0101H, the “@JMP_A” macro will make the jump table to start from 0100h. SONiX TECHNOLOGY CO., LTD Page 21 Version 1.1 SN8P1602B 8-Bit Micro-Controller DATA MEMORY (RAM) OVERVIEW The SN8P1602B has internally built-in data memory up to 48 bytes for storing the general-purpose data. 48 * 8-bit RAM The memory is separated into bank 0. The bank 0 uses the first 48 bytes as general-purpose area, and the remaining 128 bytes area as system register. SN8P1602B 000h “ “ “ “ “ 02Fh BANK 0 080h “ “ “ “ “ 0FFh RAM location 000h~02FH/07FH of Bank 0 store general-purpose data (48 bytes /128bytes). General purpose area 080h~0FFh of Bank 0 store system registers (128 bytes). System register End of bank 0 area SONiX TECHNOLOGY CO., LTD Page 22 Version 1.1 SN8P1602B 8-Bit Micro-Controller WORKING REGISTERS These Y,Z registers can be used as the general-purpose working buffer or access ROM’s and RAM’s data. For instance, all of the ROM table can be looked-up by Y and Z registers. The data of RAM memory can be indirectly accessed with Y and Z registers. Y, Z REGISTERS The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. can be used as general working registers can be used as RAM data pointers with @YZ register can be used as ROM data pointer with the MOVC instruction for look-up table 084H Y Read/Write After reset Bit 7 YBIT7 R/W 0 Bit 6 YBIT6 R/W 0 Bit 5 YBIT5 R/W 0 Bit 4 YBIT4 R/W 0 Bit 3 YBIT3 R/W 0 Bit 2 YBIT2 R/W 0 Bit 1 YBIT1 R/W 0 Bit 0 YBIT0 R/W 0 083H Z Read/Write After reset Bit 7 ZBIT7 R/W 0 Bit 6 ZBIT6 R/W 0 Bit 5 ZBIT5 R/W 0 Bit 4 ZBIT4 R/W 0 Bit 3 ZBIT3 R/W 0 Bit 2 ZBIT2 R/W 0 Bit 1 ZBIT1 R/W 0 Bit 0 ZBIT0 R/W 0 Example: uses YZ register as the data pointer to access data in the RAM address 025H of bank0. B0MOV B0MOV B0MOV Y, #00H Z, #25H A, @YZ ; To set RAM bank 0 for Y register ; To set location 25H for Z register ; To read a data into ACC Example: uses the YZ register as data pointer to clear the RAM data B0MOV B0MOV Y, #0 Z, #07FH ; Y = 0, bank 0 ; Y = 7FH, the last address of the data memory area CLR @YZ ; Clear @YZ to be zero DECMS JMP Z CLR_YZ_BUF ; Z – 1, if Z= 0, finish the routine ; Not zero CLR @YZ CLR_YZ_BUF: END_CLR: ; End of clear general purpose data memory area of bank 0 . SONiX TECHNOLOGY CO., LTD Page 23 Version 1.1 SN8P1602B 8-Bit Micro-Controller R REGISTERS R register is an 8-bit buffer. There are two major functions of the register. can be used as working register for store high-byte data of look-up table (MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the low-byte data will be stored in ACC). 082H R Read/Write After reset Bit 7 RBIT7 R/W 0 Bit 6 RBIT6 R/W 0 Bit 5 RBIT5 R/W 0 Bit 4 RBIT4 R/W 0 Bit 3 RBIT3 R/W 0 Bit 2 RBIT2 R/W 0 Bit 1 RBIT1 R/W 0 Bit 0 RBIT0 R/W 0 Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application. SONiX TECHNOLOGY CO., LTD Page 24 Version 1.1 SN8P1602B 8-Bit Micro-Controller PROGRAM FLAG The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there is carry, borrow occurrence, then these flags will be set to PFLAG register. 086H PFLAG Read/Write After reset Bit 7 NT0 R/W - Bit 6 NPD R/W - Bit 5 - Bit 4 - Bit 3 - Bit 2 C R/W 0 Bit 1 DC R/W 0 Bit 0 Z R/W 0 RESET/WAKEUP FLAG NT0 NPD 0 0 0 1 1 1 0 1 Description During the sleep mode, the device wakes up by the watch dog. Such function only valid when users set “INT_16K_RC” code option as “Always_On” Watchdog timer overflow in normal/slow/green mode. During the sleep mode, the device wakes up by the reset pin. External reset or LVD reset active Note: Watchdog timer can also be used as a fixed-period timer if the watchdog reset function has been disabled. CARRY FLAG C = 1: When executed arithmetic addition with overflow or executed arithmetic subtraction without borrow or executed rotation instruction with logic “1” shifting out. C = 0: When executed arithmetic addition without overflow or executed arithmetic subtraction with borrow or executed rotation instruction with logic “0” shifting out. DECIMAL CARRY FLAG DC = 1: If executed arithmetic addition with overflow of low nibble or executed arithmetic subtraction without borrow of low nibble. DC = 0: If executed arithmetic addition without overflow of low nibble or executed arithmetic subtraction with borrow of low nibble. ZERO FLAG Z = 1: When the content of ACC or target memory is zero after executing instructions involving a zero flag. Z = 0: When the content of ACC or target memory is not zero after executing instructions involving a zero flag. SONiX TECHNOLOGY CO., LTD Page 25 Version 1.1 SN8P1602B 8-Bit Micro-Controller ACCUMULATOR The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register. ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing mode. Example: Read and write ACC value. ; Read ACC data and store in BUF data memory MOV BUF, A ; Write a immediate data into ACC MOV A, #0FH ; Write ACC data from BUF data memory MOV A, BUF The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to other data memories. Example: Protect ACC and working registers. ACCBUF PFLAGBUF EQU EQU 00H 01H ; ACCBUF is ACC data buffer. ; PFLAGBUF is PFLAG data buffer. B0XCH B0MOV B0MOV A, ACCBUF A, PFLAG PFLAGBUF,A ; Store ACC value ; Store PFLAG value . . . . B0MOV B0MOV B0XCH A, PFLAGBUF PFLAG,A A, ACCBUF INT_SERVICE: RETI ; Re-load PFLAG value ; Re-load ACC by B0XCH command, and which will not affect the PFLAG again. ; Exit interrupt service vector Note: To save and re-load ACC data, users must use “B0XCH” instruction, or else the PFLAG Register might be modified by ACC operation. SONiX TECHNOLOGY CO., LTD Page 26 Version 1.1 SN8P1602B 8-Bit Micro-Controller STACK OPERATIONS OVERVIEW The stack buffer of SN8P1602B has 4-level. These buffers are designed to push and pop up program counter’s (PC) data when interrupt service routine is executed. The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program counter (PC) data. RET / CALL / RETI interrupt PCH PCL STK3H STK3L STK2H STK2L STKP = 3 STKP + 1 STKP -1 STKP = 2 STKP STKP STK1H STK1L STK0H STK0L STKP = 1 STKP = 0 SONiX TECHNOLOGY CO., LTD Page 27 Version 1.1 SN8P1602B 8-Bit Micro-Controller STACK REGISTERS The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 10-bit data memory (STKnH and STKnL) set aside for temporary storage of stack addresses. The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to the top address of stack buffer and write the last program counter value (PC) into the stack buffer. The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer (STKnH and STKnL) are located in the system register area bank 0. SN8P1602B 0DFH Bit 7 GIE STKP Read/Write R/W After reset 0 Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 STKPB2 R/W 1 Bit 1 STKPB1 R/W 1 Bit 0 STKPB0 R/W 1 STKPBn: Stack pointer (n = 0 ~ 2) GIE: Global interrupt control bit. 0 = disable, 1 = enable. Please refer to the interrupt chapter. Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointers in the beginning of the program. MOV B0MOV A, #00000111B STKP, A SN8P1602B 0F0H~0FFH Bit 7 Bit 6 STKnH Read/Write After reset STKn = <STKnH , STKnL> (n = 3 ~ 0) Bit 5 - Bit 4 - SN8P1602B 0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 SnPC7 SnPC6 SnPC5 SnPC4 STKnL Read/Write R/W R/W R/W R/W After reset 0 0 0 0 For SN8P1602B : STKn = <STKnH , STKnL> (n = 3 ~ 0) SONiX TECHNOLOGY CO., LTD Page 28 Bit 3 - Bit 2 - Bit 1 SnPC9 R/W 0 Bit 0 SnPC8 R/W 0 Bit 3 SnPC3 R/W 0 Bit 2 SnPC2 R/W 0 Bit 1 SnPC1 R/W 0 Bit 0 SnPC0 R/W 0 Version 1.1 SN8P1602B 8-Bit Micro-Controller STACK OPERATION EXAMPLE The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC) to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to the next available stack location. The stack buffer stores the program counter about the op-code address. The Stack-Save operation is as the following table. SN8P1602B Stack Level 0 1 2 3 4 >4 STKPB2 STKP Register STKPB1 STKPB0 1 1 1 1 0 0 1 1 0 0 1 1 Stack Buffer High Byte Low Byte 1 0 1 0 1 0 Free STK0H STK1H STK2H STK3H - Description Stack Over, error Free STK0L STK1L STK2L STK3L - There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs, the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter (PC) to the program counter registers. The Stack-Restore operation is as the following table. SN8P1602B Stack Level 4 3 2 1 0 STKPB2 STKP Register STKPB1 STKPB0 0 1 1 1 1 1 0 0 1 1 Stack Buffer High Byte Low Byte 1 0 1 0 1 STK3H STK2H STK1H STK0H Free Description - STK3L STK2L STK1L STK0L Free PROGRAM COUNTER The program counter (PC) is a 10-bit binary counter separated into the high-byte 2 and the low-byte 8 bits. This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program counter is automatically incremented with each instruction during program execution. Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction is executed, the destination address will be inserted to bit 0 ~ bit 9. SN8P1602B Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 PC9 PC After 0 reset PCH SONiX TECHNOLOGY CO., LTD Bit 8 PC8 Bit 7 PC7 Bit 6 PC6 Bit 5 PC5 Bit 4 PC4 Bit 3 PC3 Bit 2 PC2 Bit 1 PC1 Bit 0 PC0 0 0 0 0 0 0 0 0 0 PCL Page 29 Version 1.1 SN8P1602B 8-Bit Micro-Controller ONE ADDRESS SKIPPING There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction. If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction. FC C0STEP ; To skip, if Carry_flag = 1 ; Else jump to C0STEP. C0STEP: B0BTS1 JMP . NOP A, BUF0 FZ C1STEP ; Move BUF0 value to ACC. ; To skip, if Zero flag = 0. ; Else jump to C1STEP. C1STEP: B0MOV B0BTS0 JMP . NOP If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. C0STEP: CMPRS JMP . NOP A, #12H C0STEP ; To skip, if ACC = 12H. ; Else jump to C0STEP. If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next instruction. INCS instruction: C0STEP: INCS JMP … NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. INCMS JMP … NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. INCMS instruction: C0STEP: If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next instruction. DECS instruction: C0STEP: DECS JMP … NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. DECMS JMP … NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. DECMS instruction: C0STEP: SONiX TECHNOLOGY CO., LTD Page 30 Version 1.1 SN8P1602B 8-Bit Micro-Controller MULTI-ADDRESS JUMPING Users can jump around the multi-address by either JMP instruction or ADD M, An instruction (M = PCL) to activate multi-address jumping function. If carry flag occurs after execution of ADD PCL, A, the carry flag will not affect PCH register. Example: If PC = 0323H (PCH = 03H、PCL = 23H) ; PC = 0323H ; PC = 0328H MOV B0MOV . . . MOV B0MOV A, #28H PCL, A . . . A, #00H PCL, A ; Jump to address 0328H ; Jump to address 0300H Example: If PC = 0323H (PCH = 03H、PCL = 23H) ; PC = 0323H B0ADD JMP JMP JMP JMP . PCL, A A0POINT A1POINT A2POINT A3POINT . SONiX TECHNOLOGY CO., LTD ; PCL = PCL + ACC, the PCH cannot be changed. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; Page 31 Version 1.1 SN8P1602B 8-Bit Micro-Controller 4 ADDRESSING MODE OVERVIEW The SN8P1602B provides three addressing modes to access RAM data, including immediate addressing mode, directly addressing mode and indirectly address mode. IMMEDIATE ADDRESSING MODE The immediate addressing mode uses an immediate data to set up the location (“ MOV A, # I ”, “ B0MOV ACC or specific RAM. M, # I “) in Immediate addressing mode MOV A, #12H ; To set an immediate data 12H into ACC DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC.(“ MOV A,12H ”, “ MOV 12H, A ”). Directly addressing mode B0MOV A, 12H ; To get a content of location 12H of bank 0 and save in ACC INDIRECTLY ADDRESSING MODE The indirectly addressing mode is to access the memory by the data pointer registers (Y/Z). Example: Indirectly addressing mode with @YZ register CLR B0MOV B0MOV Y Z, #12H A, @YZ SONiX TECHNOLOGY CO., LTD ; To clear Y register to access RAM bank 0. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. Page 32 Version 1.1 SN8P1602B 8-Bit Micro-Controller 5 SYSTEM REGISTER OVERVIEW The RAM area located in 80H~FFH bank 0 is system register area. The main purpose of system registers is to control peripheral hardware of the chip. Using system registers can control I/O ports, timers and counters by programming. The memory map provides an easy and quick reference source for writing application program. These system registers accessing is controlled by the selected memory bank (RBANK = 0) or the bank 0 read/write instruction (B0MOV, B0BSET, B0BCLR…). SYSTEM REGISTER ARRANGEMENT (BANK 0) BYTES of SYSTEM REGISTER SN8P1602B 0 1 8 9 A B C D E F 2 3 4 5 6 7 PFLAG RPAGE 8 9 A B C D E F - - R Z Y - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PUR PEDGE P1W P1M P2M - - - - - P0 P1 P2 - - - - - - - - - - - - @YZ - - - - - - - - INTRQ INTEN OSCM - - - PCL PCH T0M - TC0M TC0C - - - STKP - - - - - - - - STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H Description PFLAG = P1W = PnM = INTRQ = OSCM = TCnM = T0M.1= STKP = @YZ = ROM page and special flag register. Port 1 wakeup register. Port n input/output mode register. Interrupt request register. Oscillator mode register. Timer n mode register. TC0GN, TC0 green mode wakeup flag. Stack pointer buffer. RAM YZ indirect addressing index pointer. SONiX TECHNOLOGY CO., LTD R= Y, Z = Pn = INTEN = PCH, PCL = TCnC = Working register and ROM look-up data buffer. Working, @YZ and ROM addressing register. Port n data buffer. Interrupt enable register. Program counter. Timer n counting register. STK0~STK3 = Stack 0 ~ stack 3 buffer. Page 33 Version 1.1 SN8P1602B 8-Bit Micro-Controller BITS of SYSTEM REGISTER SN8P1602B system register table Address 082H 083H 084H 086H 0BEH 0BFH 0C0H 0C1H 0C2H 0C8H 0C9H 0CAH 0CEH 0CFH 0D0H 0D1H 0D2H 0D8H 0DAH 0DBH 0DFH 0E7H 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH Bit7 RBIT7 ZBIT7 YBIT7 NT0 PEDGEN 0 0 P27M 0 0 WTCKS PC7 P27 TC0ENB TC0C7 GIE @YZ7 S3PC7 S2PC7 S1PC7 S0PC7 - Bit6 RBIT6 ZBIT6 YBIT6 NPD 0 0 P26M 0 0 WDRST PC6 P26 TC0rate2 TC0C6 @YZ6 S3PC6 S2PC6 S1PC6 S0PC6 - Bit5 RBIT5 ZBIT5 YBIT5 0 0 P25M TC0IRQ TC0IEN 0 PC5 P25 TC0rate1 TC0C5 @YZ5 S3PC5 S2PC5 S1PC5 S0PC5 - Bit4 RBIT4 ZBIT4 YBIT4 P00G1 P14W P14M P24M 0 0 CPUM1 PC4 P14 P24 TC0rate0 TC0C4 @YZ4 S3PC4 S2PC4 S1PC4 S0PC4 - Bit3 RBIT3 ZBIT3 YBIT3 P00G0 P13W P13M P23M 0 0 CPUM0 PC3 P13 P23 TC0CKS TC0C3 @YZ3 S3PC3 S2PC3 S1PC3 S0PC3 - Bit2 RBIT2 ZBIT2 YBIT2 C PUR2 P12W P12M P22M 0 0 CLKMD PC2 P12 P22 0 TC0C2 STKPB2 @YZ2 S3PC2 S2PC2 S1PC2 S0PC2 - Bit1 RBIT1 ZBIT1 YBIT1 DC PUR1 P11W P11M P21M 0 0 STPHX PC1 PC9 P11 P21 TC0GN 0 TC0C1 STKPB1 @YZ1 S3PC1 S3PC9 S2PC1 S2PC9 S1PC1 S1PC9 S0PC1 S0PC9 Bit0 RBIT0 ZBIT0 YBIT0 Z PUR0 P10W P10M P20M P00IRQ P00IEN 0 PC0 PC8 P00 P10 P20 0 TC0C0 STKPB0 @YZ0 S3PC0 S3PC8 S2PC0 S2PC8 S1PC0 S1PC8 S0PC0 S0PC8 R/W R/W R/W R/W R/W W W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Remarks R Z Y PFLAG PUR PEDGE P1W wakeup register P1M I/O direction P2M I/O direction INTRQ INTEN OSCM PCL PCH P0 data buffer P1 data buffer P2 data buffer T0M TC0M TC0C STKP stack pointer @YZ index pointer STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H Note a): To avoid system error, please be sure to put all the “0” as it indicates in the above table b). All of register names had been declared in SN8ASM assembler. c). One-bit name had been declared in SN8ASM assembler with “F” prefix code. d). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers. e). For detail description, please refer to the “System Register Quick Reference Table” SONiX TECHNOLOGY CO., LTD Page 34 Version 1.1 SN8P1602B 8-Bit Micro-Controller 6 POWER ON RESET OVERVIEW SN8P1602B provides two system resets. One is external reset and the other is internal low voltage detector (LVD). The external reset is a simple RC circuit connecting to the reset pin. The low voltage detector (LVD) is built in internal circuit. When one of the reset devices occurs, the system will reset and the system registers become initial value. The timing diagram is as the following. VDD LVD Detect Level External Reset External Reset Detect Level LVD End of LVD Reset Internal Reset Signal End of External Reset SN8P1602B power on reset timing diagram SONiX TECHNOLOGY CO., LTD Page 35 Version 1.1 SN8P1602B 8-Bit Micro-Controller EXTERNAL RESET DESCRIPTION The external reset is a low level active device. The reset pin receives the low voltage and resets the system. When the voltage detects high level, it stops resetting the system. Users can use an external reset circuit to control system operation. VDD External Reset External Reset Detect Level Internal Reset Signal System Reset End of External Reset Users must make sure the VDD is stable earlier than external reset. Otherwise, the power on reset maybe fail. The external reset circuit is a simple RC circuit as the following figure. R VDD 20K ohm RST C 0.1uF MCU VSS VCC GND SONiX TECHNOLOGY CO., LTD Page 36 Version 1.1 SN8P1602B 8-Bit Micro-Controller Under different environment, by placing a diode in between VCC and reset pin will help the Brownout reset. R DIODE VDD 20K ohm RST C 0.1uF MCU VSS VCC GND LOW VOLTAGE DETECTOR (LVD) DESCRIPTION The LVD is a low voltage detector. It detects VDD level and reset the system as the VDD lower than the detected voltage. The detect level is 1.8V. If the VDD lower than 1.8V, the system resets. VDD LVD Detect Level LVD System Reset SONiX TECHNOLOGY CO., LTD End of LVD Reset Page 37 Version 1.1 SN8P1602B 8-Bit Micro-Controller 7 OSCILLATORS OVERVIEW The SN8P1602B is a dual clock micro-controller system. There are external high-speed clock and internal low-speed clock. The high-speed clock is generated from the external oscillator circuit. The low-speed clock is generated from on-chip RC oscillator circuit. Both the external high-speed clock and the internal low-speed clock can be system clock (Fosc). The system clock is divided by 4 to be the instruction cycle (Fcpu). Fcpu = Fosc / 4 CLOCK BLOCK DIAGRAM HXRC(1:0) is code option •00= RC •01 =32 Khz Oscillator •10 = High Speed Oscillator (>10Mhz) •11 = Standard Oscillator (4Mhz) STPHX Divided by 2 1 : Disable HXRC CLKMD fosc/4 CPUM0 0 : Enable XIN HXOSC. fh XOUT OSG Divided by 2 Divided by 4 fcpu OSG : Oscillator Safe Guard CPUM0 LXOSC. 1 : Disable -- System Default fl 0 : Enable CPUM0 HXOSC: External high-speed clock LXOSC: Internal low-speed clock OSG: Oscillator safe guard SONiX TECHNOLOGY CO., LTD Page 38 Version 1.1 SN8P1602B 8-Bit Micro-Controller OSCM REGISTER DESCRIPTION The OSCM register is an oscillator control register. It controls oscillator status, system mode, watchdog timer clock rate. 0CAH OSCM Read/Write After reset Bit 7 WTCKS R/W 0 Bit 6 WDRST R/W 0 Bit 5 0 - Bit 4 CPUM1 R/W 0 Bit 3 CPUM0 R/W 0 Bit 2 CLKMD R/W 0 Bit 1 STPHX R/W 0 Bit 0 0 - STPHX: External high-speed oscillator control bit. 0 = free run, 1 = stop. This bit only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC oscillator is still running. CLKMD: System high/Low clock mode: bit 0 = normal (dual) mode, 1 = slow mode. CPUM1, CPUM0: CPU operating mode control bit: 00 = normal 01 = sleep (power down) mode 10 = green mode 11 = reserved. WDRST: Watchdog timer reset bit 0 = Non-reset 1 = clear the watchdog timer’s counter. Please refer to the “watchdog timer chapter” for detailed information. WTCKS: Watchdog clock source 0 = Fcpu 1 = internal RC low clock SONiX TECHNOLOGY CO., LTD Page 39 Version 1.1 SN8P1602B 8-Bit Micro-Controller EXTERNAL HIGH-SPEED OSCILLATOR SN8P1602B can be operated in four different oscillator modes. There are external RC oscillator modes, high crystal/resonator mode (12M code option), standard crystal/resonator mode (4M code option) and low crystal mode (32K code option). For different application, the users can select one of suitable oscillator mode by programming code option to generate system high-speed clock source after reset. Example: Stop external high-speed oscillator B0BSET FSTPHX ; To stop external high-speed oscillator only. Example: When entering the Power Down mode, both external high-speed oscillator and internal low-speed oscillator will be stopped. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). OSCILLATOR MODE CODE OPTION SN8P1602B has four oscillator modes for different applications. These modes are 4M, 12M, 32K and RC. The main purpose is to support different oscillator types and frequencies. MCU needs more current when operating at High-speed mode than the low-speed mode. For crystals, there are three steps to select. If the oscillator is RC type, to select “RC” and the system will divide the frequency by 2 automatically. User can select oscillator mode from code option table before compiling. Following is the code option table. Code Option 00 01 10 11 Oscillator Mode RC mode 32K 12M 4M Remark Output the Fcpu square wave from Xout pin. 32768Hz 12MHz ~ 16MHz 3.58MHz OSCILLATOR DEVIDE BY 2 CODE OPTION SN8P1602B has a code option to divide external clock by 2,called “High_Clk / 2”. If “High_Clk / 2” is enabled, the external clock frequency is divided by 8 for the Fcpu. Fcpu is equal to Fosc/8. If “High_Clk / 2” is disabled, the Fcpu is equal to Fosc/4. Note: In RC mode, “High_Clk / 2” is always enabled. OSCILLATOR SAFE GUARD CODE OPTION SN8P1602B builds in an oscillator safe guard (OSG) to make oscillator more stable. It is a low-pass filter circuit and stops high frequency noise into system from external oscillator circuit. This function makes system to work better under AC noisy conditions. SONiX TECHNOLOGY CO., LTD Page 40 Version 1.1 SN8P1602B 8-Bit Micro-Controller SYSTEM OSCILLATOR CIRCUITS VDD 20PF XIN CRYSTAL 20PF MCU XOUT VSS Crystal/Ceramic Oscillator VDD R XIN XOUT C MCU VSS RC Oscillator VDD External Clock Input XIN XOUT MCU VSS External clock input Note1: The external oscillator circuit must be directly from Vss pin of micro-controller. Note2: The input source of XIN pin received from external oscillator circuit, the code option can be either be RC type oscillator or crystal type oscillator. Note3: In RC type oscillator code option situation, the external clock frequency is automatically divided by 2. SONiX TECHNOLOGY CO., LTD Page 41 Version 1.1 SN8P1602B 8-Bit Micro-Controller External RC Oscillator Frequency Measurement There are two ways to get the Fosc frequency of external RC oscillator. One way is to measure the XOUT output waveform. Moreover, the other way is to measure the external RC frequency by software instruction cycle (Fcpu). Example: Fcpu instruction cycle of external oscillator B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle signal. B0BSET B0BCLR JMP P1.0 P1.0 @B ; Output Fcpu toggle signal in low-speed clock mode. ; Measure the Fcpu frequency by oscilloscope. @@: Note: Do not measure the RC frequency directly from XIN, the probe impendence will affect the RC value. SONiX TECHNOLOGY CO., LTD Page 42 Version 1.1 SN8P1602B 8-Bit Micro-Controller INTERNAL LOW-SPEED OSCILLATOR The internal low-speed oscillator is built in the micro-controller. The low-speed clock source is a RC type oscillator circuit. Example: Stop internal low-speed oscillator B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0 bit of OSCM register. The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relation between the RC frequency and voltage is as the following figure. Internal RC vs. VDD 40 38.678 35.343 Fintrc (KHz) 35 32.008 30 28.673 25.338 25 22.003 20 18.668 15.333 15 11.998 10 8.663 7.329 5 0 1.80 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50 VDD (Volts) Example: Measure the internal RC frequency by instruction cycle (Fcpu). The internal RC frequency is the Fcpu multiplied by 4. We can get the Fosc frequency of internal RC from the Fcpu frequency. B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle signal. B0BSET FCLKMD ; Switch the system clock to internal low-speed clock mode. B0BSET B0BCLR JMP P1.0 P1.0 @B ; Output Fcpu toggle signal in low-speed clock mode. ; Measure the Fcpu frequency by oscilloscope. @@: SONiX TECHNOLOGY CO., LTD Page 43 Version 1.1 SN8P1602B 8-Bit Micro-Controller SYSTEM MODE DESCRIPTION OVERVIEW The chip is featured with low power consumption by switching around four different modes as following. High-speed mode Low-speed mode Power-down mode (Sleep mode) Green mode NORMAL MODE In normal mode, the system clock source is external high-speed clock. After power on, the system works under normal mode. The instruction cycle is fosc/4. When the external high-speed oscillator is 3.58MHz, the instruction cycle is 3.58MHz/4 = 895KHz. From normal mode, the system can get into power down mode, slow mode and green mode. SLOW MODE In slow mode, the system clock source is internal low-speed RC clock. To set CLKMD =1, the system switches into slow mode. In slow mode, the system functions similar to the normal mode except using the internal RC clock. The system in slow mode can switch back to high-speed normal mode. On the other hand, it can be easily switch to power down mode and green mode for less power consumption. GREEN MODE The green mode provides a time-variable wakeup function. Users can decide wakeup time by setting TC0 timer. There are two paths into green mode. One is from normal mode and the other is from slow mode. In normal mode, the TC0 timer overflow time is very short. In slow mode, the overflow time is longer. Users can select appropriate situation for their applications. Under green mode, the power consumption is around 5uA in 3V condition. The system can be waked up to last system mode by TC0 timer timeout and P0 trigger signal. POWER DOWN MODE The power down mode is also called sleep mode. The MCU stops working as sleeping status. To set CUPM0 = 1, the system gets into power down mode. The external high-speed and low-speed oscillators are turned off. The system can be waked up by P0, P1 trigger signal. SONiX TECHNOLOGY CO., LTD Page 44 Version 1.1 SN8P1602B 8-Bit Micro-Controller SYSTEM MODE CONTROL Power Down Mode (Sleep Mode) P0, P1 wake-up function active. External reset circuit active. CPUM1, CPUM0 = 01 CLKMD = 1 Normal Mode Slow Mode CLKMD = 0 CPUM1, CPUM0 = 10 P0, P1 wake-up function active. P0, P1 wake-up function active. TC0 time out. TC0 time out. External reset circuit active. Green Mode External reset circuit active. SN8P1602B Type Operating mode description MODE NORMAL SLOW GREEN HX osc. LX osc. CPU instruction Running Running Executing By STPHX Running Executing By STPHX Running Stop POWER DOWN (SLEEP) Stop Stop Stop TC0 timer *Active *Active *Active Inactive Watchdog timer Active Active By INT_16K_RC By INT_16K_RC All active All active TC0 All inactive All active All active All active All inactive - - P0, P1, TC0 Reset P0, P1, Reset Internal interrupt External interrupt Wakeup source SONiX TECHNOLOGY CO., LTD Page 45 REMARK * Active by program Version 1.1 SN8P1602B 8-Bit Micro-Controller SYSTEM MODE SWITCHING Switch normal/slow mode to power down (sleep) mode. CPUM0 = 1 B0BSET FCPUM0 ; Set CPUM0 = 1. During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. Switch normal mode to slow mode. B0BSET B0BSET FCLKMD FSTPHX ;To set CLKMD = 1, Change the system into slow mode ;To stop external high-speed oscillator for power saving. Switch slow mode to normal mode (The external high-speed oscillator is still running) B0BCLR FCLKMD ;To set CLKMD = 0 Switch slow mode to normal mode (The external high-speed oscillator stops) If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for external clock stable. @@: B0BCLR FSTPHX ; Turn on the external high-speed oscillator. B0MOV DECMS JMP Z, #27 Z @B ; If VDD = 5V, internal RC=32KHz (typical) will delay ; 0.125ms X 81 = 10.125ms for external clock stable B0BCLR FCLKMD ; ; Change the system back to the normal mode Example: Go into Green mode and enable TC0 wakeup function. ; Set TC0 timer wakeup function. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BCLR B0BCLR B0BSET B0BSET ; Go into green mode B0BCLR B0BSET FTC0IEN FTC0ENB A,#20H TC0M,A A,#74H TC0C,A FTC0IEN FTC0IRQ FTC0ENB FTC0GN FCPUM0 FCPUM1 ; To disable TC0 interrupt service ; To disable TC0 timer ; ; To set TC0 clock = Fcpu / 64 ; To set TC0C initial value = 74H (To set TC0 interval = 10 ms) ; To disable TC0 interrupt service ; To clear TC0 interrupt request ; To enable TC0 timer ; To enable TC0 wakeup function ;To set CPUMx = 10 Note: If TC0ENB = 0 or TC0GN = 0, TC0 will not be able to wakeup from green mode to normal/slow mode function. SONiX TECHNOLOGY CO., LTD Page 46 Version 1.1 SN8P1602B 8-Bit Micro-Controller WAKEUP TIME OVERVIEW The external high-speed oscillator needs a delay time from stopping to operating. The delay is necessary for oscillator to be stabilized.. The delay time for external high-speed oscillator restart is sometimes called wakeup time. Following are two conditions require wakeup time, one is switching power down mode to normal mode, and the other is switching slow mode to normal mode. For the first condition, SN8P1602B provides 2048 oscillator clocks as the wakeup time. The second condition, users need to take the wakeup time into consideration, which involved stabilizing period for start up the external high-speed oscillator. HARDWARE WAKEUP When the system is in power down mode (sleep mode), the external high-speed oscillator stops. When waked up from power down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode. The value of the wakeup time is as the following. The Wakeup time = 1/Fosc * 2048 (sec) + X’tal settling time The X’tal settling time is depended on the X’tal type. Typically, it is about 2~4mS. Example: In power down mode (sleep mode), the system is waked up by P0 or P1 trigger signal. After the wakeup time, the system goes into normal mode. The wakeup time of P0, P1 wakeup function is as the following. The wakeup time = 1/Fosc * 2048 = 0.57 ms (Fosc = 3.58MHz) The total wakeup time = 0.57ms + X’tal settling time Under power down mode (sleep mode), only the I/O ports with wakeup function are able to wake the system up to normal mode. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function always enables, but the Port 1 is controlled by the P1W register. SN8P1602B 0C0H Bit 7 0 P1W Read/Write After reset - Bit 6 0 - Bit 5 0 - Bit 4 P14W R/W 0 Bit 3 P13W R/W 0 Bit 2 P12W R/W 0 Bit 1 P11W R/W 0 Bit 0 P10W R/W 0 P10W~P14W: Port 1 wakeup function control bits. 0 = none wakeup function, 1 = Enable each pin of Port 1 wakeup function. SONiX TECHNOLOGY CO., LTD Page 47 Version 1.1 SN8P1602B 8-Bit Micro-Controller EXTERNAL WAKEUP TRIGGER CONTROL In the SN8P1602B, the wakeup trigger direction is control by PEDGE register. PEDGE initial value = 0xx0 0xxx 0BFH PEDGE Bit 7 PEDGEN R/W Bit 6 - Bit 5 - Bit 4 P00G1 R/W Bit 3 P00G0 R/W Bit 2 - Bit7 PEDGEN: Interrupt and wakeup trigger edge control bit. 0 = Disable edge trigger function. Port 0: Low-level wakeup trigger and falling edge interrupt trigger. Port 1: Low-level wakeup trigger. 1 = Enable edge trigger function. P0.0: Wakeup and interrupt trigger is controlled by P00G1 and P00G0 bits. Port 1: Level change (falling or rising edge) wakeup trigger. Bit[4:3] P00G[1:0]: Port 0.0 edge select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction. SONiX TECHNOLOGY CO., LTD Page 48 Bit 1 - Bit 0 - Version 1.1 SN8P1602B 8-Bit Micro-Controller 8 TIMERS WATCHDOG TIMER (WDT) The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into the unknown status by noise interference, WDT overflow signal raises and resets MCU. The instruction that clears the watchdog timer (“ B0BSET FWDRST “) should be executed within a certain period. If an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted. 0CAH OSCM Read/Write After reset Bit 7 WTCKS R/W 0 Bit 6 WDRST R/W 0 Bit 5 0 - Bit 4 CPUM1 R/W 0 Bit 3 CPUM0 R/W 0 Bit 2 CLKMD R/W 0 Bit 1 STPHX R/W 0 Bit 0 0 - WDRST: Watchdog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer counter. WTCKS: Watchdog clock source select bit 0 = Fcpu, 1 = internal RC low clock. Watchdog timer overflow table. WTCKS CLKMD Code Option Watchdog Timer Overflow Time 0 0 0 1 - 0 0 1 - 4M_X’tal / 12M_X’tal / RC 32K_X’tal Enable Int_16K_RC 1 / ( Fcpu ÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz 1 / ( Fcpu ÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz 1 / ( Fcpu ÷ 214 ÷ 16 ) = 65.5s, Fosc=16KHz@3V 1 / ( 16K ÷ 512 ÷ 16 ) ~ 0.5s @3V 1 / ( 16K ÷ 512 ÷ 16 ) ~ 0.5s @3V Note: The watchdog timer can be enabled or disabled by the code option. If disabled, the watchdog timer can also be served as fixed-period timer by checking the NT0 flag. Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the main routine of the program. Main: B0BSET . CALL CALL . . . JMP FWDRST . SUB1 SUB2 . . . MAIN SONiX TECHNOLOGY CO., LTD ; Clear the watchdog timer counter. Page 49 Version 1.1 SN8P1602B 8-Bit Micro-Controller TIMER0 (TC0) OVERVIEW The TC0 is an 8-bit binary up timer and event counter, using TC0M register to select TC0C’s clock source from GTMR or from external INT0 pin ( falling edge trigger) for counting a precision time. If TC0 timer occurs an overflow (from FFH to 00H), it will continue counting and issue a time-out signal to trigger TC0 interrupt to request interrupt service. ÷ 2(8-TC0Rate) TC0cks TC0enb Internal data bus pre_load Fcpu TC0C 8-bit b inary counter INT0 (schmitter t rigger) TC0 Time out CPUM1,0 The main purposes of the TC0 timer is as following. 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. External event counter: Counts system “events” based on falling edge detection of external clock signals at the INT0 input pin. SONiX TECHNOLOGY CO., LTD Page 50 Version 1.1 SN8P1602B 8-Bit Micro-Controller TC0M MODE REGISTER The TC0M is an 8-bit read/write timer mode register. By loading different value into the TC0M register, users can modify the timer period as program executing. Eight rates for TC0 timer can be selected by TC0RATE0 ~ TC0RATE2 bits. The range is from fcpu/2 to fcpu/256. The TC0M initial value is zero and the rate is fcpu/256. The bit7 of TC0M called TC0ENB is the control bit to start TC0 timer. The combination of these bits is to determine the TC0 timer clock frequency and the intervals. 0DAH TC0M Read/Write After reset Bit 7 TC0ENB R/W 0 Bit 6 TC0rate2 R/W 0 Bit 5 TC0rate1 R/W 0 Bit 4 TC0rate0 R/W 0 Bit 3 TC0CKS R/W 0 Bit 2 0 - Bit 1 0 - Bit 0 0 - TC0ENB: TC0 counter enable bit. “0” = disable, “1” = enable. TC0RATE2~TC0RATE0: TC0 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, … , 110 = fcpu/4, 111 = fcpu/2. TC0CKS: TC0 clock source select bit. 0 = Fcpu, 1 = External clock comes from INT0/P0.0 pin. Note1: The ICE S8KC does not support the PWM0OUT and TC0OUT Function. The PWM0OUT and TC0OUT must use the S8KD ICE (or later) to verify the function. Note2: When TC0CKS=1, TC0 became an external event counter. No more P0.0 interrupt request will be raised. (P0.0IRQ will be always 0) SONiX TECHNOLOGY CO., LTD Page 51 Version 1.1 SN8P1602B 8-Bit Micro-Controller TC0C COUNTING REGISTER TC0C is an 8-bit counter register for the timer (TC0). TC0C must be reset whenever the TC0ENB is set to “1” to start the timer. TC0C is incremented each time a clock pulse of the frequency determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to “0FFH”, it counts to “00H” an overflow generated. Under TC0 interrupt service request (TC0IEN) enable condition, the TC0 interrupt request flag will be set to “1” and the system executes the interrupt service routine. The TC0C has no auto reload function. After TC0C overflow, the TC0C is continuing counting. Users need to redefine the TC0C value to get an accurate time. 0DBH TC0C Read/Write After reset Bit 7 TC0C7 R/W 0 Bit 6 TC0C6 R/W 0 Bit 5 TC0C5 R/W 0 Bit 4 TC0C4 R/W 0 Bit 3 TC0C3 R/W 0 Bit 2 TC0C2 R/W 0 Bit 1 TC0C1 R/W 0 Bit 0 TC0C0 R/W 0 The basic timer table interval time of TC0 TC0RATE TC0CLOCK 000 001 010 011 100 101 110 111 fcpu/256 fcpu/128 fcpu/64 fcpu/32 fcpu/16 fcpu/8 fcpu/4 fcpu/2 High speed mode (Fcpu = 3.58MHz / 4) Max overflow interval One step = max/256 73.2 ms 286us 36.6 ms 143us 18.3 ms 71.5us 9.15 ms 35.8us 4.57 ms 17.9us 2.28 ms 8.94us 1.14 ms 4.47us 0.57 ms 2.23us Low speed mode (Fcpu = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31.25 ms 4000 ms 15.63 ms 2000 ms 7.8 ms 1000 ms 3.9 ms 500 ms 1.95 ms 250 ms 0.98 ms 125 ms 0.49 ms 62.5 ms 0.24 ms The equation of TC0C initial value is as following. TC0C initial value = 256 - (TC0 interrupt interval time * input clock) Example: To set 10ms interval time for TC0 interrupt at 3.58MHz high-speed mode. TC0C value (74H) = 256 - (10ms * fcpu/64) TC0C initial value = 256 - (TC0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 106 / 4 / 64) = 256 - (10-2 * 3.58 * 106 / 4 / 64) = 116 = 74H SONiX TECHNOLOGY CO., LTD Page 52 Version 1.1 SN8P1602B 8-Bit Micro-Controller TC0 TIMER OPERATION SEQUENCE The TC0 timer’s sequence of operation may be as following. Set the TC0C initial value to setup the interval time. Set the TC0ENB to be “1” to enable TC0 timer. TC0C is incremented by one after each clock pulse corresponding to TC0M selection. TC0C overflow if TC0C from FFH to 00H. When TC0C overflow occur, the TC0IRQ flag is set to be “1” by hardware. Execute the interrupt service routine. Users reset the TC0C value and resume the TC0 timer operation. Example: Setup the TC0M and TC0C. B0BCLR B0BCLR MOV B0MOV MOV B0MOV FTC0IEN FTC0ENB A,#20H TC0M,A A,#74H TC0C,A ; To disable TC0 interrupt service ; To disable TC0 timer ; ; To set TC0 clock = Fcpu / 64 ; To set TC0C initial value = 74H ;(To set TC0 interval = 10 ms) B0BSET B0BCLR B0BSET FTC0IEN FTC0IRQ FTC0ENB ; To enable TC0 interrupt service ; To clear TC0 interrupt request ; To enable TC0 timer Example: TC0 interrupt service routine. ORG JMP 8 INT_SERVICE ; Interrupt vector B0XCH B0MOV B0MOV A, ACCBUF A, PFLAG PFLAGBUF, A ; B0xch instruction do not change C,Z flag B0BTS1 JMP FTC0IRQ EXIT_INT ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector B0BCLR MOV B0MOV . . JMP FTC0IRQ A,#74H TC0C,A . . EXIT_INT ; Reset TC0IRQ ; Reload TC0C . . . . B0MOV B0MOV B0XCH A, PFLAGBUF PFLAG, A A, ACCBUF INT_SERVICE: ; TC0 interrupt service routine ; End of TC0 interrupt service routine and exit interrupt vector EXIT_INT: RETI SONiX TECHNOLOGY CO., LTD ; Restore ACC value. ; Exit interrupt vector Page 53 Version 1.1 SN8P1602B 8-Bit Micro-Controller 9 INTERRUPT OVERVIEW The SN8P1602B provides 2 interrupt sources, including 1 internal interrupt (TC0) and 1 external interrupt (INT0). The external interrupt can wakeup the chip while the system is switched from power down mode to high-speed normal mode. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt request. On the contrast, when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request. All of the interrupt request signals are stored in INTRQ register. SN8P1602B The interrupt trigger edge : INT0 = falling edge TC0 time out INT0 trigger INTEN Interrupt enable register TC0IRQ INTRQ 2-bit Latchs P00IRQ Interrupt enable gating Interrupt vector address (0008H) Global interrupt request signal Note: The GIE bit must enable during all interrupt operation. SONiX TECHNOLOGY CO., LTD Page 54 Version 1.1 SN8P1602B 8-Bit Micro-Controller INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt service routine instruction (RETI) is executed. SN8P1602B 0C9H Bit 7 0 INTEN Read/Write After reset - Bit 6 0 - Bit 5 TC0IEN R/W 0 Bit 4 0 - Bit 3 0 - Bit 2 0 - Bit 1 0 - Bit 0 P00IEN R/W 0 P00IEN : External P0.0 interrupt control bit. 0 = disable, 1 = enable. TC0IEN : Timer 0 interrupt control bit 0 = disable, 1 = enable. INTRQ INTERRUPT REQUEST REGISTER INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request. SN8P1602B 0C8H Bit 7 0 INTRQ Read/Write After reset - Bit 6 0 - Bit 5 TC0IRQ R/W 0 Bit 4 0 - Bit 3 0 - Bit 2 0 - Bit 1 0 - Bit 0 P00IRQ R/W 0 P00IRQ : External P0.0 interrupt request bit. 0 = non-request, 1 = request. TC0IRQ : TC0 timer interrupt request controls bit 0 = non request, 1 = request. When interrupt occurs, the related request bit of INTRQ register will be set to “1” no matter the related enable bit of INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the system won’t execute interrupt vector even when the related bit of INTRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation. SONiX TECHNOLOGY CO., LTD Page 55 Version 1.1 SN8P1602B 8-Bit Micro-Controller INTERRUPT OPERATION DESCRIPTION GIE GLOBAL INTERRUPT OPERATION GIE is the global interrupt control bit. All interrupts start work after the GIE = 1. It is necessary for interrupt service request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and the stack add 1 level. SN8P1602B 0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE STKPB2 STKPB1 STKPB0 STKP Read/Write R/W R/W R/W R/W After reset 0 1 1 1 GIE: Global interrupt control bit. 0 = disable, 1 = enable. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable during all interrupt operation. SONiX TECHNOLOGY CO., LTD Page 56 Version 1.1 SN8P1602B 8-Bit Micro-Controller INT0 (P0.0) INTERRUPT OPERATION The P0.0 interrupt trigger direction is control by PEDGE register. PEDGE initial value = 0xx0 0xxx 0BFH PEDGE Bit 7 PEDGEN R/W Bit 6 - Bit 5 - Bit 4 P00G1 R/W Bit 3 P00G0 R/W Bit 2 - Bit7 PEDGEN: Interrupt and wakeup trigger edge control bit. 0 = Disable edge trigger function. Port 0: Low-level wakeup trigger and falling edge interrupt trigger. Port 1: Low-level wakeup trigger. 1 = Enable edge trigger function. P0.0: Wakeup and interrupt trigger is controlled by P00G1 and P00G0 bits. Port 1: Level change (falling or rising edge) wakeup trigger. Bit[4:3] P00G[1:0]: Port 0.0 edge select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction. Bit 1 - Bit 0 - Example: INT0 interrupt request setup. B0BSET B0BCLR B0BSET FP00IEN FP00IRQ FGIE ; Enable INT0 interrupt service ; Clear INT0 interrupt request flag ; Enable GIE Example: INT0 interrupt service routine. ORG JMP 8 INT_SERVICE ; Interrupt vector B0XCH B0MOV B0MOV A, ACCBUF A, PFLAG PFLAGBUF, A ; Store ACC value. B0BTS1 JMP FP00IRQ EXIT_INT ; Check P00IRQ ; P00IRQ = 0, exit interrupt vector B0BCLR . . FP00IRQ . . ; Reset P00IRQ ; INT0 interrupt service routine B0MOV B0MOV B0XCH A, PFLAGBUF PFLAG, A A, ACCBUF INT_SERVICE: EXIT_INT: RETI ; Restore ACC value. ; Exit interrupt vector When the INT0 trigger occurs, the P00IRQ will be set to “1” no matter the P00IEN is enable or disable. If the P00IEN = 1 and the trigger event P00IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG 8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even when the P00IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation. SONiX TECHNOLOGY CO., LTD Page 57 Version 1.1 SN8P1602B 8-Bit Micro-Controller TC0 INTERRUPT OPERATION Example: TC0 interrupt request setup. B0BCLR B0BCLR MOV B0MOV MOV B0MOV FTC0IEN FTC0ENB A, #20H TC0M, A A, #74H TC0C, A ; Disable TC0 interrupt service ; Disable TC0 timer ; ; Set TC0 clock = Fcpu / 64 ; Set TC0C initial value = 74H ; Set TC0 interval = 10 ms B0BSET B0BCLR B0BSET FTC0IEN FTC0IRQ FTC0ENB ; Enable TC0 interrupt service ; Clear TC0 interrupt request flag ; Enable TC0 timer B0BSET FGIE ; Enable GIE Example: TC0 interrupt service routine. ORG JMP 8 INT_SERVICE ; Interrupt vector B0XCH B0MOV B0MOV A, ACCBUF A, PFLAG PFLAGBUF, A ; Store ACC value. B0BTS1 JMP FTC0IRQ EXIT_INT ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector B0BCLR MOV B0MOV . . FTC0IRQ A, #74H TC0C, A . . ; Reset TC0IRQ B0MOV B0MOV B0XCH A, PFLAGBUF PFLAG, A A, ACCBUF INT_SERVICE: ; Reset TC0C. ; TC0 interrupt service routine EXIT_INT: RETI ; Restore ACC value. ; Exit interrupt vector When the TC0C counter overflows, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the TC0IEN = 0, the trigger event TC0IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even when the TC0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation. SONiX TECHNOLOGY CO., LTD Page 58 Version 1.1 SN8P1602B 8-Bit Micro-Controller MULTI-INTERRUPT OPERATION Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. And which means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be logic “1”. The IRQ and its trigger event relationship is as the below table. Interrupt Name P00IRQ TC0IRQ Trigger Event Description P0.0 trigger controlled by PEDGE TC0C overflow For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests. Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and interrupt request flag in interrupt routine. Example: Check the interrupt request under multi-interrupt operation ORG 8 ; Interrupt vector B0XCH B0MOV B0MOV A, ACCBUF A, PFLAG PFLAGBUF,A ; Store ACC value. ; Store PFLAG value B0BTS1 JMP B0BTS0 JMP FP00IEN INTTC0CHK FP00IRQ INTP00 B0BTS1 JMP B0BTS0 JMP FTC0IEN INT_EXIT FTC0IRQ INTTC0 B0MOV B0MOV B0XCH A, PFLAGBUF PFLAG,A A, ACCBUF INTP00CHK: INTTC0CHK: ; Check INT0 interrupt request ; Check P00IEN ; Jump check to next interrupt ; Check P00IRQ ; Jump to INT0 interrupt service routine ; Check TC0 interrupt request ; Check TC0IEN ; Jump to exit of IRQ ; Check TC0IRQ ; Jump to TC0 interrupt service routine INT_EXIT: RETI SONiX TECHNOLOGY CO., LTD ; Restore PFLAG value ; Restore ACC value. ; Exit interrupt vector Page 59 Version 1.1 SN8P1602B 8-Bit Micro-Controller 10 I/O PORT OVERVIEW The SN8P1602B provides 3 ports for users’ application, consisting one input only port (P0) and two I/O ports (P1, P2,). Each port consists input pull-up resistors. The direction of I/O port can be selected by PnM register. When the system resets, these ports will then be set as input port without pull up resistors. The pull-up resistor can be set up by PUR register. SN8P1602B Port1~Port2 structure Port0 structure PUR PUR PnM, PUR PUR Pin PnM Pin Int. bus Latch PnM Note: All of the latch output circuits are push-pull structures. . SONiX TECHNOLOGY CO., LTD Page 60 Version 1.1 SN8P1602B 8-Bit Micro-Controller I/O PORT FUNCTION TABLE SN8P1602B Port/Pin I/O P0.0 I P1.0~P1.4 I/O P2.0~P2.7 I/O Function Description General-purpose input function External interrupt (INT0) Wakeup from power down mode General-purpose input/output function Wakeup from power down mode General-purpose input/output function Remark See <P00G1,P00G0> See <P00G1,P00G0> Level Change Note: The P1.4 enables when the external oscillator is RC type. I/O PORT MODE The port direction is programmed by PnM register. Port 0 is always input mode. Port 1 and Port 2 can select input or output direction. SN8P1602B 0C1H Bit 7 0 P1M Read/Write After reset - Bit 6 0 - Bit 5 0 - Bit 4 P14M R/W 0 Bit 3 P13M R/W 0 Bit 2 P12M R/W 0 Bit 1 P11M R/W 0 Bit 0 P10M R/W 0 SN8P1602B 0C2H Bit 7 P27M P2M Read/Write R/W After reset 0 Bit 6 P26M R/W 0 Bit 5 P25M R/W 0 Bit 4 P24M R/W 0 Bit 3 P23M R/W 0 Bit 2 P22M R/W 0 Bit 1 P21M R/W 0 Bit 0 P20M R/W 0 When PnM=0, the Pn is input mode PnM=1, the Pn is output mode Users can program them by bit control instructions (B0BSET, B0BCLR). Example: I/O mode selecting CLR CLR P1M P2M ; Set all ports to be input mode. MOV B0MOV B0MOV A, #0FFH P1M, A P2M, A ; Set all ports to be output mode. B0BCLR P1M.2 ; Set P1.2 to be input mode. B0BSET P1M.2 ; Set P1.2 to be output mode. SONiX TECHNOLOGY CO., LTD Page 61 Version 1.1 SN8P1602B 8-Bit Micro-Controller I/O PULL UP REGISTER SN8P1602B 0BEH Bit 7 PUR Read/Write After reset - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 PUR2 W 0 Bit 1 PUR1 W 0 Bit 0 PUR0 W 0 Example: I/O Pull up Register CLR PUR ; Disable all ports Pull-up register. MOV B0MOV A, #07H PUR, A ; Enable Port0, 1, 2 Pull-up register, ; I/O PORT DATA REGISTER SN8P1602B 0D0H Bit 7 P0 Read/Write After reset - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 P00 R 0 SN8P1602B 0D1H Bit 7 P1 Read/Write After reset - Bit 6 - Bit 5 - Bit 4 P14 R/W 0 Bit 3 P13 R/W 0 Bit 2 P12 R/W 0 Bit 1 P11 R/W 0 Bit 0 P10 R/W 0 SN8P1602B 0D2H Bit 7 P27 P2 Read/Write R/W After reset 0 Bit 6 P26 R/W 0 Bit 5 P25 R/W 0 Bit 4 P24 R/W 0 Bit 3 P23 R/W 0 Bit 2 P22 R/W 0 Bit 1 P21 R/W 0 Bit 0 P20 R/W 0 Example: Read data from input port. B0MOV A, P0 B0MOV A, P1 B0MOV A, P2 Example: Write data to output port. MOV A, #55H B0MOV P1, A B0MOV P2, A Example: Write one bit data to output port. B0BSET P1.3 B0BSET P2.5 B0BCLR B0BCLR Example: Port bit test. B0BTS1 B0BTS0 ; Read data from Port 0 ; Read data from Port 1 ; Read data from Port 2 ; Write data 55H to Port 1 and Port 2 ; Set P1.3 and P2.5 to be “1”. P1.3 P2.5 ; Set P1.3 and P2.5 to be “0”. P0.0 P1.2 ; Bit test 1 for P0.0 ; Bit test 0 for P1.2 SONiX TECHNOLOGY CO., LTD Page 62 Version 1.1 SN8P1602B 8-Bit Micro-Controller 11 CODING ISSUE TEMPLATE CODE ;******************************************************************************* ; FILENAME : TEMPLATE.ASM ; AUTHOR : SONiX ; PURPOSE : Template Code for SN8X16XX ; REVISION : 09/01/2002 V1.0 First issue ;******************************************************************************* ;* (c) Copyright 2002, SONiX TECHNOLOGY CO., LTD. ;******************************************************************************* CHIP SN8P1602B ; Select the CHIP ;------------------------------------------------------------------------------; Include Files ;------------------------------------------------------------------------------.nolist ; do not list the macro file INCLUDESTD INCLUDESTD INCLUDESTD MACRO1.H MACRO2.H MACRO3.H .list ; Enable the listing function ;------------------------------------------------------------------------------; Constants Definition ;------------------------------------------------------------------------------; ONE EQU 1 ;------------------------------------------------------------------------------; Variables Definition ;------------------------------------------------------------------------------.DATA org 0h ;Data section start from RAM address 0 Wk00 DS 1 ;Temporary buffer for main loop Iwk00 DS 1 ;Temporary buffer for ISR AccBuf DS 1 ;Accumulator buffer PflagBuf DS 1 ;PFLAG buffer ;------------------------------------------------------------------------------; Bit Variables Definition ;------------------------------------------------------------------------------Wk00B0 Iwk00B1 EQU EQU Wk00.0 Iwk00.1 SONiX TECHNOLOGY CO., LTD ;Bit 0 of Wk00 ;Bit 1 of Iwk00 Page 63 Version 1.1 SN8P1602B 8-Bit Micro-Controller ;------------------------------------------------------------------------------; Code section ;------------------------------------------------------------------------------.CODE ORG jmp 0 Reset ORG jmp 8 Isr ;Code section start ;Reset vector ;Address 4 to 7 are reserved ;Interrupt vector ORG 10h ;------------------------------------------------------------------------------; Program reset section ;------------------------------------------------------------------------------Reset: mov A,#07Fh ;Initial stack pointer and b0mov STKP,A ;disable global interrupt b0mov PFLAG,#00h ;pflag = x,x,x,x,x,c,dc,z mov A,#40h ;Clear watchdog timer and initial system mode b0mov OSCM,A call call b0bset ClrRAM SysInit FGIE ;Clear RAM ;System initial ;Enable global interrupt ;------------------------------------------------------------------------------; Main routine ;------------------------------------------------------------------------------Main: b0bset FWDRST ;Clear watchdog timer call MnApp jmp Main ;------------------------------------------------------------------------------; Main application ;------------------------------------------------------------------------------MnApp: ; Put your main program here ret ;----------------------------------; Jump table routine ;----------------------------------ORG 0x0100 ;The jump table should start from the head ;of boundary. b0mov A,Wk00 and A,#3 ADD PCL,A jmp JmpSub0 jmp JmpSub1 jmp JmpSub2 ;----------------------------------- SONiX TECHNOLOGY CO., LTD Page 64 Version 1.1 SN8P1602B 8-Bit Micro-Controller JmpSub0: ; Subroutine 1 jmp JmpExit JmpSub1: ; Subroutine 2 jmp JmpExit JmpSub2: ; Subroutine 3 jmp JmpExit JmpExit: ret ;Return Main ;------------------------------------------------------------------------------; Isr (Interrupt Service Routine) ; Arguments : ; Returns : ; Reg Change: ;------------------------------------------------------------------------------Isr: ;----------------------------------; Save ACC ;----------------------------------b0xch A,AccBuf b0mov b0mov A,PFLAG PflagBuf,A ;B0xch instruction do not change C,Z flag ;----------------------------------; Interrupt service routine ;----------------------------------b0bts0 jmp b0bts0 jmp FP00IRQ INT0isr FTC0IRQ TC0isr ;----------------------------------; Exit interrupt service routine ;----------------------------------IsrExit: b0mov b0mov b0xch A, PflagBuf PFLAG, A A,AccBuf reti SONiX TECHNOLOGY CO., LTD ;Restore the PFlag ;Restore the Reg. A ;B0xch instruction do not change C,Z flag ;Exit the interrupt routine Page 65 Version 1.1 SN8P1602B 8-Bit Micro-Controller ;------------------------------------------------------------------------------; INT0 interrupt service routine ;------------------------------------------------------------------------------INT0isr: b0bclr FP00IRQ ;Process P0.0 external interrupt here jmp IsrExit ;------------------------------------------------------------------------------; TC0 interrupt service routine ;------------------------------------------------------------------------------TC0isr: b0bclr FTC0IRQ ;Process TC0 interrupt here jmp IsrExit ;------------------------------------------------------------------------------; SysInit ; System initial to define Register, RAM, I/O, Timer...... ;------------------------------------------------------------------------------SysInit: ret ;------------------------------------------------------------------------------; ClrRAM ; Use index @YZ to clear RAM (00h~2Fh) ;------------------------------------------------------------------------------ClrRAM: clr b0mov ClrRAM10: clr decms jmp clr Y Z,#0x2f ; ;Set @YZ address from 2fh @YZ Z ClrRAM10 @YZ ;Clear @YZ content ;z = z – 1 , skip next if z=0 ;Clear address $00 ret ;------------------------------------------------------------------------------ENDP SONiX TECHNOLOGY CO., LTD Page 66 Version 1.1 SN8P1602B 8-Bit Micro-Controller PROGRAM CHECK LIST Item Undefined Bits Interrupt Non-Used I/O Sleep Mode Stack Buffer Description All bits those are marked as “0” (undefined bits) in system registers should be set “0” to avoid unpredicted system errors. Do not enable interrupt before initializing RAM. Non-used I/O ports should be set as output low mode or pull-up at input mode to save current consumption. Enable on-chip pull-up resistors of port 0 and port 1 to avoid unpredicted wakeup. Be careful of function call and interrupt service routine operation. Don’t let stack buffer overflow or underflow. 1. Write 0x7F into STKP register to initial stack pointer and disable global interrupt System Initial 2. Clear all RAM. 3. Initialize all system register even unused registers. 1. Enable OSG and High_Clk / 2 code option together 2. Enable noise filter code option in SN8P1602B. 3. Enable the watchdog option to protect system crash. Noisy Immunity 4. Non-used I/O ports should be set as output low mode 5. Constantly refresh important system registers and variables in RAM to avoid system crash by a high electrical fast transient noise. 6. Disable Low Power Function SONiX TECHNOLOGY CO., LTD Page 67 Version 1.1 SN8P1602B 8-Bit Micro-Controller 12 INSTRUCTION SET TABLE Field M O V E A R I T H M E T I C L O G I C P R O C E S S B R A N C H M I S C Mnemonic MOV A,M MOV M,A B0MOV A,M B0MOV M,A MOV A,I B0MOV M,I XCH A,M B0XCH A,M MOVC Description A←M M←A A ← M (bank 0) M (bank 0) ← A A←I M ← I, (M = only for Working registers R, Y, Z , RBANK & PFLAG) A ←→M A ←→M (bank 0) R, A ← ROM [Y,Z] C - DC - Z √ √ - Cycle 1 1 1 1 1 1 1 1 2 ADC ADC ADD ADD B0ADD ADD SBC SBC SUB SUB SUB DAA A,M M,A A,M M,A M,A A,I A,M M,A A,M M,A A,I A ← A + M + C, if occur carry, then C=1, else C=0 M ← A + M + C, if occur carry, then C=1, else C=0 A ← A + M, if occur carry, then C=1, else C=0 M ← A + M, if occur carry, then C=1, else C=0 M (bank 0) ← M (bank 0) + A, if occur carry, then C=1, else C=0 A ← A + I, if occur carry, then C=1, else C=0 A ← A - M - /C, if occur borrow, then C=0, else C=1 M ← A - M - /C, if occur borrow, then C=0, else C=1 A ← A - M, if occur borrow, then C=0, else C=1 M ← A - M, if occur borrow, then C=0, else C=1 A ← A - I, if occur borrow, then C=0, else C=1 To adjust ACC’s data format from HEX to DEC. √ √ √ √ √ √ √ √ √ √ √ - √ √ √ √ √ √ √ √ √ √ √ - 1 1 1 1 1 1 1 1 1 1 1 1 AND AND AND OR OR OR XOR XOR XOR A,M M,A A,I A,M M,A A,I A,M M,A A,I A ← A and M M ← A and M A ← A and I A ← A or M M ← A or M A ← A or I A ← A xor M M ← A xor M A ← A xor I √ √ √ √ √ √ √ √ √ √ √ √ - - 1 1 1 1 1 1 1 1 1 SWAP SWAPM RRC RRCM RLC RLCM CLR BCLR BSET B0BCLR B0BSET M M M M M M M M.b M.b M.b M.b A (b3~b0, b7~b4) ←M(b7~b4, b3~b0) M(b3~b0, b7~b4) ← M(b7~b4, b3~b0) A ← RRC M M ← RRC M A ← RLC M M ← RLC M M←0 M.b ← 0 M.b ← 1 M(bank 0).b ← 0 M(bank 0).b ← 1 √ √ √ √ - - √ √ √ √ √ √ √ √ √ - CMPRS CMPRS INCS INCMS DECS DECMS BTS0 BTS1 B0BTS0 B0BTS1 JMP CALL A,I A,M M M M M M.b M.b M.b M.b d d ZF,C ← A - I, If A = I, then skip next instruction ZF,C ← A – M, If A = M, then skip next instruction A ← M + 1, If A = 0, then skip next instruction M ← M + 1, If M = 0, then skip next instruction A ← M - 1, If A = 0, then skip next instruction M ← M - 1, If M = 0, then skip next instruction If M.b = 0, then skip next instruction If M.b = 1, then skip next instruction If M(bank 0).b = 0, then skip next instruction If M(bank 0).b = 1, then skip next instruction PC15/14 ← RomPages1/0, PC13~PC0 ← d Stack ← PC15~PC0, PC15/14 ← RomPages1/0, PC13~PC0 ← d √ √ - - √ √ - 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 2 2 PC ← Stack PC ← Stack, and to enable global interrupt PC ← Stack, and to load a value by PC+A No operation - - - 2 2 2 1 RET RETI RETLW NOP 1 1 1 1 1 1 1 1 1 1 1 Note: Any instruction that read/write from OSCM, will add an extra cycle. SONiX TECHNOLOGY CO., LTD Page 68 Version 1.1 SN8P1602B 8-Bit Micro-Controller 13 ELECTRICAL CHARACTERISTIC ABSOLUTE MAXIMUM RATING (All of the voltages referenced to Vss) Supply voltage (Vdd)………………………………………………………………………………………………… - 0.3V ~ 6.0V Input in voltage (Vin)……………………………………………………………………………………..Vss - 0.2V ~ Vdd + 0.2V Operating ambient temperature (Top)…………………………………………………………………………..-20°C ~ + 70°C Storage ambient temperature (Tstor)……………………………………………………………………………-30°C ~ + 125°C Power consumption (Pc)……………………………………………………………………………………………………500 mW STANDARD ELECTRICAL CHARACTERISTIC SN8P1602B (All of voltages referenced to Vss, Vdd = 5.0V, Fosc = 3.579545 MHz, ambient temperature is 25°C unless otherwise notice.) PARAMETER SYM. Operating voltage Vdd RAM Data Retention voltage Reset pin leakage current I/O port input leakage current Port1 output source current sink current Port2 output source current sink current INTn trigger pulse width Vdr ViL1 ViL2 ViL3 ViL4 ViH1 ViH2 ViH3 ViH4 Ilekg Ilekg IoH IoL IoH IoL Tint0 Oscillator Frequency Fhosc Input Low Voltage Input High Voltage Idd1 Idd2 Supply Current Idd3 Idd4 Idd5 LVD Detect Voltage Vdet DESCRIPTION Normal mode (OSG, Low Power Disable) Normal mode (OSG Enable, Low Power Disable) Normal mode (OSG Disable, Low Power Enable) Normal mode (OSG, Low Power Enable) Programming mode, Vpp = 12.5V MIN. 2.4 2.4 2.9 2.9 4.5 All input pins except those specified below Vss Input with Schmitt trigger buffer - Port0 Vss Reset pin ; Xin ( in RC mode ) Vss Xin ( in X’tal mode ) Vss All input pins except those specified below 0.7Vdd Input with Schmitt trigger buffer –Port0 0.8Vdd Reset pin ; Xin ( in RC mode ) 0.9Vdd Xin ( in X’tal mode ) 0.7Vdd Vin = Vdd Pull-up resistor disable, Vin = Vdd Vop = Vdd – 0.5V Vop = Vss + 0.5V Vop = Vdd – 0.5V Vop = Vss + 0.5V INT0 ~ INT2 interrupt request pulse width 2/fcpu Crystal type or ceramic resonator 32768 VDD = 3V, RC type for external mode VDD = 5V, RC type for external mode Vdd= 5V 4Mhz Run Mode Vdd= 3V 4Mhz (Low Power Disable) Vdd= 3V 32768Hz Vdd= 5V 4Mhz Run Mode (Low Power Enable) Vdd= 3V 4Mhz Vdd= 5V 32KHz Int. RC Slow mode (Stop High Clock) Vdd= 3V 16KHz Int. RC Vdd= 5V Sleep mode Vdd= 3V Vdd= 5V 32KHz Int. RC Green Mode (Stop High Clock) Vdd= 3V 16KHz Int. RC Low voltage detect level - TYP. 5.0 5.0 5.0 5.0 5.0 1.5 12 15 12 15 4M 6M 10M 3 1 50 2 0.8 25 7 1 0.6 15 3 1.8 MAX. 5.5 5.5 5.5 5.5 5.5 0.3Vdd 0.2Vdd 0.3Vdd 0.3Vdd Vdd Vdd Vdd Vdd 1 2 16M 8 2 100 5 2 50 20 2 1 30 10 - UNIT V V V V V V V V V V V V V V uA uA mA mA cycle Hz mA mA uA mA mA uA uA uA uA uA V Note: Date in Typical (TYP.) column is base on characterization results at 25℃. This data is design for guidance only and is not tested. SONiX TECHNOLOGY CO., LTD Page 69 Version 1.1 SN8P1602B 8-Bit Micro-Controller CHARACTERISTIC GRAPHS The Graphs in this section are for design guidance, not tested or guaranteed. In some graphs, the data presented are outside specified operating range. This is for information only and devices are guaranteed to operate properly only within the specified range. SN8P1602B VDD 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 2 Working area 4 8 12 Fosc 20 MHz 16 VDD 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 2 Figure 13-1Working Voltage vs. Frequency (OSG, Low Power, Noise Filter Disable) VDD 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 2 8 12 Fosc 20 MHz 16 4 8 12 Fosc 20 MHz 16 Figure 13-2 Working Voltage vs. Frequency (Noise Filter Enable, OSG, Low Power Disable) Working area 4 Working area Figure 13-3 Working Voltage vs. Frequency (Low Power Enable, OSG, Noise Filter Disable) VDD 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 2 Working area 4 8 12 Fosc 20 MHz 16 Figure 13-4 Working Voltage vs. Frequency (OSG Enable, Noise filter, Low Power Disable) uA 2.0 uA 30 25 1.5 20 1.0 15 10 0.5 5 VDD 0.0 2.0 2.5 3.0 3.5 4.0 4.5 VDD 0 5.0 2.0 Figure 13-5 Typical Stop Mode current (Idd4) vs. VDD 2.5 3.0 3.5 4.0 4.5 5.0 Figure 13-6 Typical Slow Mode current (Idd3) vs. VDD (Stop High Clock) SONiX TECHNOLOGY CO., LTD Page 70 Version 1.1 SN8P1602B 8-Bit Micro-Controller mA mA 10 10 8 8 5V 5V 6 6 4 4 3V 2 3V 2 0 2 6 10 14 18 0 Fosc MHz 2 6 10 14 Fosc MHz 18 Figure 13-7 Typical Run Mode current (Idd1) vs. Fosc Figure 13-8 Typical Run Mode current (Idd2) vs. Fosc (Low Power Disable) (Low Power Enable) mA uA 16 4.0 14 5V 12 3.0 10 8 2.0 6 3V 4 1.0 2 0.0 2 6 10 14 18 VDD 0 Fosc MHz 2.0 Figure 13-9 Typical Green Mode current vs. Fosc (Without Stopping High clock) 2.5 3.0 3.5 4.0 4.5 5.0 Figure 13-10 Typical Green Mode current vs. VDD (Stop High clock) mA mA -14 16 -12 14 -10 12 10 -8 8 -6 6 -4 4 -2 2 VDD 0 2.0 2.5 3.0 3.5 4.0 4.5 2.0 5.0 Figure 13-11 Typical IOH vs. VDD SONiX TECHNOLOGY CO., LTD VDD 0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 13-12 Typical IOL vs. VDD Page 71 Version 1.1 SN8P1602B 8-Bit Micro-Controller Fosc KHz 30 25 20 15 10 5 VDD 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 13-13 Typical Slow Mode Frequency vs. VDD SONiX TECHNOLOGY CO., LTD Page 72 Version 1.1 SN8P1602B 8-Bit Micro-Controller 14 PACKAGE INFORMATION P-DIP 18 PIN SYMBOLS A A1 A2 D E E1 L ｅB θ° MIN NOR MAX MIN (inch) 0.015 0.125 0.880 0.245 0.115 0.335 0° SONiX TECHNOLOGY CO., LTD 0.130 0.900 0.300 0.250 0.130 0.355 7° NOR MAX (mm) 0.210 0.135 0.920 0.381 3.175 22.352 0.255 0.150 0.375 15° 6.223 2.921 8.509 0° Page 73 3.302 22.860 7.620 6.350 3.302 9.017 7° 5.334 3.429 23.368 6.477 3.810 9.525 15° Version 1.1 SN8P1602B 8-Bit Micro-Controller SOP 18 PIN SYMBOLS A A1 D E H L θ° MIN NOR MAX MIN (inch) 0.093 0.004 0.447 0.291 0.394 0.016 0° SONiX TECHNOLOGY CO., LTD 0.099 0.008 0.455 0.295 0.407 0.033 4° NOR MAX (mm) 0.104 0.012 0.463 0.299 0.419 0.050 8° Page 74 2.362 0.102 11.354 7.391 10.008 0.406 0° 2.502 0.203 11.557 7.493 10.325 0.838 4° 2.642 0.305 11.760 7.595 10.643 1.270 8° Version 1.1 SN8P1602B 8-Bit Micro-Controller SSOP 20 PIN SYMBOLS A A1 A2 b c D E E1 [e] h L L1 ZD Y θ° MIN NOR MAX MIN (inch) 0.053 0.004 0.008 0.007 0.337 0.228 0.150 0.010 0.016 0.039 0° SONiX TECHNOLOGY CO., LTD 0.063 0.006 0.010 0.008 0.341 0.236 0.154 0.025 0.017 0.025 0.041 0.059 - NOR MAX (mm) 0.069 0.010 0.059 0.012 0.010 0.344 0.244 0.157 1.350 0.100 0.200 0.180 8.560 5.800 3.800 0.020 0.050 0.043 0.250 0.400 1.000 0.004 8° 0° Page 75 1.600 0.150 0.254 0.203 8.660 6.000 3.900 0.635 0.420 0.635 1.050 1.500 - 1.750 0.250 1.500 0.300 0.250 8.740 6.200 4.000 0.500 1.270 1.100 0.100 8° Version 1.1 SN8P1602B 8-Bit Micro-Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part. Main Office: Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C. Tel: 886-3-551 0520 Fax: 886-3-551 0523 Taipei Office: Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C. Tel: 886-2-2759 1980 Fax: 886-2-2759 8180 Hong Kong Office: Address: Flat 3 9/F Energy Plaza 92 Granville Road, Tsimshatsui East Kowloon. Tel: 852-2723 8086 Fax: 852-2723 9179 Technical Support by Email: [email protected] SONiX TECHNOLOGY CO., LTD Page 76 Version 1.1