CXA1884N Low-voltage FM IF Amplifier Description The CXA1884N is designed for FM communication devices. They incorporate a paging system, mixer, IF limiter, FM detector, operational amplifier, comparator, and others. 20 pin SSOP (Plastic) Features • Low operating voltage 1.0 to 4.0V • Low power consumption 2mA at 1.5V • Built-in power source voltage monitor Applications IF Amplifier for Paging System Receiver Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C) • Supply voltage Vcc 7 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –65 to +150 V °C °C Recommended Operating Conditions Supply voltage Vcc 1.0 to 4.0 V RF IN GND LVA BSV VB OUT SENSE NRZ COMP IN A2 IN A1 OUT Block Diagram and Pin Configuration 20 19 18 17 16 15 14 13 12 11 MIXER ERR. AMP REG. A2 A1 IF LIM. QUAD DET. 1 2 3 4 5 6 7 8 9 10 OSC1 OSC2 MIX OUT VCC IF IN IF P1 IF P2 QD DET OUT A1 IN OSC Note) DET. : DETECTOR LIM. : LIMITER REG. : REGURATOR ERR. : ERROR CORRECTION Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97Z05A8Y CXA1884N Pin Description Pin No. Symbol Equivalent circuit Description VCC 1 OSC1 1 2 2 OSC2 GND Those pins are connected to the external parts of an oscillating circuit. The oscillator is an internally-biased Colpitts type with the collector, base, and emitter connections at Vcc, pins 1 and 2 respectively. VCC 3 3 Mixer output pin. Connect a 455kHz ceramic filter between this pin and the IF IN pin. MIX OUT GND 4 VCC 5 IF IN Vcc pin. Input pin for the IF limiter amplifier. VCC Connection pin of the bypass capacitor for the IF limiter amplifier. Connect a capacitor of about 0.047µF between this pin and ground (or Vcc). 5 6 IF P1 6 GND VCC 7 IF P2 Connection pin of the bypass capacitor for the IF limiter amplifier. Connect a capacitor of about 0.047µF between this pin and ground (or Vcc). 7 GND VCC 8 QD 8 Connected to a quadrature detector phase shifter. GND –2– CXA1884N Pin No. Symbol Equivalent circuit Description VCC 9 9 DET OUT Recovered signal output. GND VCC 10 A1 IN Input pin of inverting OP amplifier A1. 10 GND VCC 11 A1 OUT Output pin of OP amplifier A1. 11 GND VCC 12 A2 IN Input pin of OP amplifier A2. 12 GND VCC 13 COMP IN Input pin of the comparator. This pin is internally connected to the output of OP amplifier A2. 13 GND –3– CXA1884N Pin No. Symbol Equivalent circuit Description 14 14 NRZ (Non Return Zero) output pin. NRZ GND VCC 15 SENSE Voltage control pin for external bias supply. 15 GND VCC 16 VB OUT Supplies bias voltage to external circuit transistors and others. 16 GND 17 17 Reduces IC power consumption. Lowering pin voltage beiow 0.35V stops IC operation. BSV GND 18 18 Output pin for Low Voltage Alarm (LVA). The pin turns to high impedance when power voltage drops below 1.05V. LVA GND 19 Ground pin. GND VCC 20 RF IN Mixer input pin. 20 GND –4– CXA1884N Electrical Characteristics (VCC = 1.5V, Ta = 25°C, fs = 21.7MHz, fMOD = 256Hz, fDIV = 2.3kHz, AMMOD = 30%) Item Symbol Condition Min. Typ. Max. Unit Power consumption (during operation) ICC Test circuit 1 1.2 2.0 2.6 mA Power consumption (during battery saving) ICCS Test circuit 1 VI = 0.3V — — 20 µA Input for –3dB Limiting VIN (LIM) Test circuit 3 — 7 — dBµ AM rejection ratio AMRR VIN = 60dBµ Test circuit 3 25 — — dB OP amplifier input bias current IBIAS Test circuit 2 — 30 100 nA OP amplifier open loop gain AV Test ciTcuit 4 45 60 — dB OP amplifier output voltage amplitude VO Test circuit 5 0.25 — — Vp-p Comparator hysteresis width NRZ∗ output leak current VTW Test circuit 6 30 40 50 mV ILNRZ Test circuit 7 — — 5.0 µA NRZ∗ saturation voltage VSATNRZ ISINK = 200µA Test circuit 8 — — 0.4 V VB output current IOUT VB = 0.9V 0.1 — — mA VB output voltage VBOUT Test circuit 9 0.95 — — V Sense voltage VSEN Test circuit 2 85 100 115 mV LVA threshold voltage VPML Test circuit 10 1.00 1.05 1.10 V LVA hysteresis width VPMTH VPMH – VPML 35 50 70 mV LVA output leak current ILLVA Test circuit 7 — — 5.0 µA LVA saturation voltage VSATLVA Test circuit 8 — — 0.4 V Recovered signal voltage VDET Test circuit 3 10 — — mVrms BSV high level VTHBSV 0.95 — — V BSV low level VTLBSV — — 0.35 V ∗ NRZ: Non Return Zero –5– CXA1884N Electrical Characteristics Test Circuit VCC 1.5V 1 20 1 20 2 19 2 19 3 18 3 18 4 17 4 17 5 16 5 16 6 15 6 15 7 14 7 14 8 13 8 13 9 12 10 11 VI 0.95V VCC 1.5V 9 12 10 11 VI 0.95V 7.5k 1k RNF1 100k RNF2 100k Test circuit 1 22p 15p CF1 455k CP1 0.047µ CP2 0.047µ 4.7k VCC 1.5V Vo Test circuit 2 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 C IN 1 100p RL 50 VI 0.95V V IN 1 21.7MHz VCC 1.5V C IN 2 10µ RNF2 10k 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 Test circuit 3 20 R IN 1 10k C IN 1 10µ V IN 1 0.1Vp-p 1 20 2 19 2 19 3 18 3 18 4 17 4 17 5 16 5 16 VI 0.95V 6 15 6 15 7 14 7 14 8 13 8 13 9 12 10 11 V IN1 7V 9 12 10 11 Vo VCC 1.5V Test circuit 5 RNF1 10k Test circuit 4 1 V IN2 0.1V VI 0.95V RNF2 10k V IN 2 0.1Vp-p VCC 1.5V 1 –6– Test circuit 6 VI 0.95V CP (C) RNF 10k V IN 0.2 to 0.3V RL 10k CXA1884N VCC 1.5V 1 20 1 20 2 19 2 19 3 18 3 18 4 17 4 17 5 16 6 15 5 16 6 15 7 14 8 13 9 12 10 11 VI 0.95V VCC 1.5V 14 8 13 9 12 10 VCC 1.5V Test circuit 7 VCC 1.5V 7 20 1 20 19 2 19 3 18 3 18 4 17 4 17 5 16 5 16 6 15 15 7 14 IS VS 0.15V 200µA 7 14 13 8 13 8 9 12 9 12 10 11 10 11 VCC 1.5V Test circuit 9 Test circuit 10 –7– IS1 200µA VI 0.3V Test circuit 8 2 6 IS2 200µA RNF 10k 11 1 VI 0.95V VI 0.95V CP (C) VI 0.95V CXA1884N Test Method Input for –3dB Limiting VIN (LIM) Use test circuit 3. Apply a signal with the following characteristics to SIG IN. Signal frequency: fs = 21.7MHz Modulation frequency: fMOD = 256Hz Frequency deviation: fDIV = 2.3kHz Signal level: VL = 40dBµ Here, the value of VAC is specified as VAC1. Next, the signal level VL is changed to 19dBµ and VAC value is hence specified as VAC2. 20 log VAC1 < 3dB VAC2 AM rejection ratio (AMRR) Use test circuit 3. Apply a signal with the following characteristics to SIG IN. Signal frequency: fs = 21.7MHz Modulation frequency: fMOD = 256Hz Frequency deviation: fDIV = 2.3kHz Signal level: VL = 40dBµ Here, the value of VAC is specified as VAC1. Next, AM is modified to: Modulation ratio: AMMOD = 30% Modulation frequency: fMOD = 256Hz and the VAC value is hence specified as VAC2. AMRR = 20 log VAC1 VAC2 > 25dB Recovered signal voltage VDET Use test circuit 3. Apply a signal with the following characteristics to SIG IN. Signal frequency: fs = 21.7MHz Modulation frequency: fMOD = 256Hz Frequency deviation: fDIV = 2.3kHz Signal level: VL = 50dBµ Here, the value of the Pin 9 output voltage is expressed as VDET. OP amplifier output voltage amplitude VO Use test circuit 5. If output voltage V is expressed as V1 when VIN is 0.1V, and as V2 when VIN is 0.3V, it follows that: VO = V1 – V2 Comparator hysteresis width VTW Use test circuit 6. Vary VIN between 0.1 to 0.3V. Specify VIN voltage, as V1 when (C) voltage changes from low to high. Similarly, specify VIN voltage as V2, when (C) voltage changes from high to low. Therefore: VHY VTW = V1 – V2 LVA threshold voltage VPML and recovery voltage VPMH Use test circuit 10. Vary power voltage Vcc from 1.3 to 0.95V. Specify Vcc as VPML, when (C) voltage changes from low to high. Similarly, specify Vcc as VPMH, when (C) voltage changes from high to low. –8– CXA1884N Design Reference Values (Ta = 25°C, Vcc = 1.4V) Symbol Item Condition Min. Typ. Max. Unit Mixer input resistance RIN (MIX) 1.3 1.6 1.9 kΩ Mixer input capacity CIN (MIX) — 4.0 — pF Mixer output resistance ROUT (MIX) 1.44 1.8 2.16 kΩ IF input resistance RIN (IF) 1.44 1.8 2.16 kΩ IF gain stability GN (IF) — ±6 — dB Detector output resistance ROUT (QD) 1.28 1.6 2.0 kΩ OP amplifier max. input voltage VINMAX — — 0.39 V OP amplifier min. input voltage VINMIN 0.05 — — V Comparator max. input voltage VINMAXCOMP — — 0.39 V Comparator min. input voltage VINMINCOMP 0.05 — — V OP amplifier off-set voltage VOFS — — 3 mV Ta = –20 to +60°C Application Circuit TO RF AMP TO 1ST MIX TO 2nd MIX BATT.S DATA AUDIO LVA VCC 6.8k 27k 19 20 0.1µ 18 17 16 R5 C4 56k 68k 13 14 15 12 ERR MIXER A1 3 4 5 6 15p 9 8 7 4.7k 22p 20.945MHz DET LIM OSC 2 11 A2 REG 1 C3 R4 R6 4.7µ (BP) or 1µ 10 R1 C2 R3 R2 0.047µ 0.047µ 1µ CFVM455 C1 CDB455C3 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –9– CXA1884N 1) Supply This IC incorporates a regulation and is designed to operate steadily on a wide range of supply voltage from 1.0 to 4.0V. Decoupling on the wiring to the supply pin (Pin 4) should be done as close to the pin as possible. 2) Oscillation input Oscillation input method (a) Using Pins 1 and 2, input self-excited oscillation signals through the composition of a Colpitts type crystal oscillating circuit. (b) Input local oscillation signals to Pin 1 directly. 1 2 1 3 2 Ceramic filter 3 Ceramic filter VCC From LOCAL SIG (a) (b) Fig. 1 3) Mixer This IC's mixer is of the double balance type. Pin 24 is the input pin. Input through a suitable alignment circuit. Input impedance is at 1.6kΩ. The mixer output features a built-in 1.6kΩ Ioad resistance at Pin 3. 4) IF filter The filter to be connected between this IC's mixer and the IF limiter should have the following specifications. I/O impedance: 1.6kΩ ± 10% Band width: Use according to application – 10 – CXA1884N 5) IF limiter The IF limiter of this IC features a gain of about 100dB. To this effect, the following points should be considered for the wiring connecting IF limiter input pin (Pin 5) and decoupling capacitor pins (Pins 6 and 7). (a) Wiring to mixer output (Pin 3) and IF limiter input (Pin 5) should be as short and as far apart as possible to avoid neutral interference. (b) Connect a decoupling capacitor to IF limiter IF P1 (Pin 6) and IF P2 (Pin 7). Here the decoupling capacitor should be positioned as close as possible to each pin and the wiring be as short as can be. (c) As IF limiter output shows at QD (Pin 8), keep the wiring connected to QD pin R, L, C and the ceramic discriminator as short as possible. Interference to the mixer output, IF limiter input and others must be kept to a minimum. 3 4 5 6 8 7 VCC Wiring as short and as far apart as possible As short as possible Fig. 2 6) Detector The detector is of the quadrature type. To phase shift, either R, L, C resonance circuit or the ceramic discriminator is connected to Pin 8. The phase capacitor of the quadrature detector is built-in. FM (FSK) signals demodulated by this detector have their high frequency components dropped by the LPF formed inside from CRs, to be output at DET OUT (Pin 9). DET OUT output impedance is about 3kΩ. For the CXA1884N ceramic discriminator, CDB 455 C3 (Murata Production) is recommended. 7 8 7 9 8 DET OUTPUT 9 DET OUTPUT 4.7k Coil Ceramic discriminator CDB 455 C3 VCC VCC (a) Coil (b) Ceramic discriminator Fig. 3 – 11 – CXA1884N 7) OP AMP, NRZ OUT This IC has 2 built-in operation amplifiers. One of these operation amplifiers is connected inside the IC to NRZ comparator. 12 13 14 11 0.2V 10 Fig. 4 Making use of these operation amplifiers an LPF or the sort is made up to eliminate noise during signal demodulation and input to the following NRZ comparator. NRZ comparator molds the waveform of input signals to output them as square waves. NRZ comparator output is an open collector. Accordingly as CPU is a CMOS, in case the supply voltage differs, by following the method indicated in Fig. 5 direct interfacing becomes possible. VCC 1.5V VCC 4 VCC for CMOS IC 14 CMOS IC NRZ OUT Fig. 5 8) VB SENSE, VB OUT This controls the base bias of the external transistor. Pin 16 VB OUT can be used as the previous amplifier 1st mixer bias. 9) LVA OUT When supply voltage turns low this pin turns to High (Open). Output is an open collector, and similarly as NRX OUT, can directly drive CMOS. This LVA setting voltage is at 1.05V ± 50mV with hysterisis versus supply voltage. Hysterisis width is at 50mV ± 10mV. – 12 – CXA1884N 10) BSV By turning this pin to low, this IC's operation can be stopped. This pin can also be directly connected to CMOS. Consumption current with BSV is 20µA (at 1.5V) and below. 17 BSV Fig. 6 – 13 – CXA1884N Mixer input signal vs. Output characteristics Input sensitivity 0 S+D+N 4. Length Butterworth Cascade MFB (G = 4) 1µ 33k 68k Output characteristics [dB] –10 9 12k 24k 2200p 22k A2 A1 33k 0.01µ –20 470p 0.01µ 200mV 200mV –30 1000p 1.8µH D+N S+D+N –50 –60 20 MIX fC = 1.5kHz, K = L67 (–3dB) –40 13 VCC = 1.5V, fMOD = 1kHz fDEV = ±3kHz, fS = 21.7MHz N –120 –110 –100 –90 –80 –70 –60 –50 –40 Mixer input signal level [dBm] –30 –20 –10 0 4th LP Butterworth cascade MFB constant using OP1 and OP2 inside CXA1884N R2 R1 R3 9 R5 C2 R4 R6 C4 A1 C1 200mV A2 C3 200mV fMOD 256Hz fc (–3dB) 400Hz A1 Gain 1 A2 Gain 4 R1 47kΩ R2 47kΩ R3 22kΩ R4 47kΩ R5 180kΩ R6 33kΩ C1 0.012µF C2 680pF C3 0.015µF C4 1200pF – 14 – 13 CXA1884N Supply voltage vs. Consumption current Logical input level vs. Mixer conversion 20 Mixer conversion level [dB] ICC – Consumption current [mA] 4.0 3.0 2.0 1.0 2.0 3.0 VCC – Supply voltage [V] 4.0 Conversion gain [dB] Input frequency vs. Conversion gain 10 0 LOCAL INPUT LEVEL = –10dBm –10 1M 10M Input frequency [Hz] 100M – 15 – 10 0 f = 21.245MHz –10 A RF IN –20 B –30 OSC IN –40 Test the ratio between A and B. 0 –30 –20 –10 10 Logical input level [dBm] 20 CXA1884N Package Outline Unit: mm 20PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗6.5 ± 0.1 0.1 11 20 1 6.4 ± 0.2 ∗4.4 ± 0.1 A 10 + 0.05 0.15 – 0.02 0.65 + 0.1 0.22 – 0.05 0.13 M 0.5 ± 0.2 0.1 ± 0.1 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER / PALLADIUM PLATING SONY CODE SSOP-20P-L01 LEAD TREATMENT EIAJ CODE SSOP020-P-0044 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 16 –